Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1914184	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2133470

1

T1

103

T2

102

T3

322

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3700321	1			T1	105		T2	93		T3	289
values[0x0]	172949	1			T1	47		T2	37		T3	87
values[0x1]	174384	1			T1	48		T2	27		T3	113

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1520925	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2526729

1

T1

112

T2

114

T3

367

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11447	1			T1	1		T3	1		T11	5
valid_sources[0x01]	11195	1			T3	1		T11	4		T28	4
valid_sources[0x02]	11360	1			T3	1		T9	114		T11	6
valid_sources[0x03]	13952	1			T1	1		T11	3		T22	6
valid_sources[0x04]	11631	1			T3	2		T11	8		T22	1
valid_sources[0x05]	12698	1			T1	1		T3	3		T11	3
valid_sources[0x06]	11816	1			T1	1		T3	1		T11	3
valid_sources[0x07]	14271	1			T3	4		T11	3		T12	10
valid_sources[0x08]	11703	1			T1	2		T3	1		T11	7
valid_sources[0x09]	11354	1			T3	2		T9	60		T11	7
valid_sources[0x0a]	11489	1			T3	2		T11	2		T22	11
valid_sources[0x0b]	11010	1			T3	3		T11	5		T22	6
valid_sources[0x0c]	15536	1			T1	2		T3	1		T9	106
valid_sources[0x0d]	77623	1			T1	1		T11	5		T12	1
valid_sources[0x0e]	17430	1			T1	2		T3	3		T4	2
valid_sources[0x0f]	10962	1			T1	1		T9	22		T11	4
valid_sources[0x10]	12593	1			T3	1		T9	32		T11	1
valid_sources[0x11]	11366	1			T9	14		T11	6		T12	5
valid_sources[0x12]	14611	1			T11	11		T22	4		T20	1
valid_sources[0x13]	13019	1			T3	5		T11	10		T12	1
valid_sources[0x14]	11904	1			T3	1		T9	8		T11	10
valid_sources[0x15]	16489	1			T1	1		T3	1		T11	3
valid_sources[0x16]	11686	1			T3	2		T11	9		T12	3
valid_sources[0x17]	11388	1			T3	1		T11	3		T12	14
valid_sources[0x18]	11212	1			T3	3		T11	9		T12	4
valid_sources[0x19]	11114	1			T1	3		T3	1		T11	2
valid_sources[0x1a]	11266	1			T1	1		T3	1		T11	6
valid_sources[0x1b]	12560	1			T1	2		T3	5		T11	10
valid_sources[0x1c]	11606	1			T3	1		T11	3		T12	7
valid_sources[0x1d]	12823	1			T1	1		T3	1		T11	6
valid_sources[0x1e]	11557	1			T1	2		T3	2		T11	12
valid_sources[0x1f]	12455	1			T3	1		T11	6		T12	8
valid_sources[0x20]	14880	1			T3	2		T11	8		T12	6
valid_sources[0x21]	11201	1			T3	1		T11	10		T12	4
valid_sources[0x22]	100451	1			T11	7		T12	1		T22	2
valid_sources[0x23]	14459	1			T11	1		T12	22		T22	7
valid_sources[0x24]	11509	1			T1	1		T3	4		T11	10
valid_sources[0x25]	11536	1			T1	4		T3	2		T11	8
valid_sources[0x26]	11191	1			T1	3		T11	9		T12	3
valid_sources[0x27]	11237	1			T11	3		T12	18		T22	3
valid_sources[0x28]	14170	1			T3	3		T4	2		T11	5
valid_sources[0x29]	69196	1			T3	1		T11	7		T12	7
valid_sources[0x2a]	11127	1			T1	2		T3	2		T11	3
valid_sources[0x2b]	13553	1			T3	4		T11	4		T12	10
valid_sources[0x2c]	11377	1			T3	1		T4	5		T9	5
valid_sources[0x2d]	13187	1			T3	1		T11	4		T12	9
valid_sources[0x2e]	35144	1			T1	3		T3	1		T11	2
valid_sources[0x2f]	12720	1			T11	7		T12	6		T22	7
valid_sources[0x30]	11917	1			T3	1		T4	3		T11	12
valid_sources[0x31]	12575	1			T11	5		T12	17		T22	1
valid_sources[0x32]	14114	1			T1	2		T11	4		T12	8
valid_sources[0x33]	12061	1			T1	1		T3	2		T11	4
valid_sources[0x34]	11536	1			T1	1		T3	1		T4	7
valid_sources[0x35]	14841	1			T11	2		T12	1		T22	5
valid_sources[0x36]	98833	1			T1	1		T3	3		T11	7
valid_sources[0x37]	18575	1			T1	3		T11	4		T12	5
valid_sources[0x38]	12707	1			T3	3		T11	8		T22	4
valid_sources[0x39]	11176	1			T3	4		T9	1		T11	6
valid_sources[0x3a]	11505	1			T1	2		T3	3		T4	2
valid_sources[0x3b]	10866	1			T3	1		T11	6		T12	3
valid_sources[0x3c]	11064	1			T3	2		T4	9		T11	8
valid_sources[0x3d]	10864	1			T3	2		T11	11		T12	3
valid_sources[0x3e]	11251	1			T3	4		T11	2		T12	6
valid_sources[0x3f]	11972	1			T11	4		T20	14		T15	6
valid_sources[0x40]	11642	1			T1	1		T11	6		T12	6
valid_sources[0x41]	11377	1			T11	11		T22	9		T20	2
valid_sources[0x42]	11166	1			T1	2		T3	3		T11	3
valid_sources[0x43]	15820	1			T3	1		T11	3		T12	1
valid_sources[0x44]	14515	1			T1	1		T3	2		T11	3
valid_sources[0x45]	13335	1			T3	2		T9	111		T11	2
valid_sources[0x46]	12356	1			T3	3		T11	9		T28	2
valid_sources[0x47]	10757	1			T1	1		T4	1		T11	4
valid_sources[0x48]	11443	1			T1	1		T3	5		T11	3
valid_sources[0x49]	12078	1			T3	2		T11	10		T12	2
valid_sources[0x4a]	34086	1			T3	1		T9	89		T11	5
valid_sources[0x4b]	66509	1			T1	3		T3	3		T9	34
valid_sources[0x4c]	11595	1			T11	9		T12	7		T28	9
valid_sources[0x4d]	11428	1			T3	3		T11	7		T12	2
valid_sources[0x4e]	11092	1			T1	1		T3	1		T11	8
valid_sources[0x4f]	11593	1			T1	1		T3	1		T11	6
valid_sources[0x50]	11726	1			T3	2		T11	2		T12	29
valid_sources[0x51]	15521	1			T3	2		T11	5		T22	6
valid_sources[0x52]	11222	1			T1	1		T3	2		T11	16
valid_sources[0x53]	11398	1			T3	4		T11	5		T12	8
valid_sources[0x54]	17689	1			T11	5		T13	6670		T22	8
valid_sources[0x55]	11782	1			T1	2		T3	4		T4	2
valid_sources[0x56]	13202	1			T3	2		T11	8		T12	33
valid_sources[0x57]	11496	1			T3	2		T11	2		T12	4
valid_sources[0x58]	11245	1			T1	1		T3	4		T11	5
valid_sources[0x59]	13153	1			T11	5		T12	4		T22	1
valid_sources[0x5a]	13733	1			T3	4		T11	5		T12	2
valid_sources[0x5b]	30047	1			T1	1		T3	2		T11	7
valid_sources[0x5c]	14798	1			T1	1		T3	4		T11	8
valid_sources[0x5d]	11555	1			T1	1		T3	1		T11	3
valid_sources[0x5e]	11562	1			T3	4		T11	5		T12	2
valid_sources[0x5f]	12405	1			T11	3		T12	15		T22	3
valid_sources[0x60]	11286	1			T1	2		T3	3		T11	8
valid_sources[0x61]	11913	1			T1	2		T3	2		T11	7
valid_sources[0x62]	63004	1			T1	5		T3	2		T11	6
valid_sources[0x63]	16965	1			T3	3		T11	5		T22	4
valid_sources[0x64]	11127	1			T1	1		T11	8		T12	3
valid_sources[0x65]	13876	1			T1	1		T3	1		T11	7
valid_sources[0x66]	12041	1			T1	1		T3	2		T11	4
valid_sources[0x67]	11435	1			T1	1		T3	3		T4	16
valid_sources[0x68]	11249	1			T3	3		T11	4		T22	5
valid_sources[0x69]	11266	1			T3	2		T4	2		T11	16
valid_sources[0x6a]	11197	1			T1	3		T3	1		T11	1
valid_sources[0x6b]	11503	1			T1	3		T3	1		T11	7
valid_sources[0x6c]	11917	1			T3	4		T11	4		T12	10
valid_sources[0x6d]	14794	1			T4	6		T11	4		T22	4
valid_sources[0x6e]	12606	1			T3	1		T11	7		T12	2
valid_sources[0x6f]	11109	1			T3	1		T11	5		T22	2
valid_sources[0x70]	11058	1			T1	1		T3	1		T11	4
valid_sources[0x71]	13076	1			T1	1		T3	4		T11	6
valid_sources[0x72]	11211	1			T3	1		T11	6		T12	1
valid_sources[0x73]	11664	1			T1	2		T3	2		T4	3
valid_sources[0x74]	27207	1			T4	3		T11	6		T22	4
valid_sources[0x75]	11333	1			T3	3		T4	2		T11	1
valid_sources[0x76]	11921	1			T3	3		T10	191		T11	5
valid_sources[0x77]	11661	1			T1	1		T11	2		T12	16
valid_sources[0x78]	11057	1			T3	3		T11	5		T12	1
valid_sources[0x79]	12439	1			T1	1		T3	2		T4	3
valid_sources[0x7a]	12489	1			T1	1		T4	1		T11	6
valid_sources[0x7b]	11019	1			T1	1		T3	3		T11	8
valid_sources[0x7c]	11091	1			T3	2		T11	10		T22	3
valid_sources[0x7d]	15143	1			T1	1		T3	4		T9	8
valid_sources[0x7e]	12126	1			T1	3		T4	10		T11	14
valid_sources[0x7f]	91242	1			T1	1		T3	3		T11	6
valid_sources[0x80]	16228	1			T1	1		T3	1		T11	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1834540

1

T1

56

T2

47

T3

150

values[0x0]

all_enables

biggest_size

149805

1

T1

27

T2

34

T3

77

values[0x1]

all_enables

biggest_size

149125

1

T1

20

T2

21

T3

95