Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	114483078	15057	0	0
claim_transition_if_regwen_rd_A	114483078	1215	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114483078	15057	0	0
T43	0	5	0	0
T44	0	13	0	0
T52	0	3	0	0
T53	0	2	0	0
T56	0	16	0	0
T62	1755	0	0	0
T63	5154	0	0	0
T65	16025	0	0	0
T75	0	12	0	0
T90	387947	6	0	0
T91	0	1	0	0
T104	0	9	0	0
T146	0	4	0	0
T147	2833	0	0	0
T148	27241	0	0	0
T149	28604	0	0	0
T150	27164	0	0	0
T151	31588	0	0	0
T152	80369	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114483078	1215	0	0
T42	248891	0	0	0
T91	327297	2	0	0
T111	0	14	0	0
T116	0	14	0	0
T129	0	15	0	0
T135	0	15	0	0
T153	0	59	0	0
T154	0	110	0	0
T155	0	13	0	0
T156	0	15	0	0
T157	0	7	0	0
T158	1045	0	0	0
T159	22800	0	0	0
T160	31058	0	0	0
T161	7383	0	0	0
T162	4794	0	0	0
T163	6296	0	0	0
T164	23132	0	0	0
T165	41455	0	0	0