Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1717352	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1942371

1

T1

17

T2

2159

T3

1056

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3305830	1			T1	27		T2	3448		T3	1083
values[0x0]	176125	1			T1	2		T2	330		T3	313
values[0x1]	177768	1			T1	6		T2	313		T3	311

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1363512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2296211

1

T1

23

T2

2571

T3

1209

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11382	1			T3	5		T10	8		T11	4
valid_sources[0x01]	10834	1			T3	9		T10	6		T11	1
valid_sources[0x02]	11119	1			T3	15		T10	12		T11	4
valid_sources[0x03]	11200	1			T3	9		T10	4		T11	3
valid_sources[0x04]	12795	1			T3	6		T10	6		T11	2
valid_sources[0x05]	11443	1			T3	3		T10	4		T11	11
valid_sources[0x06]	11009	1			T3	4		T10	5		T11	4
valid_sources[0x07]	10742	1			T3	10		T10	8		T11	13
valid_sources[0x08]	11901	1			T3	3		T10	10		T61	1
valid_sources[0x09]	11114	1			T3	2		T10	1		T11	5
valid_sources[0x0a]	11394	1			T3	5		T10	2		T6	3
valid_sources[0x0b]	11755	1			T10	5		T11	12		T6	5
valid_sources[0x0c]	11277	1			T3	4		T10	12		T11	4
valid_sources[0x0d]	10697	1			T3	5		T10	3		T11	11
valid_sources[0x0e]	11058	1			T3	13		T10	7		T11	4
valid_sources[0x0f]	11163	1			T3	8		T10	6		T11	11
valid_sources[0x10]	10816	1			T3	15		T10	4		T11	2
valid_sources[0x11]	14606	1			T3	8		T10	1		T11	8
valid_sources[0x12]	12612	1			T3	6		T10	8		T11	2
valid_sources[0x13]	11617	1			T3	8		T10	5		T11	3
valid_sources[0x14]	12380	1			T3	2		T10	3		T11	6
valid_sources[0x15]	11204	1			T3	7		T10	1		T11	3
valid_sources[0x16]	10975	1			T3	4		T10	7		T11	4
valid_sources[0x17]	11376	1			T3	7		T10	2		T11	6
valid_sources[0x18]	11444	1			T10	11		T11	9		T6	5
valid_sources[0x19]	27948	1			T3	7		T10	3		T11	6
valid_sources[0x1a]	11056	1			T3	1		T10	1		T11	8
valid_sources[0x1b]	11121	1			T3	4		T10	2		T11	10
valid_sources[0x1c]	11590	1			T3	7		T10	12		T11	6
valid_sources[0x1d]	11079	1			T3	8		T10	1		T11	17
valid_sources[0x1e]	10460	1			T3	12		T10	11		T11	5
valid_sources[0x1f]	13564	1			T2	2766		T3	10		T10	5
valid_sources[0x20]	71070	1			T3	5		T10	8		T11	3
valid_sources[0x21]	12035	1			T3	3		T10	9		T11	7
valid_sources[0x22]	13692	1			T3	7		T10	7		T11	9
valid_sources[0x23]	11589	1			T3	1		T11	8		T6	3
valid_sources[0x24]	11114	1			T3	6		T10	1		T11	8
valid_sources[0x25]	11364	1			T3	6		T10	5		T11	9
valid_sources[0x26]	55232	1			T2	42		T3	4		T10	5
valid_sources[0x27]	16873	1			T3	7		T10	3		T11	9
valid_sources[0x28]	16568	1			T3	8		T10	3		T11	11
valid_sources[0x29]	12407	1			T3	6		T10	12		T11	10
valid_sources[0x2a]	12840	1			T3	3		T10	6		T11	3
valid_sources[0x2b]	13836	1			T3	4		T10	5		T11	9
valid_sources[0x2c]	11943	1			T3	3		T10	2		T6	7
valid_sources[0x2d]	13595	1			T3	9		T10	2		T11	10
valid_sources[0x2e]	11849	1			T3	1		T10	4		T11	5
valid_sources[0x2f]	79482	1			T3	3		T10	2		T11	6
valid_sources[0x30]	11945	1			T3	6		T10	5		T11	8
valid_sources[0x31]	11172	1			T3	7		T10	2		T11	12
valid_sources[0x32]	11108	1			T3	6		T10	9		T11	4
valid_sources[0x33]	10625	1			T3	4		T10	5		T11	5
valid_sources[0x34]	10825	1			T3	6		T10	1		T11	7
valid_sources[0x35]	11053	1			T3	3		T10	3		T11	5
valid_sources[0x36]	10923	1			T3	4		T10	3		T11	1
valid_sources[0x37]	10902	1			T3	4		T10	9		T61	1
valid_sources[0x38]	10866	1			T3	14		T10	6		T11	9
valid_sources[0x39]	11226	1			T3	6		T10	1		T7	1
valid_sources[0x3a]	11107	1			T3	11		T10	4		T11	2
valid_sources[0x3b]	12456	1			T3	14		T10	1		T11	4
valid_sources[0x3c]	11226	1			T3	1		T10	3		T11	21
valid_sources[0x3d]	10741	1			T3	4		T10	1		T6	1
valid_sources[0x3e]	11108	1			T3	7		T10	10		T11	3
valid_sources[0x3f]	10773	1			T3	9		T10	3		T11	8
valid_sources[0x40]	13513	1			T3	4		T10	5		T11	6
valid_sources[0x41]	11212	1			T3	6		T10	11		T61	3
valid_sources[0x42]	11941	1			T2	6		T3	6		T10	5
valid_sources[0x43]	11217	1			T3	16		T10	6		T11	1
valid_sources[0x44]	11640	1			T3	2		T10	3		T11	4
valid_sources[0x45]	11776	1			T3	6		T10	6		T11	21
valid_sources[0x46]	10877	1			T3	3		T10	5		T11	9
valid_sources[0x47]	13432	1			T3	1		T10	8		T11	9
valid_sources[0x48]	10750	1			T3	1		T10	6		T11	6
valid_sources[0x49]	19435	1			T3	2		T10	8		T11	3
valid_sources[0x4a]	13758	1			T3	4		T10	16		T6	1
valid_sources[0x4b]	11584	1			T10	1		T11	10		T6	1
valid_sources[0x4c]	11231	1			T3	8		T10	4		T11	18
valid_sources[0x4d]	10411	1			T3	7		T10	11		T11	4
valid_sources[0x4e]	11321	1			T3	5		T10	7		T11	10
valid_sources[0x4f]	11200	1			T3	3		T10	10		T11	23
valid_sources[0x50]	10937	1			T3	15		T10	5		T11	5
valid_sources[0x51]	76721	1			T3	12		T10	6		T11	9
valid_sources[0x52]	10826	1			T3	13		T10	5		T11	6
valid_sources[0x53]	11151	1			T3	12		T10	3		T11	1
valid_sources[0x54]	11161	1			T3	6		T10	5		T11	1
valid_sources[0x55]	16429	1			T3	5		T10	5		T11	14
valid_sources[0x56]	12152	1			T3	6		T10	9		T11	4
valid_sources[0x57]	10762	1			T3	7		T10	5		T11	1
valid_sources[0x58]	10838	1			T3	8		T10	3		T11	1
valid_sources[0x59]	13893	1			T1	6		T3	4		T10	4
valid_sources[0x5a]	12649	1			T3	4		T10	6		T11	4
valid_sources[0x5b]	11422	1			T3	10		T10	4		T11	9
valid_sources[0x5c]	10913	1			T3	2		T10	7		T11	11
valid_sources[0x5d]	11074	1			T3	9		T10	10		T11	11
valid_sources[0x5e]	10913	1			T3	8		T11	6		T6	2
valid_sources[0x5f]	10882	1			T3	3		T10	5		T11	24
valid_sources[0x60]	11016	1			T3	3		T10	6		T11	10
valid_sources[0x61]	13707	1			T3	1		T10	3		T11	2
valid_sources[0x62]	11046	1			T3	2		T10	6		T11	2
valid_sources[0x63]	11138	1			T3	6		T10	6		T11	7
valid_sources[0x64]	11139	1			T3	11		T10	4		T11	1
valid_sources[0x65]	12539	1			T3	4		T10	4		T11	3
valid_sources[0x66]	12020	1			T3	22		T10	6		T11	4
valid_sources[0x67]	10921	1			T3	10		T10	2		T11	5
valid_sources[0x68]	10892	1			T3	12		T10	5		T6	2
valid_sources[0x69]	12276	1			T3	13		T10	9		T11	5
valid_sources[0x6a]	10627	1			T3	21		T10	6		T11	1
valid_sources[0x6b]	11039	1			T3	10		T10	5		T6	3
valid_sources[0x6c]	12021	1			T3	8		T10	3		T6	5
valid_sources[0x6d]	10685	1			T3	16		T10	7		T11	3
valid_sources[0x6e]	10933	1			T10	3		T11	8		T6	5
valid_sources[0x6f]	11759	1			T3	7		T10	11		T11	11
valid_sources[0x70]	11465	1			T2	38		T3	5		T10	5
valid_sources[0x71]	13279	1			T3	5		T10	14		T11	1
valid_sources[0x72]	12689	1			T3	7		T10	1		T11	13
valid_sources[0x73]	11153	1			T3	10		T10	6		T11	2
valid_sources[0x74]	10832	1			T1	4		T3	17		T10	2
valid_sources[0x75]	11388	1			T3	8		T10	12		T11	6
valid_sources[0x76]	10877	1			T3	11		T10	5		T11	12
valid_sources[0x77]	11154	1			T3	9		T10	8		T11	6
valid_sources[0x78]	16782	1			T3	13		T10	3		T11	3
valid_sources[0x79]	12287	1			T3	11		T10	2		T11	8
valid_sources[0x7a]	10883	1			T3	11		T10	3		T11	12
valid_sources[0x7b]	10910	1			T3	4		T10	4		T11	6
valid_sources[0x7c]	10676	1			T2	1		T3	9		T10	6
valid_sources[0x7d]	11374	1			T3	6		T10	7		T11	7
valid_sources[0x7e]	11065	1			T3	7		T10	9		T11	2
valid_sources[0x7f]	12027	1			T3	7		T10	5		T11	11
valid_sources[0x80]	11490	1			T3	3		T10	8		T11	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1636782

1

T1

10

T2

1600

T3

520

values[0x0]

all_enables

biggest_size

152913

1

T1

2

T2

287

T3

273

values[0x1]

all_enables

biggest_size

152676

1

T1

5

T2

272

T3

263