Module Definition
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Module : lc_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.lc_ctrl_csr_assert 100.00 100.00



Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.32 100.00 82.35 99.89 100.00 84.38 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : lc_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 111251503 13798 0 0
claim_transition_if_regwen_rd_A 111251503 1164 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 111251503 13798 0 0
T2 417266 1 0 0
T3 41888 0 0 0
T4 34159 0 0 0
T5 124738 0 0 0
T6 57999 0 0 0
T10 35657 0 0 0
T11 23747 0 0 0
T12 1399 0 0 0
T13 7774 0 0 0
T19 34349 0 0 0
T38 0 1 0 0
T87 0 9 0 0
T98 0 4 0 0
T100 0 3 0 0
T101 0 9 0 0
T108 0 16 0 0
T143 0 2 0 0
T144 0 8 0 0
T145 0 11 0 0

claim_transition_if_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 111251503 1164 0 0
T2 417266 9 0 0
T3 41888 0 0 0
T4 34159 0 0 0
T5 124738 0 0 0
T6 57999 0 0 0
T10 35657 0 0 0
T11 23747 0 0 0
T12 1399 0 0 0
T13 7774 0 0 0
T19 34349 0 0 0
T114 0 35 0 0
T115 0 52 0 0
T119 0 105 0 0
T121 0 15 0 0
T146 0 5 0 0
T147 0 8 0 0
T148 0 20 0 0
T149 0 7 0 0
T150 0 64 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%