Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1464928	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1673659

1

T1

179

T2

1000

T3

111

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2810538	1			T1	166		T2	921		T3	117
values[0x0]	163485	1			T1	58		T2	330		T3	36
values[0x1]	164564	1			T1	46		T2	334		T3	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1162662	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1975925

1

T1

207

T2

1150

T3

126

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9045	1			T2	24		T12	5		T15	13
valid_sources[0x01]	10044	1			T15	4		T18	3		T6	57
valid_sources[0x02]	9588	1			T2	6		T12	1		T19	3
valid_sources[0x03]	9526	1			T2	12		T12	4		T15	4
valid_sources[0x04]	10494	1			T2	27		T12	3		T19	26
valid_sources[0x05]	9493	1			T2	5		T15	33		T6	71
valid_sources[0x06]	10406	1			T2	3		T12	3		T15	4
valid_sources[0x07]	9834	1			T2	4		T12	3		T14	22
valid_sources[0x08]	11122	1			T2	1		T12	3		T6	90
valid_sources[0x09]	10412	1			T2	15		T3	2		T12	9
valid_sources[0x0a]	16034	1			T1	1		T2	2		T12	5
valid_sources[0x0b]	10013	1			T1	1		T3	2		T12	3
valid_sources[0x0c]	9310	1			T2	4		T12	6		T15	20
valid_sources[0x0d]	15042	1			T12	7		T15	30		T18	8
valid_sources[0x0e]	9787	1			T2	1		T12	4		T15	36
valid_sources[0x0f]	9864	1			T3	4		T12	3		T18	1
valid_sources[0x10]	10296	1			T2	4		T3	1		T12	3
valid_sources[0x11]	11718	1			T2	10		T12	4		T15	9
valid_sources[0x12]	9872	1			T1	6		T2	15		T12	4
valid_sources[0x13]	9374	1			T18	1		T6	71		T68	1
valid_sources[0x14]	9715	1			T2	17		T12	4		T15	13
valid_sources[0x15]	11523	1			T2	3		T12	6		T19	31
valid_sources[0x16]	9877	1			T1	7		T2	2		T12	4
valid_sources[0x17]	11822	1			T2	9		T12	5		T13	6
valid_sources[0x18]	11122	1			T12	3		T15	32		T19	6
valid_sources[0x19]	10103	1			T2	8		T12	4		T15	6
valid_sources[0x1a]	10155	1			T2	37		T3	1		T12	3
valid_sources[0x1b]	9421	1			T2	1		T3	1		T12	7
valid_sources[0x1c]	9123	1			T12	4		T15	5		T18	5
valid_sources[0x1d]	9923	1			T2	1		T12	1		T15	9
valid_sources[0x1e]	10166	1			T12	2		T15	26		T19	22
valid_sources[0x1f]	9685	1			T2	8		T12	3		T15	25
valid_sources[0x20]	9572	1			T2	1		T3	7		T12	1
valid_sources[0x21]	10947	1			T2	1		T12	1		T15	16
valid_sources[0x22]	9672	1			T2	10		T12	5		T15	30
valid_sources[0x23]	9657	1			T2	18		T12	4		T15	9
valid_sources[0x24]	9432	1			T2	1		T12	2		T15	35
valid_sources[0x25]	11272	1			T2	1		T12	1		T15	16
valid_sources[0x26]	10167	1			T2	17		T12	3		T13	5
valid_sources[0x27]	71881	1			T2	1		T12	4		T15	4
valid_sources[0x28]	10505	1			T2	11		T12	4		T15	21
valid_sources[0x29]	9439	1			T2	3		T3	4		T12	5
valid_sources[0x2a]	10087	1			T1	35		T2	9		T3	2
valid_sources[0x2b]	31898	1			T2	10		T3	2		T12	3
valid_sources[0x2c]	9969	1			T2	1		T12	8		T15	5
valid_sources[0x2d]	11051	1			T1	5		T12	1		T15	23
valid_sources[0x2e]	11467	1			T12	7		T15	3		T18	23
valid_sources[0x2f]	10038	1			T12	2		T15	2		T18	19
valid_sources[0x30]	9739	1			T1	4		T2	13		T12	5
valid_sources[0x31]	10077	1			T3	5		T12	10		T15	13
valid_sources[0x32]	9561	1			T1	3		T12	4		T15	3
valid_sources[0x33]	9730	1			T2	14		T12	1		T15	7
valid_sources[0x34]	15570	1			T1	23		T12	5		T15	1
valid_sources[0x35]	9817	1			T12	8		T15	1		T18	3
valid_sources[0x36]	10002	1			T2	11		T3	1		T12	4
valid_sources[0x37]	11336	1			T1	1		T2	14		T11	1802
valid_sources[0x38]	9857	1			T2	9		T12	2		T15	15
valid_sources[0x39]	15661	1			T2	7		T15	26		T6	56
valid_sources[0x3a]	11390	1			T2	9		T12	4		T15	15
valid_sources[0x3b]	9800	1			T2	13		T3	3		T12	7
valid_sources[0x3c]	10628	1			T12	3		T15	19		T18	6
valid_sources[0x3d]	9423	1			T2	13		T12	1		T15	5
valid_sources[0x3e]	11239	1			T2	18		T3	1		T12	6
valid_sources[0x3f]	9179	1			T12	1		T15	3		T19	20
valid_sources[0x40]	9394	1			T12	2		T6	52		T28	7
valid_sources[0x41]	11242	1			T12	3		T15	9		T19	2
valid_sources[0x42]	10279	1			T2	1		T12	2		T15	7
valid_sources[0x43]	9436	1			T2	11		T12	4		T15	1
valid_sources[0x44]	13544	1			T1	1		T2	12		T12	4
valid_sources[0x45]	10042	1			T2	2		T12	2		T15	18
valid_sources[0x46]	10100	1			T2	1		T12	5		T15	8
valid_sources[0x47]	10042	1			T2	2		T12	6		T15	31
valid_sources[0x48]	9434	1			T3	1		T12	2		T15	20
valid_sources[0x49]	9766	1			T2	1		T12	3		T15	9
valid_sources[0x4a]	14193	1			T2	10		T12	8		T6	77
valid_sources[0x4b]	9450	1			T2	5		T12	3		T15	13
valid_sources[0x4c]	10098	1			T2	20		T3	1		T12	3
valid_sources[0x4d]	9480	1			T3	1		T12	6		T15	11
valid_sources[0x4e]	10585	1			T2	9		T3	3		T12	7
valid_sources[0x4f]	10035	1			T2	15		T12	6		T15	35
valid_sources[0x50]	14313	1			T2	7		T12	4		T13	4
valid_sources[0x51]	11596	1			T2	4		T12	6		T15	21
valid_sources[0x52]	9999	1			T2	53		T3	10		T12	1
valid_sources[0x53]	9772	1			T2	5		T12	1		T15	32
valid_sources[0x54]	10587	1			T3	3		T12	1		T15	25
valid_sources[0x55]	9628	1			T2	9		T12	3		T15	2
valid_sources[0x56]	9906	1			T2	10		T12	5		T15	43
valid_sources[0x57]	11739	1			T12	3		T15	7		T18	5
valid_sources[0x58]	9543	1			T12	2		T15	8		T6	45
valid_sources[0x59]	10468	1			T1	1		T2	11		T12	3
valid_sources[0x5a]	10834	1			T1	4		T3	2		T12	6
valid_sources[0x5b]	10021	1			T2	1		T3	2		T12	2
valid_sources[0x5c]	19998	1			T2	2		T12	4		T6	47
valid_sources[0x5d]	9802	1			T2	14		T12	1		T15	13
valid_sources[0x5e]	10077	1			T2	20		T12	5		T15	30
valid_sources[0x5f]	9699	1			T2	3		T12	4		T15	19
valid_sources[0x60]	9428	1			T12	7		T15	12		T6	53
valid_sources[0x61]	9686	1			T2	8		T12	2		T15	51
valid_sources[0x62]	10147	1			T2	4		T3	1		T12	4
valid_sources[0x63]	12053	1			T12	3		T15	34		T19	3
valid_sources[0x64]	10033	1			T2	13		T12	4		T15	18
valid_sources[0x65]	8999	1			T12	5		T14	27		T15	10
valid_sources[0x66]	11000	1			T2	3		T12	4		T15	6
valid_sources[0x67]	15246	1			T2	8		T3	3		T15	18
valid_sources[0x68]	11461	1			T2	2		T12	2		T15	16
valid_sources[0x69]	9566	1			T3	1		T12	3		T15	10
valid_sources[0x6a]	11074	1			T2	5		T12	2		T15	22
valid_sources[0x6b]	9741	1			T2	4		T12	7		T15	1
valid_sources[0x6c]	10364	1			T12	4		T13	1		T15	16
valid_sources[0x6d]	9891	1			T2	3		T3	11		T12	3
valid_sources[0x6e]	10015	1			T12	4		T13	1		T15	34
valid_sources[0x6f]	9797	1			T3	8		T12	1		T15	15
valid_sources[0x70]	14196	1			T3	1		T12	3		T15	13
valid_sources[0x71]	10045	1			T2	2		T12	3		T15	1
valid_sources[0x72]	11189	1			T2	14		T12	3		T15	32
valid_sources[0x73]	9524	1			T2	3		T12	6		T15	2
valid_sources[0x74]	9477	1			T12	5		T15	24		T19	3
valid_sources[0x75]	11613	1			T12	3		T14	87		T15	13
valid_sources[0x76]	10408	1			T2	21		T3	2		T18	4
valid_sources[0x77]	9382	1			T2	14		T12	4		T15	22
valid_sources[0x78]	10505	1			T12	1		T15	29		T6	61
valid_sources[0x79]	9785	1			T2	9		T12	5		T15	3
valid_sources[0x7a]	9861	1			T1	1		T12	1		T14	154
valid_sources[0x7b]	9793	1			T2	51		T3	1		T12	4
valid_sources[0x7c]	9609	1			T2	1		T3	2		T12	4
valid_sources[0x7d]	10464	1			T2	2		T3	1		T12	8
valid_sources[0x7e]	9807	1			T12	6		T15	26		T18	2
valid_sources[0x7f]	9336	1			T3	1		T12	3		T15	20
valid_sources[0x80]	90503	1			T2	1		T12	5		T15	35

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1391279

1

T1

87

T2

421

T3

47

values[0x0]

all_enables

biggest_size

141569

1

T1

52

T2

291

T3

32

values[0x1]

all_enables

biggest_size

140811

1

T1

40

T2

288

T3

32