Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	98059193	11951	0	0
claim_transition_if_regwen_rd_A	98059193	1591	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98059193	11951	0	0
T49	747954	4	0	0
T50	38080	0	0	0
T67	0	3	0	0
T92	0	2	0	0
T93	0	1	0	0
T97	0	6	0	0
T111	0	17	0	0
T147	0	2	0	0
T148	0	2	0	0
T149	0	9	0	0
T150	0	8	0	0
T151	8664	0	0	0
T152	18649	0	0	0
T153	43399	0	0	0
T154	26525	0	0	0
T155	24519	0	0	0
T156	39485	0	0	0
T157	74187	0	0	0
T158	28752	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98059193	1591	0	0
T51	0	11	0	0
T93	274822	4	0	0
T108	0	3	0	0
T110	0	6	0	0
T121	0	40	0	0
T139	0	51	0	0
T147	159210	0	0	0
T159	0	19	0	0
T160	0	4	0	0
T161	0	5	0	0
T162	0	6	0	0
T163	4136	0	0	0
T164	1403	0	0	0
T165	27453	0	0	0
T166	39460	0	0	0
T167	18350	0	0	0
T168	1887	0	0	0
T169	78845	0	0	0
T170	1915	0	0	0