Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1416381	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1629935

1

T2

1065

T3

35

T9

1053

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2706684	1			T2	1115		T3	47		T9	1055
values[0x0]	168946	1			T2	281		T3	21		T9	312
values[0x1]	170686	1			T2	303		T3	24		T9	288

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1124232	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1922084

1

T2

1187

T3

42

T9

1199

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8136	1			T2	9		T3	7		T9	9
valid_sources[0x01]	10628	1			T2	6		T9	11		T10	12
valid_sources[0x02]	8008	1			T2	5		T9	7		T11	9
valid_sources[0x03]	8910	1			T2	4		T9	6		T10	8
valid_sources[0x04]	7900	1			T2	5		T9	8		T10	17
valid_sources[0x05]	8394	1			T2	10		T9	9		T10	50
valid_sources[0x06]	8534	1			T3	3		T9	7		T11	21
valid_sources[0x07]	31564	1			T2	4		T9	3		T11	14
valid_sources[0x08]	8283	1			T2	6		T9	9		T10	12
valid_sources[0x09]	9464	1			T2	8		T9	8		T11	16
valid_sources[0x0a]	8011	1			T2	5		T3	8		T9	9
valid_sources[0x0b]	8196	1			T2	5		T9	4		T11	15
valid_sources[0x0c]	8463	1			T2	7		T9	7		T10	30
valid_sources[0x0d]	8170	1			T2	5		T9	8		T11	20
valid_sources[0x0e]	8342	1			T2	14		T9	6		T11	16
valid_sources[0x0f]	8407	1			T2	7		T9	3		T11	13
valid_sources[0x10]	8193	1			T2	6		T9	13		T11	8
valid_sources[0x11]	30965	1			T2	6		T9	4		T10	12
valid_sources[0x12]	9146	1			T2	2		T9	6		T11	12
valid_sources[0x13]	8183	1			T2	10		T9	6		T11	15
valid_sources[0x14]	8331	1			T2	5		T9	10		T11	9
valid_sources[0x15]	8147	1			T2	5		T9	4		T11	7
valid_sources[0x16]	7921	1			T2	5		T9	6		T10	28
valid_sources[0x17]	8038	1			T2	6		T9	9		T11	12
valid_sources[0x18]	12898	1			T2	5		T9	6		T11	15
valid_sources[0x19]	9165	1			T2	12		T9	4		T11	14
valid_sources[0x1a]	13341	1			T2	4		T9	5		T10	10
valid_sources[0x1b]	9727	1			T2	12		T3	7		T9	9
valid_sources[0x1c]	9575	1			T2	9		T9	8		T11	13
valid_sources[0x1d]	9344	1			T2	9		T9	1		T11	16
valid_sources[0x1e]	25951	1			T2	4		T9	5		T11	6
valid_sources[0x1f]	8009	1			T2	8		T9	8		T10	16
valid_sources[0x20]	31551	1			T2	5		T9	4		T11	14
valid_sources[0x21]	8613	1			T2	2		T9	4		T10	42
valid_sources[0x22]	9401	1			T2	9		T9	4		T11	16
valid_sources[0x23]	8678	1			T2	7		T3	3		T9	8
valid_sources[0x24]	8376	1			T2	7		T9	11		T11	8
valid_sources[0x25]	10037	1			T2	5		T9	12		T11	9
valid_sources[0x26]	8509	1			T2	3		T9	3		T11	10
valid_sources[0x27]	26858	1			T2	7		T9	6		T11	21
valid_sources[0x28]	8155	1			T2	6		T9	8		T11	16
valid_sources[0x29]	12602	1			T2	3		T9	2		T11	9
valid_sources[0x2a]	8071	1			T2	3		T9	3		T10	3
valid_sources[0x2b]	21330	1			T9	9		T10	12		T11	15
valid_sources[0x2c]	17377	1			T2	8		T9	9		T11	11
valid_sources[0x2d]	8109	1			T2	5		T9	8		T11	7
valid_sources[0x2e]	8299	1			T2	3		T9	3		T11	14
valid_sources[0x2f]	8039	1			T2	5		T9	8		T10	2
valid_sources[0x30]	8172	1			T2	11		T9	4		T10	1
valid_sources[0x31]	10314	1			T2	6		T9	7		T11	12
valid_sources[0x32]	8453	1			T2	5		T9	4		T11	15
valid_sources[0x33]	8898	1			T2	11		T9	2		T11	14
valid_sources[0x34]	7834	1			T2	2		T9	6		T11	3
valid_sources[0x35]	8401	1			T2	8		T9	2		T11	10
valid_sources[0x36]	8538	1			T2	8		T9	6		T10	19
valid_sources[0x37]	8011	1			T2	5		T9	11		T10	8
valid_sources[0x38]	47280	1			T2	13		T9	5		T10	11
valid_sources[0x39]	8375	1			T2	9		T9	13		T10	2
valid_sources[0x3a]	9399	1			T2	1		T9	3		T11	9
valid_sources[0x3b]	8810	1			T2	6		T9	2		T11	7
valid_sources[0x3c]	8245	1			T2	6		T9	7		T11	8
valid_sources[0x3d]	9717	1			T2	11		T9	6		T11	13
valid_sources[0x3e]	8548	1			T2	9		T9	5		T11	11
valid_sources[0x3f]	8213	1			T2	3		T9	6		T11	16
valid_sources[0x40]	7890	1			T2	9		T3	3		T9	4
valid_sources[0x41]	8528	1			T2	4		T9	6		T11	10
valid_sources[0x42]	8658	1			T2	8		T9	3		T10	26
valid_sources[0x43]	37694	1			T2	8		T9	8		T10	19
valid_sources[0x44]	10014	1			T2	5		T9	10		T11	9
valid_sources[0x45]	8652	1			T2	12		T9	7		T10	3
valid_sources[0x46]	10265	1			T2	1		T9	4		T11	5
valid_sources[0x47]	8060	1			T2	10		T9	4		T11	24
valid_sources[0x48]	8898	1			T2	8		T3	7		T9	9
valid_sources[0x49]	8013	1			T2	8		T9	2		T11	23
valid_sources[0x4a]	11786	1			T2	5		T9	7		T10	7
valid_sources[0x4b]	8384	1			T2	12		T9	4		T11	7
valid_sources[0x4c]	49596	1			T2	10		T9	8		T10	8
valid_sources[0x4d]	10414	1			T2	8		T9	12		T11	7
valid_sources[0x4e]	8062	1			T2	9		T9	4		T10	12
valid_sources[0x4f]	8714	1			T2	7		T9	8		T11	12
valid_sources[0x50]	8301	1			T2	5		T9	3		T11	16
valid_sources[0x51]	16325	1			T2	10		T9	4		T10	14
valid_sources[0x52]	8065	1			T2	7		T9	9		T11	9
valid_sources[0x53]	8251	1			T2	8		T9	11		T11	9
valid_sources[0x54]	8100	1			T2	9		T9	9		T10	14
valid_sources[0x55]	13282	1			T2	5		T9	6		T11	6
valid_sources[0x56]	40420	1			T2	3		T9	8		T11	7
valid_sources[0x57]	8398	1			T2	5		T9	4		T11	17
valid_sources[0x58]	10707	1			T2	8		T9	3		T10	25
valid_sources[0x59]	12117	1			T2	5		T9	10		T11	7
valid_sources[0x5a]	7929	1			T2	10		T9	3		T10	2
valid_sources[0x5b]	25068	1			T2	8		T9	6		T11	5
valid_sources[0x5c]	61525	1			T2	9		T9	17		T11	15
valid_sources[0x5d]	8130	1			T2	4		T9	10		T11	20
valid_sources[0x5e]	8253	1			T2	8		T9	7		T11	14
valid_sources[0x5f]	62992	1			T2	6		T9	8		T10	18
valid_sources[0x60]	8419	1			T2	4		T9	8		T10	14
valid_sources[0x61]	8499	1			T2	6		T9	11		T11	21
valid_sources[0x62]	8323	1			T2	3		T9	6		T10	27
valid_sources[0x63]	9443	1			T2	4		T9	8		T11	18
valid_sources[0x64]	8390	1			T2	12		T9	6		T11	13
valid_sources[0x65]	9450	1			T2	7		T9	10		T11	7
valid_sources[0x66]	8342	1			T2	8		T9	5		T10	7
valid_sources[0x67]	9599	1			T2	7		T9	4		T10	21
valid_sources[0x68]	8325	1			T2	3		T9	5		T10	33
valid_sources[0x69]	8450	1			T2	9		T9	9		T10	63
valid_sources[0x6a]	15012	1			T2	11		T9	13		T11	6
valid_sources[0x6b]	8195	1			T2	8		T9	7		T10	8
valid_sources[0x6c]	8716	1			T2	9		T3	2		T9	6
valid_sources[0x6d]	21700	1			T2	5		T9	4		T11	13
valid_sources[0x6e]	8180	1			T2	7		T9	9		T11	14
valid_sources[0x6f]	10054	1			T2	10		T9	2		T11	10
valid_sources[0x70]	25001	1			T2	10		T9	8		T11	25
valid_sources[0x71]	8501	1			T2	5		T10	76		T11	12
valid_sources[0x72]	8456	1			T2	11		T9	7		T11	9
valid_sources[0x73]	8377	1			T2	5		T9	9		T10	18
valid_sources[0x74]	7883	1			T2	10		T9	6		T11	11
valid_sources[0x75]	12033	1			T2	4		T3	18		T9	13
valid_sources[0x76]	8332	1			T2	5		T9	7		T10	22
valid_sources[0x77]	9697	1			T2	4		T9	7		T11	14
valid_sources[0x78]	8283	1			T2	4		T9	6		T10	37
valid_sources[0x79]	8219	1			T2	10		T3	2		T9	8
valid_sources[0x7a]	7898	1			T2	5		T9	6		T11	7
valid_sources[0x7b]	9664	1			T2	6		T9	8		T11	15
valid_sources[0x7c]	9633	1			T2	7		T9	8		T11	11
valid_sources[0x7d]	8231	1			T2	11		T9	7		T10	6
valid_sources[0x7e]	8879	1			T2	10		T9	5		T11	16
valid_sources[0x7f]	21991	1			T2	2		T9	4		T10	1
valid_sources[0x80]	7863	1			T2	7		T9	5		T11	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1336980

1

T2

556

T3

23

T9

529

values[0x0]

all_enables

biggest_size

146555

1

T2

245

T3

8

T9

271

values[0x1]

all_enables

biggest_size

146400

1

T2

264

T3

4

T9

253