Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	108750981	14234	0	0
claim_transition_if_regwen_rd_A	108750981	1532	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108750981	14234	0	0
T6	7650	0	0	0
T16	392840	3	0	0
T17	185962	7	0	0
T18	50952	0	0	0
T25	80614	0	0	0
T35	0	9	0	0
T37	0	19	0	0
T51	4042	0	0	0
T52	76877	0	0	0
T53	465163	0	0	0
T54	0	3	0	0
T78	30568	0	0	0
T85	0	6	0	0
T100	0	14	0	0
T136	0	4	0	0
T137	0	4	0	0
T138	0	1	0	0
T139	88271	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108750981	1532	0	0
T6	7650	0	0	0
T16	392840	17	0	0
T17	185962	0	0	0
T18	50952	0	0	0
T25	80614	0	0	0
T51	4042	0	0	0
T52	76877	0	0	0
T53	465163	0	0	0
T78	30568	0	0	0
T112	0	17	0	0
T114	0	13	0	0
T121	0	5	0	0
T139	88271	0	0	0
T140	0	15	0	0
T141	0	15	0	0
T142	0	3	0	0
T143	0	17	0	0
T144	0	6	0	0
T145	0	10	0	0