Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1608363	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1826676

1

T1

24265

T2

172

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3096724	1			T1	46938		T2	155		T4	460
values[0x0]	169093	1			T1	554		T2	67		T3	18
values[0x1]	169222	1			T1	586		T2	66		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1276560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2158479

1

T1

29130

T2

196

T3

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9945	1			T1	188		T5	3		T10	1
valid_sources[0x01]	9662	1			T1	198		T5	13		T11	2
valid_sources[0x02]	10105	1			T1	172		T5	3		T10	2
valid_sources[0x03]	9961	1			T1	198		T5	9		T10	3
valid_sources[0x04]	14149	1			T1	163		T5	4		T10	1
valid_sources[0x05]	18526	1			T1	199		T5	4		T20	3
valid_sources[0x06]	10431	1			T1	186		T5	5		T10	1
valid_sources[0x07]	11854	1			T1	195		T5	1		T10	6
valid_sources[0x08]	12508	1			T1	208		T5	11		T10	2
valid_sources[0x09]	10009	1			T1	197		T10	1		T11	1
valid_sources[0x0a]	12633	1			T1	196		T5	3		T10	2
valid_sources[0x0b]	9537	1			T1	165		T5	7		T10	2
valid_sources[0x0c]	10063	1			T1	151		T5	6		T10	1
valid_sources[0x0d]	9664	1			T1	214		T5	20		T10	2
valid_sources[0x0e]	9545	1			T1	180		T5	16		T20	8
valid_sources[0x0f]	9817	1			T1	179		T10	1		T11	1
valid_sources[0x10]	11021	1			T1	210		T5	3		T10	1
valid_sources[0x11]	9809	1			T1	177		T2	19		T5	7
valid_sources[0x12]	10602	1			T1	162		T5	13		T10	3
valid_sources[0x13]	89652	1			T1	162		T11	3		T20	5
valid_sources[0x14]	10422	1			T1	210		T10	4		T11	3
valid_sources[0x15]	14612	1			T1	194		T5	8		T11	1
valid_sources[0x16]	10932	1			T1	168		T5	3		T10	2
valid_sources[0x17]	9872	1			T1	201		T5	3		T10	2
valid_sources[0x18]	9492	1			T1	191		T5	4		T10	1
valid_sources[0x19]	9950	1			T1	216		T10	1		T11	1
valid_sources[0x1a]	11398	1			T1	193		T5	6		T10	4
valid_sources[0x1b]	11494	1			T1	206		T5	2		T11	1
valid_sources[0x1c]	9870	1			T1	181		T5	14		T20	7
valid_sources[0x1d]	9429	1			T1	195		T5	2		T10	1
valid_sources[0x1e]	10166	1			T1	178		T5	1		T10	3
valid_sources[0x1f]	10235	1			T1	190		T10	3		T11	1
valid_sources[0x20]	10828	1			T1	188		T5	23		T10	2
valid_sources[0x21]	10040	1			T1	169		T2	1		T5	26
valid_sources[0x22]	10325	1			T1	176		T5	6		T9	1
valid_sources[0x23]	11746	1			T1	198		T5	8		T10	2
valid_sources[0x24]	10636	1			T1	212		T5	2		T10	1
valid_sources[0x25]	10104	1			T1	213		T5	15		T20	8
valid_sources[0x26]	9916	1			T1	214		T10	2		T11	2
valid_sources[0x27]	9983	1			T1	197		T5	13		T10	6
valid_sources[0x28]	9994	1			T1	185		T5	12		T10	4
valid_sources[0x29]	11288	1			T1	209		T5	2		T10	1
valid_sources[0x2a]	28762	1			T1	174		T5	16		T10	1
valid_sources[0x2b]	10278	1			T1	197		T5	9		T10	2
valid_sources[0x2c]	9832	1			T1	175		T20	6		T16	3
valid_sources[0x2d]	9878	1			T1	179		T5	2		T10	5
valid_sources[0x2e]	17806	1			T1	196		T5	2		T10	2
valid_sources[0x2f]	21262	1			T1	197		T5	1		T11	3
valid_sources[0x30]	9566	1			T1	177		T5	3		T10	3
valid_sources[0x31]	10105	1			T1	190		T5	4		T10	1
valid_sources[0x32]	9772	1			T1	189		T5	1		T11	1
valid_sources[0x33]	10084	1			T1	187		T5	1		T11	1
valid_sources[0x34]	9806	1			T1	169		T2	2		T10	2
valid_sources[0x35]	9932	1			T1	199		T5	1		T10	1
valid_sources[0x36]	19235	1			T1	173		T5	2		T10	1
valid_sources[0x37]	9521	1			T1	191		T2	10		T5	3
valid_sources[0x38]	45068	1			T1	180		T5	9		T10	2
valid_sources[0x39]	11810	1			T1	198		T10	2		T9	1
valid_sources[0x3a]	10123	1			T1	206		T2	1		T10	1
valid_sources[0x3b]	13369	1			T1	157		T2	3		T5	5
valid_sources[0x3c]	11785	1			T1	180		T5	10		T20	6
valid_sources[0x3d]	10028	1			T1	210		T5	6		T11	1
valid_sources[0x3e]	9789	1			T1	195		T5	17		T10	4
valid_sources[0x3f]	10050	1			T1	174		T5	6		T10	2
valid_sources[0x40]	9737	1			T1	180		T5	12		T10	1
valid_sources[0x41]	9832	1			T1	221		T5	4		T10	3
valid_sources[0x42]	11364	1			T1	215		T5	1		T10	1
valid_sources[0x43]	9621	1			T1	189		T5	9		T10	1
valid_sources[0x44]	14177	1			T1	183		T5	5		T10	4
valid_sources[0x45]	9691	1			T1	167		T5	1		T10	1
valid_sources[0x46]	11537	1			T1	203		T2	20		T10	3
valid_sources[0x47]	10772	1			T1	189		T5	6		T10	1
valid_sources[0x48]	9871	1			T1	182		T5	2		T10	3
valid_sources[0x49]	10243	1			T1	197		T5	1		T10	2
valid_sources[0x4a]	10099	1			T1	185		T5	16		T10	1
valid_sources[0x4b]	9863	1			T1	189		T5	1		T10	5
valid_sources[0x4c]	9875	1			T1	186		T10	1		T9	1
valid_sources[0x4d]	9812	1			T1	182		T2	3		T10	3
valid_sources[0x4e]	10632	1			T1	190		T5	6		T10	1
valid_sources[0x4f]	9850	1			T1	186		T5	3		T11	1
valid_sources[0x50]	12146	1			T1	186		T5	6		T19	10
valid_sources[0x51]	9870	1			T1	167		T5	1		T10	1
valid_sources[0x52]	112736	1			T1	199		T5	1		T10	4
valid_sources[0x53]	10625	1			T1	185		T5	11		T10	2
valid_sources[0x54]	10091	1			T1	196		T5	7		T9	2
valid_sources[0x55]	10044	1			T1	198		T2	5		T5	3
valid_sources[0x56]	27781	1			T1	193		T5	4		T10	2
valid_sources[0x57]	9919	1			T1	154		T5	5		T10	1
valid_sources[0x58]	13515	1			T1	197		T5	2		T10	1
valid_sources[0x59]	9698	1			T1	206		T5	1		T10	2
valid_sources[0x5a]	10832	1			T1	188		T5	12		T20	7
valid_sources[0x5b]	9690	1			T1	171		T5	5		T10	1
valid_sources[0x5c]	9968	1			T1	213		T5	9		T10	1
valid_sources[0x5d]	15972	1			T1	177		T5	7		T10	1
valid_sources[0x5e]	11495	1			T1	193		T2	43		T5	1
valid_sources[0x5f]	9839	1			T1	207		T5	4		T10	4
valid_sources[0x60]	11354	1			T1	177		T2	33		T5	1
valid_sources[0x61]	9931	1			T1	193		T5	2		T10	1
valid_sources[0x62]	10000	1			T1	167		T10	1		T9	1
valid_sources[0x63]	9743	1			T1	189		T5	5		T10	5
valid_sources[0x64]	10455	1			T1	181		T5	5		T10	1
valid_sources[0x65]	10063	1			T1	184		T5	4		T10	3
valid_sources[0x66]	118504	1			T1	207		T10	1		T20	2
valid_sources[0x67]	9813	1			T1	205		T5	19		T20	11
valid_sources[0x68]	10372	1			T1	199		T5	5		T10	2
valid_sources[0x69]	9755	1			T1	171		T5	3		T10	1
valid_sources[0x6a]	9341	1			T1	161		T5	1		T11	1
valid_sources[0x6b]	13153	1			T1	200		T5	9		T11	2
valid_sources[0x6c]	11565	1			T1	191		T5	2		T11	1
valid_sources[0x6d]	9867	1			T1	192		T5	5		T11	1
valid_sources[0x6e]	9611	1			T1	207		T5	9		T10	3
valid_sources[0x6f]	9573	1			T1	171		T10	3		T11	2
valid_sources[0x70]	11740	1			T1	191		T5	5		T11	1
valid_sources[0x71]	10156	1			T1	169		T5	19		T10	2
valid_sources[0x72]	10041	1			T1	196		T2	29		T5	4
valid_sources[0x73]	11270	1			T1	157		T5	5		T20	2
valid_sources[0x74]	34422	1			T1	211		T5	1		T10	1
valid_sources[0x75]	96785	1			T1	159		T5	7		T10	3
valid_sources[0x76]	9559	1			T1	183		T2	6		T5	16
valid_sources[0x77]	9628	1			T1	151		T5	3		T10	3
valid_sources[0x78]	10275	1			T1	172		T5	2		T10	1
valid_sources[0x79]	9975	1			T1	187		T10	3		T11	1
valid_sources[0x7a]	9865	1			T1	191		T5	10		T10	2
valid_sources[0x7b]	12325	1			T1	188		T5	4		T10	1
valid_sources[0x7c]	11659	1			T1	200		T5	8		T11	1
valid_sources[0x7d]	10350	1			T1	217		T2	1		T20	5
valid_sources[0x7e]	10082	1			T1	199		T5	15		T20	6
valid_sources[0x7f]	9891	1			T1	191		T10	2		T20	5
valid_sources[0x80]	9627	1			T1	191		T5	3		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1534928

1

T1

23272

T2

85

T4

178

values[0x0]

all_enables

biggest_size

146499

1

T1

479

T2

43

T3

8

values[0x1]

all_enables

biggest_size

145249

1

T1

514

T2

44

T3

2