Unified Coverage Report :: Module :: tlul_cmd_intg_gen

Module : tlul_cmd_intg_gen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tap_tlul_host.u_cmd_intg_gen	100.00	100.00					100.00

---

Module Instance : tb.dut.u_tap_tlul_host.u_cmd_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.78	95.45	91.67			100.00	100.00	u_tap_tlul_host

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_data_gen	100.00	100.00
u_cmd_gen	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_cmd_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	20	1	1	100.00
CONT_ASSIGN	33	1	1	100.00
ALWAYS	46	4	4	100.00
CONT_ASSIGN	54	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_cmd_intg_gen.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
20	1	1
33	1	1
46	1	1
47	1	1
48	1	1
49	1	1
54	1	1

---

Assert Coverage for Module : tlul_cmd_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayMaxWidthCheck_A	817	817	0	0

PayMaxWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	817	817	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0