Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	105487984	13905	0	0
claim_transition_if_regwen_rd_A	105487984	1641	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105487984	13905	0	0
T25	32776	0	0	0
T36	0	9	0	0
T48	0	3	0	0
T57	180326	1	0	0
T82	0	2	0	0
T140	0	12	0	0
T141	0	1	0	0
T142	0	7	0	0
T143	0	2	0	0
T144	0	13	0	0
T145	0	7	0	0
T146	32965	0	0	0
T147	17825	0	0	0
T148	43255	0	0	0
T149	1393	0	0	0
T150	4370	0	0	0
T151	98157	0	0	0
T152	79717	0	0	0
T153	25373	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105487984	1641	0	0
T37	20115	0	0	0
T50	108016	0	0	0
T82	179268	5	0	0
T89	22964	0	0	0
T90	29778	0	0	0
T91	5973	0	0	0
T92	1447	0	0	0
T99	0	7	0	0
T103	0	8	0	0
T130	0	254	0	0
T154	0	7	0	0
T155	0	3	0	0
T156	0	4	0	0
T157	0	13	0	0
T158	0	14	0	0
T159	0	56	0	0
T160	37798	0	0	0
T161	13480	0	0	0
T162	32450	0	0	0