Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1890204	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2118618

1

T1

390

T2

9

T3

273

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3652681	1			T1	460		T3	322		T5	78
values[0x0]	178021	1			T1	95		T2	22		T3	77
values[0x1]	178120	1			T1	97		T2	23		T3	67

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1502831	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2505991

1

T1

445

T2

14

T3

304

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11163	1			T1	3		T12	8		T18	15
valid_sources[0x01]	11711	1			T12	7		T18	1		T19	3
valid_sources[0x02]	12853	1			T1	4		T5	1		T12	9
valid_sources[0x03]	12956	1			T1	4		T12	3		T18	6
valid_sources[0x04]	12389	1			T1	3		T12	9		T18	9
valid_sources[0x05]	11259	1			T5	1		T12	11		T18	15
valid_sources[0x06]	14699	1			T1	4		T3	2		T5	1
valid_sources[0x07]	11923	1			T1	3		T5	2		T12	6
valid_sources[0x08]	12567	1			T1	5		T12	14		T18	2
valid_sources[0x09]	14822	1			T1	1		T3	1		T12	9
valid_sources[0x0a]	11478	1			T1	2		T5	1		T12	3
valid_sources[0x0b]	11777	1			T1	1		T12	7		T18	3
valid_sources[0x0c]	14682	1			T1	2		T5	1		T12	7
valid_sources[0x0d]	14487	1			T1	4		T12	10		T18	8
valid_sources[0x0e]	13066	1			T1	2		T12	19		T18	10
valid_sources[0x0f]	11502	1			T1	5		T12	11		T19	4
valid_sources[0x10]	13958	1			T1	2		T12	15		T18	4
valid_sources[0x11]	12526	1			T1	2		T12	6		T18	7
valid_sources[0x12]	11568	1			T1	3		T5	1		T12	13
valid_sources[0x13]	12080	1			T1	2		T5	1		T12	3
valid_sources[0x14]	13194	1			T1	6		T12	6		T19	4
valid_sources[0x15]	52059	1			T1	3		T12	5		T18	11
valid_sources[0x16]	11639	1			T1	4		T3	5		T12	7
valid_sources[0x17]	11945	1			T1	5		T5	1		T12	9
valid_sources[0x18]	13911	1			T3	1		T12	7		T18	7
valid_sources[0x19]	13180	1			T1	3		T12	6		T18	4
valid_sources[0x1a]	12149	1			T1	2		T3	2		T12	9
valid_sources[0x1b]	12913	1			T1	1		T12	16		T19	10
valid_sources[0x1c]	13510	1			T1	5		T12	5		T18	3
valid_sources[0x1d]	13273	1			T1	5		T12	6		T18	3
valid_sources[0x1e]	13838	1			T1	3		T3	12		T12	10
valid_sources[0x1f]	10989	1			T1	5		T12	6		T18	6
valid_sources[0x20]	12363	1			T1	4		T12	8		T18	7
valid_sources[0x21]	13347	1			T1	2		T5	2		T12	14
valid_sources[0x22]	11851	1			T1	2		T12	4		T18	9
valid_sources[0x23]	11704	1			T1	1		T5	2		T12	7
valid_sources[0x24]	13797	1			T5	1		T12	6		T18	8
valid_sources[0x25]	12425	1			T1	2		T5	1		T12	6
valid_sources[0x26]	12325	1			T12	11		T18	4		T19	4
valid_sources[0x27]	11252	1			T1	5		T12	9		T18	1
valid_sources[0x28]	11528	1			T1	5		T12	9		T18	4
valid_sources[0x29]	11963	1			T1	2		T12	11		T19	3
valid_sources[0x2a]	12455	1			T1	2		T12	13		T18	12
valid_sources[0x2b]	14617	1			T1	3		T5	2		T12	5
valid_sources[0x2c]	12667	1			T1	2		T12	8		T18	2
valid_sources[0x2d]	11685	1			T1	2		T5	1		T12	4
valid_sources[0x2e]	13817	1			T1	3		T5	2		T12	10
valid_sources[0x2f]	12923	1			T1	2		T5	2		T12	6
valid_sources[0x30]	11986	1			T1	1		T12	8		T18	3
valid_sources[0x31]	12798	1			T12	10		T18	2		T19	4
valid_sources[0x32]	13024	1			T1	8		T12	16		T18	2
valid_sources[0x33]	46269	1			T1	5		T5	1		T9	34
valid_sources[0x34]	96296	1			T1	3		T12	9		T18	3
valid_sources[0x35]	13734	1			T1	3		T3	11		T12	12
valid_sources[0x36]	14944	1			T1	1		T12	7		T18	8
valid_sources[0x37]	11953	1			T5	1		T12	7		T18	2
valid_sources[0x38]	11677	1			T1	6		T12	12		T18	6
valid_sources[0x39]	11706	1			T1	5		T3	13		T12	10
valid_sources[0x3a]	60810	1			T1	3		T3	41		T12	7
valid_sources[0x3b]	12037	1			T1	5		T12	15		T18	11
valid_sources[0x3c]	14638	1			T1	7		T3	5		T12	12
valid_sources[0x3d]	13992	1			T1	1		T5	1		T12	6
valid_sources[0x3e]	11320	1			T1	4		T5	1		T12	13
valid_sources[0x3f]	11785	1			T12	9		T18	1		T19	2
valid_sources[0x40]	11562	1			T12	8		T18	5		T19	1
valid_sources[0x41]	14053	1			T1	1		T5	1		T12	7
valid_sources[0x42]	12486	1			T1	3		T12	13		T18	1
valid_sources[0x43]	12006	1			T12	8		T18	1		T13	1
valid_sources[0x44]	11286	1			T1	2		T12	11		T18	6
valid_sources[0x45]	12954	1			T1	2		T12	13		T18	4
valid_sources[0x46]	12842	1			T1	2		T12	3		T18	4
valid_sources[0x47]	12577	1			T1	2		T5	1		T12	8
valid_sources[0x48]	12449	1			T1	1		T12	18		T18	3
valid_sources[0x49]	59179	1			T1	1		T12	8		T18	1
valid_sources[0x4a]	12472	1			T5	3		T12	11		T18	9
valid_sources[0x4b]	11370	1			T1	5		T12	8		T18	19
valid_sources[0x4c]	29507	1			T1	4		T12	8		T19	6
valid_sources[0x4d]	12739	1			T1	3		T5	3		T12	10
valid_sources[0x4e]	18138	1			T1	4		T12	9		T19	13
valid_sources[0x4f]	12413	1			T2	45		T12	11		T13	3
valid_sources[0x50]	12467	1			T1	1		T12	13		T18	7
valid_sources[0x51]	11012	1			T1	2		T12	11		T18	6
valid_sources[0x52]	11886	1			T1	8		T5	5		T12	6
valid_sources[0x53]	12469	1			T1	2		T5	2		T12	7
valid_sources[0x54]	12089	1			T1	1		T12	6		T18	1
valid_sources[0x55]	73966	1			T1	1		T12	7		T18	7
valid_sources[0x56]	84626	1			T1	5		T12	17		T18	5
valid_sources[0x57]	14195	1			T1	1		T10	264		T12	11
valid_sources[0x58]	13528	1			T1	1		T12	10		T18	4
valid_sources[0x59]	13692	1			T1	2		T12	9		T18	5
valid_sources[0x5a]	12396	1			T1	7		T12	9		T18	7
valid_sources[0x5b]	12058	1			T1	3		T12	8		T18	3
valid_sources[0x5c]	16576	1			T12	8		T19	3		T13	5
valid_sources[0x5d]	12356	1			T1	3		T5	1		T12	8
valid_sources[0x5e]	11836	1			T1	4		T3	7		T12	11
valid_sources[0x5f]	12332	1			T1	2		T5	1		T12	17
valid_sources[0x60]	11976	1			T1	2		T5	1		T12	4
valid_sources[0x61]	11839	1			T1	4		T5	3		T12	8
valid_sources[0x62]	12099	1			T1	5		T12	9		T18	5
valid_sources[0x63]	23898	1			T1	5		T5	1		T12	13
valid_sources[0x64]	11673	1			T1	3		T3	21		T5	3
valid_sources[0x65]	23729	1			T1	2		T5	1		T12	9
valid_sources[0x66]	13742	1			T1	3		T12	6		T19	5
valid_sources[0x67]	32922	1			T3	8		T12	8		T18	3
valid_sources[0x68]	14028	1			T1	3		T12	11		T18	4
valid_sources[0x69]	12913	1			T1	1		T12	17		T18	7
valid_sources[0x6a]	18769	1			T1	2		T3	6		T12	4
valid_sources[0x6b]	13033	1			T1	1		T12	6		T18	6
valid_sources[0x6c]	13111	1			T1	2		T12	12		T18	9
valid_sources[0x6d]	11077	1			T1	3		T5	1		T12	12
valid_sources[0x6e]	13437	1			T1	3		T12	12		T18	7
valid_sources[0x6f]	16299	1			T12	9		T13	7		T16	4
valid_sources[0x70]	12712	1			T1	1		T5	1		T11	4
valid_sources[0x71]	12621	1			T1	6		T12	16		T18	6
valid_sources[0x72]	61103	1			T1	6		T5	2		T12	20
valid_sources[0x73]	84505	1			T1	4		T3	3		T12	15
valid_sources[0x74]	11884	1			T1	2		T12	10		T18	1
valid_sources[0x75]	13761	1			T1	2		T12	10		T18	7
valid_sources[0x76]	11475	1			T1	5		T3	8		T12	6
valid_sources[0x77]	12053	1			T1	1		T5	3		T12	6
valid_sources[0x78]	13384	1			T1	1		T12	6		T18	5
valid_sources[0x79]	12480	1			T1	4		T12	11		T19	10
valid_sources[0x7a]	12843	1			T1	7		T3	19		T5	2
valid_sources[0x7b]	14362	1			T1	4		T12	13		T18	3
valid_sources[0x7c]	12468	1			T1	2		T12	8		T18	2
valid_sources[0x7d]	11672	1			T1	4		T5	1		T12	15
valid_sources[0x7e]	12059	1			T1	2		T3	8		T12	12
valid_sources[0x7f]	12509	1			T1	1		T12	8		T18	3
valid_sources[0x80]	15356	1			T1	1		T5	3		T12	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1811327

1

T1

222

T3

142

T5

31

values[0x0]

all_enables

biggest_size

154562

1

T1

86

T2

6

T3

69

values[0x1]

all_enables

biggest_size

152729

1

T1

82

T2

3

T3

62