Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	124778729	14198	0	0
claim_transition_if_regwen_rd_A	124778729	1759	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124778729	14198	0	0
T8	24155	0	0	0
T14	127407	1	0	0
T15	461089	1	0	0
T21	73156	0	0	0
T22	33722	0	0	0
T23	111648	0	0	0
T38	0	13	0	0
T41	33479	0	0	0
T44	31731	0	0	0
T53	0	20	0	0
T134	0	2	0	0
T135	0	4	0	0
T136	0	3	0	0
T137	0	5	0	0
T138	0	2	0	0
T139	0	3	0	0
T140	1481	0	0	0
T141	1158	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124778729	1759	0	0
T8	24155	0	0	0
T14	127407	2	0	0
T15	461089	1	0	0
T21	73156	0	0	0
T22	33722	0	0	0
T23	111648	0	0	0
T41	33479	0	0	0
T44	31731	0	0	0
T90	0	7	0	0
T96	0	6	0	0
T134	0	19	0	0
T135	0	2	0	0
T137	0	7	0	0
T138	0	8	0	0
T140	1481	0	0	0
T141	1158	0	0	0
T142	0	10	0	0
T143	0	4	0	0