Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1720678	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1946810

1

T2

5

T3

738

T4

615

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3312460	1			T3	664		T4	501		T6	139
values[0x0]	177754	1			T2	4		T3	235		T4	235
values[0x1]	177274	1			T2	8		T3	237		T4	229

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1366603	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2300885

1

T2

5

T3

823

T4

718

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13718	1			T6	3		T12	85		T14	74
valid_sources[0x01]	11176	1			T3	1		T4	8		T12	74
valid_sources[0x02]	10736	1			T4	7		T6	1		T12	85
valid_sources[0x03]	11156	1			T3	17		T4	5		T12	90
valid_sources[0x04]	10957	1			T4	1		T12	65		T14	62
valid_sources[0x05]	11555	1			T4	2		T12	81		T14	80
valid_sources[0x06]	10986	1			T3	19		T4	4		T12	80
valid_sources[0x07]	107760	1			T4	2		T6	2		T12	68
valid_sources[0x08]	12560	1			T4	5		T12	64		T22	1237
valid_sources[0x09]	35660	1			T12	79		T14	70		T81	3
valid_sources[0x0a]	93286	1			T4	2		T12	68		T14	63
valid_sources[0x0b]	11157	1			T4	4		T6	2		T12	76
valid_sources[0x0c]	11040	1			T2	1		T3	79		T6	1
valid_sources[0x0d]	11237	1			T4	3		T6	2		T12	97
valid_sources[0x0e]	50000	1			T4	5		T6	1		T12	71
valid_sources[0x0f]	11016	1			T2	1		T4	8		T6	1
valid_sources[0x10]	10892	1			T4	1		T10	207		T12	79
valid_sources[0x11]	12639	1			T3	68		T4	4		T12	73
valid_sources[0x12]	14315	1			T4	7		T12	66		T14	54
valid_sources[0x13]	12840	1			T4	2		T10	211		T12	72
valid_sources[0x14]	25429	1			T2	1		T4	1		T6	3
valid_sources[0x15]	14896	1			T4	4		T6	3		T12	85
valid_sources[0x16]	13424	1			T4	6		T12	81		T14	56
valid_sources[0x17]	11314	1			T4	8		T6	3		T12	68
valid_sources[0x18]	11240	1			T2	1		T4	2		T6	2
valid_sources[0x19]	148440	1			T4	7		T12	66		T14	94
valid_sources[0x1a]	12740	1			T4	1		T6	1		T12	88
valid_sources[0x1b]	10712	1			T4	2		T12	82		T14	75
valid_sources[0x1c]	19419	1			T3	3		T4	3		T6	3
valid_sources[0x1d]	12690	1			T4	7		T12	92		T14	44
valid_sources[0x1e]	10887	1			T4	6		T10	53		T12	67
valid_sources[0x1f]	12722	1			T4	4		T10	226		T12	67
valid_sources[0x20]	10851	1			T4	9		T10	64		T12	89
valid_sources[0x21]	11032	1			T4	1		T12	77		T14	73
valid_sources[0x22]	10795	1			T4	6		T12	89		T14	71
valid_sources[0x23]	10717	1			T4	2		T6	1		T12	69
valid_sources[0x24]	10914	1			T2	1		T4	4		T12	79
valid_sources[0x25]	11404	1			T3	3		T4	4		T12	75
valid_sources[0x26]	10873	1			T4	3		T12	71		T14	72
valid_sources[0x27]	10787	1			T4	3		T6	1		T12	86
valid_sources[0x28]	11556	1			T4	2		T12	83		T14	62
valid_sources[0x29]	10921	1			T3	13		T4	7		T12	79
valid_sources[0x2a]	10802	1			T3	24		T4	5		T12	84
valid_sources[0x2b]	11364	1			T3	12		T4	4		T12	82
valid_sources[0x2c]	11147	1			T4	3		T12	74		T14	45
valid_sources[0x2d]	11962	1			T4	4		T12	77		T14	79
valid_sources[0x2e]	10880	1			T4	6		T6	3		T12	89
valid_sources[0x2f]	10777	1			T4	1		T6	10		T12	88
valid_sources[0x30]	18279	1			T3	19		T4	4		T12	67
valid_sources[0x31]	13416	1			T4	5		T12	79		T14	71
valid_sources[0x32]	10818	1			T4	3		T12	87		T14	58
valid_sources[0x33]	10895	1			T4	2		T12	78		T14	48
valid_sources[0x34]	11097	1			T4	3		T12	76		T14	70
valid_sources[0x35]	23982	1			T4	2		T12	78		T14	66
valid_sources[0x36]	11122	1			T4	1		T12	78		T14	76
valid_sources[0x37]	11333	1			T4	2		T10	19		T12	75
valid_sources[0x38]	11035	1			T4	9		T6	2		T12	81
valid_sources[0x39]	10597	1			T4	1		T6	6		T12	65
valid_sources[0x3a]	10961	1			T3	13		T4	3		T12	82
valid_sources[0x3b]	10889	1			T4	4		T6	2		T12	97
valid_sources[0x3c]	10339	1			T4	2		T6	1		T12	85
valid_sources[0x3d]	16196	1			T4	2		T6	1		T12	82
valid_sources[0x3e]	19260	1			T4	7		T12	82		T14	66
valid_sources[0x3f]	17820	1			T3	12		T4	1		T12	88
valid_sources[0x40]	11126	1			T4	3		T6	1		T12	66
valid_sources[0x41]	11142	1			T4	3		T6	2		T10	10
valid_sources[0x42]	42989	1			T4	4		T12	69		T14	71
valid_sources[0x43]	10772	1			T4	5		T6	3		T12	84
valid_sources[0x44]	10965	1			T4	2		T6	3		T12	81
valid_sources[0x45]	10843	1			T4	6		T6	1		T10	44
valid_sources[0x46]	10981	1			T4	6		T12	76		T14	66
valid_sources[0x47]	10952	1			T2	1		T4	2		T10	108
valid_sources[0x48]	11162	1			T2	1		T6	1		T10	26
valid_sources[0x49]	10684	1			T3	7		T4	7		T12	58
valid_sources[0x4a]	11101	1			T4	3		T6	3		T12	77
valid_sources[0x4b]	11980	1			T12	84		T14	85		T81	4
valid_sources[0x4c]	10946	1			T4	6		T12	76		T14	58
valid_sources[0x4d]	11008	1			T4	5		T6	3		T12	82
valid_sources[0x4e]	10871	1			T4	7		T6	9		T12	80
valid_sources[0x4f]	11033	1			T4	7		T12	84		T14	52
valid_sources[0x50]	16765	1			T4	6		T6	2		T12	80
valid_sources[0x51]	11039	1			T4	4		T12	81		T14	54
valid_sources[0x52]	10983	1			T3	32		T4	2		T6	1
valid_sources[0x53]	11125	1			T4	5		T6	2		T12	85
valid_sources[0x54]	21448	1			T4	4		T6	3		T12	78
valid_sources[0x55]	10961	1			T4	4		T12	84		T14	72
valid_sources[0x56]	11691	1			T10	89		T12	95		T14	73
valid_sources[0x57]	11038	1			T3	19		T4	3		T6	1
valid_sources[0x58]	24065	1			T4	2		T6	2		T12	80
valid_sources[0x59]	10740	1			T4	3		T12	69		T14	53
valid_sources[0x5a]	10916	1			T3	36		T4	4		T12	85
valid_sources[0x5b]	17404	1			T3	1		T4	4		T12	72
valid_sources[0x5c]	11978	1			T4	3		T6	2		T12	86
valid_sources[0x5d]	10819	1			T4	1		T6	1		T12	81
valid_sources[0x5e]	12144	1			T3	32		T4	3		T12	86
valid_sources[0x5f]	10834	1			T4	2		T6	1		T12	97
valid_sources[0x60]	11306	1			T4	1		T12	76		T14	58
valid_sources[0x61]	10573	1			T12	72		T14	32		T81	3
valid_sources[0x62]	13939	1			T3	22		T4	1		T6	1
valid_sources[0x63]	10805	1			T4	3		T6	2		T12	75
valid_sources[0x64]	11234	1			T4	2		T6	1		T12	68
valid_sources[0x65]	10901	1			T4	2		T12	67		T14	64
valid_sources[0x66]	10867	1			T4	5		T6	1		T12	80
valid_sources[0x67]	14385	1			T4	3		T6	3		T12	80
valid_sources[0x68]	10883	1			T4	4		T12	76		T14	83
valid_sources[0x69]	10374	1			T3	41		T4	4		T6	1
valid_sources[0x6a]	12870	1			T4	4		T12	92		T14	61
valid_sources[0x6b]	12243	1			T3	4		T4	3		T12	74
valid_sources[0x6c]	10643	1			T2	1		T3	3		T4	3
valid_sources[0x6d]	11389	1			T4	6		T6	1		T12	99
valid_sources[0x6e]	10810	1			T4	4		T12	78		T14	55
valid_sources[0x6f]	11374	1			T4	2		T6	2		T12	88
valid_sources[0x70]	12338	1			T3	33		T4	1		T12	78
valid_sources[0x71]	11244	1			T2	1		T4	2		T6	4
valid_sources[0x72]	10769	1			T4	7		T6	5		T12	97
valid_sources[0x73]	11421	1			T4	3		T12	86		T14	56
valid_sources[0x74]	10917	1			T3	29		T4	9		T12	82
valid_sources[0x75]	15555	1			T4	8		T12	86		T14	52
valid_sources[0x76]	11017	1			T3	15		T4	7		T12	77
valid_sources[0x77]	16962	1			T4	5		T6	2		T12	77
valid_sources[0x78]	11391	1			T3	24		T4	5		T12	82
valid_sources[0x79]	10944	1			T4	4		T6	4		T12	88
valid_sources[0x7a]	11202	1			T4	2		T10	106		T12	104
valid_sources[0x7b]	12587	1			T4	4		T6	2		T12	100
valid_sources[0x7c]	11089	1			T4	1		T12	77		T14	57
valid_sources[0x7d]	10692	1			T4	6		T12	67		T14	46
valid_sources[0x7e]	12796	1			T4	2		T12	92		T14	52
valid_sources[0x7f]	10842	1			T4	6		T6	3		T12	80
valid_sources[0x80]	13537	1			T4	10		T6	2		T12	82

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1640841

1

T3

325

T4

205

T6

79

values[0x0]

all_enables

biggest_size

153966

1

T2

3

T3

205

T4

211

values[0x1]

all_enables

biggest_size

152003

1

T2

2

T3

208

T4

199