Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	115315055	14356	0	0
claim_transition_if_regwen_rd_A	115315055	1376	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115315055	14356	0	0
T15	272909	1	0	0
T17	0	13	0	0
T34	217736	5	0	0
T53	0	5	0	0
T58	40726	0	0	0
T86	0	5	0	0
T97	0	2	0	0
T111	61949	0	0	0
T139	0	1	0	0
T140	0	2	0	0
T141	0	15	0	0
T142	0	1	0	0
T143	17064	0	0	0
T144	15338	0	0	0
T145	32959	0	0	0
T146	23953	0	0	0
T147	10067	0	0	0
T148	10903	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115315055	1376	0	0
T31	27758	0	0	0
T64	4187	0	0	0
T66	0	8	0	0
T105	0	78	0	0
T112	0	17	0	0
T132	0	35	0	0
T139	207053	3	0	0
T149	0	279	0	0
T150	0	3	0	0
T151	0	52	0	0
T152	0	20	0	0
T153	0	8	0	0
T154	38360	0	0	0
T155	6030	0	0	0
T156	32940	0	0	0
T157	26541	0	0	0
T158	15878	0	0	0
T159	47285	0	0	0
T160	21200	0	0	0