Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1882187	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2107282

1

T2

388

T3

166

T9

1600

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3638469	1			T2	453		T3	129		T9	2282
values[0x0]	174843	1			T2	99		T3	54		T9	249
values[0x1]	176157	1			T2	109		T3	82		T9	263

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1495583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2493886

1

T2

447

T3

192

T9

1872

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12244	1			T2	2		T9	28		T11	12
valid_sources[0x01]	13001	1			T9	14		T11	15		T13	8
valid_sources[0x02]	14590	1			T2	12		T9	30		T13	6
valid_sources[0x03]	12612	1			T2	4		T9	3		T11	9
valid_sources[0x04]	15766	1			T2	1		T9	7		T11	12
valid_sources[0x05]	12753	1			T9	14		T11	17		T13	4
valid_sources[0x06]	12964	1			T2	2		T9	2		T11	3
valid_sources[0x07]	14126	1			T2	1		T9	10		T11	5
valid_sources[0x08]	12439	1			T2	3		T9	12		T11	11
valid_sources[0x09]	12702	1			T2	6		T9	6		T11	7
valid_sources[0x0a]	12165	1			T2	3		T9	17		T11	7
valid_sources[0x0b]	12269	1			T2	6		T9	15		T11	6
valid_sources[0x0c]	12918	1			T9	20		T11	3		T13	12
valid_sources[0x0d]	12549	1			T9	6		T11	6		T13	3
valid_sources[0x0e]	14606	1			T2	2		T9	1		T11	3
valid_sources[0x0f]	14230	1			T2	1		T9	10		T11	6
valid_sources[0x10]	24441	1			T2	3		T9	16		T11	6
valid_sources[0x11]	12324	1			T2	3		T9	17		T11	9
valid_sources[0x12]	12668	1			T2	4		T9	7		T11	9
valid_sources[0x13]	12090	1			T2	5		T9	12		T11	1
valid_sources[0x14]	48158	1			T9	8		T11	12		T13	7
valid_sources[0x15]	20166	1			T2	2		T9	12		T11	3
valid_sources[0x16]	15910	1			T2	7		T9	5		T11	7
valid_sources[0x17]	12852	1			T9	10		T11	6		T12	5
valid_sources[0x18]	118635	1			T2	2		T9	11		T11	3
valid_sources[0x19]	13105	1			T2	4		T9	2		T11	8
valid_sources[0x1a]	13065	1			T2	1		T3	265		T9	17
valid_sources[0x1b]	29722	1			T2	1		T9	3		T11	5
valid_sources[0x1c]	15602	1			T2	1		T9	12		T11	3
valid_sources[0x1d]	13246	1			T2	4		T9	6		T11	2
valid_sources[0x1e]	13518	1			T2	3		T9	9		T10	282
valid_sources[0x1f]	13577	1			T2	4		T9	27		T11	8
valid_sources[0x20]	12663	1			T2	4		T9	12		T11	1
valid_sources[0x21]	12421	1			T2	3		T9	3		T11	4
valid_sources[0x22]	13871	1			T2	3		T9	14		T11	4
valid_sources[0x23]	13745	1			T2	2		T9	13		T11	3
valid_sources[0x24]	12496	1			T9	4		T11	14		T13	6
valid_sources[0x25]	17451	1			T9	15		T11	9		T13	6
valid_sources[0x26]	13830	1			T2	7		T9	7		T11	8
valid_sources[0x27]	12573	1			T2	4		T9	14		T11	4
valid_sources[0x28]	14489	1			T9	5		T11	8		T13	6
valid_sources[0x29]	12553	1			T2	1		T9	9		T11	7
valid_sources[0x2a]	16961	1			T2	2		T9	4		T11	8
valid_sources[0x2b]	12101	1			T9	13		T11	4		T12	6
valid_sources[0x2c]	24630	1			T2	3		T9	20		T11	7
valid_sources[0x2d]	12318	1			T2	1		T9	6		T11	2
valid_sources[0x2e]	12590	1			T2	2		T9	6		T11	7
valid_sources[0x2f]	12569	1			T2	1		T9	2		T11	1
valid_sources[0x30]	12686	1			T2	1		T9	18		T11	5
valid_sources[0x31]	13336	1			T2	3		T9	7		T11	12
valid_sources[0x32]	12412	1			T2	1		T9	3		T11	12
valid_sources[0x33]	13027	1			T2	2		T9	13		T11	5
valid_sources[0x34]	48006	1			T2	6		T9	7		T11	1
valid_sources[0x35]	12129	1			T2	4		T9	8		T13	1
valid_sources[0x36]	15681	1			T2	4		T9	33		T11	6
valid_sources[0x37]	12345	1			T2	1		T9	1		T11	11
valid_sources[0x38]	13048	1			T9	18		T11	18		T12	19
valid_sources[0x39]	12789	1			T9	33		T11	2		T13	12
valid_sources[0x3a]	15876	1			T2	1		T9	13		T11	9
valid_sources[0x3b]	13761	1			T2	2		T9	2		T11	21
valid_sources[0x3c]	12446	1			T2	4		T9	6		T11	5
valid_sources[0x3d]	12426	1			T2	2		T9	9		T11	4
valid_sources[0x3e]	12267	1			T2	6		T9	28		T11	16
valid_sources[0x3f]	13819	1			T2	2		T11	9		T13	8
valid_sources[0x40]	12355	1			T2	2		T9	10		T11	2
valid_sources[0x41]	12473	1			T2	2		T9	20		T11	5
valid_sources[0x42]	12639	1			T2	6		T9	13		T11	3
valid_sources[0x43]	15462	1			T2	3		T9	16		T11	8
valid_sources[0x44]	12456	1			T9	1		T11	8		T13	5
valid_sources[0x45]	12500	1			T2	2		T9	6		T11	14
valid_sources[0x46]	12656	1			T2	8		T9	9		T11	8
valid_sources[0x47]	13080	1			T9	10		T11	4		T13	5
valid_sources[0x48]	12628	1			T2	1		T9	2		T11	4
valid_sources[0x49]	12697	1			T2	3		T9	8		T11	4
valid_sources[0x4a]	36496	1			T2	2		T9	8		T11	5
valid_sources[0x4b]	12571	1			T2	3		T9	12		T11	4
valid_sources[0x4c]	12490	1			T2	4		T9	14		T11	6
valid_sources[0x4d]	15545	1			T9	10		T11	6		T13	4
valid_sources[0x4e]	12331	1			T2	4		T9	2		T12	6
valid_sources[0x4f]	12295	1			T2	8		T9	1		T11	9
valid_sources[0x50]	13027	1			T2	3		T9	8		T11	1
valid_sources[0x51]	11991	1			T2	1		T9	5		T11	14
valid_sources[0x52]	12597	1			T2	8		T9	15		T11	5
valid_sources[0x53]	35252	1			T2	2		T9	11		T13	9
valid_sources[0x54]	12987	1			T2	1		T9	17		T11	9
valid_sources[0x55]	12087	1			T2	1		T9	9		T11	17
valid_sources[0x56]	12497	1			T9	9		T11	21		T13	3
valid_sources[0x57]	12871	1			T9	8		T11	6		T12	5
valid_sources[0x58]	12346	1			T2	4		T9	9		T11	10
valid_sources[0x59]	12062	1			T9	17		T11	11		T13	4
valid_sources[0x5a]	15771	1			T9	18		T11	1		T13	7
valid_sources[0x5b]	12474	1			T2	1		T9	2		T11	15
valid_sources[0x5c]	12403	1			T9	11		T11	3		T12	7
valid_sources[0x5d]	12388	1			T9	8		T11	3		T12	28
valid_sources[0x5e]	14087	1			T2	1		T9	8		T11	6
valid_sources[0x5f]	13081	1			T2	1		T9	6		T11	10
valid_sources[0x60]	23688	1			T2	1		T9	3		T11	7
valid_sources[0x61]	12905	1			T9	28		T11	20		T13	12
valid_sources[0x62]	14363	1			T2	5		T9	8		T11	9
valid_sources[0x63]	12706	1			T9	12		T13	9		T45	8
valid_sources[0x64]	15016	1			T2	1		T9	5		T11	6
valid_sources[0x65]	14148	1			T2	4		T9	5		T11	1
valid_sources[0x66]	12758	1			T2	4		T9	4		T11	8
valid_sources[0x67]	14509	1			T2	6		T9	15		T11	7
valid_sources[0x68]	11989	1			T2	2		T9	14		T11	18
valid_sources[0x69]	12214	1			T2	2		T9	19		T11	4
valid_sources[0x6a]	14423	1			T2	2		T9	7		T11	11
valid_sources[0x6b]	13607	1			T9	3		T11	4		T13	9
valid_sources[0x6c]	12219	1			T2	8		T9	15		T11	11
valid_sources[0x6d]	12023	1			T9	9		T11	10		T13	5
valid_sources[0x6e]	12743	1			T2	4		T9	17		T11	9
valid_sources[0x6f]	12648	1			T2	9		T9	11		T11	6
valid_sources[0x70]	12848	1			T9	29		T11	6		T12	19
valid_sources[0x71]	13736	1			T2	2		T9	8		T11	19
valid_sources[0x72]	12408	1			T2	1		T9	9		T11	7
valid_sources[0x73]	12712	1			T9	21		T11	9		T13	7
valid_sources[0x74]	15628	1			T9	26		T11	7		T12	2
valid_sources[0x75]	12992	1			T2	1		T9	6		T11	9
valid_sources[0x76]	116243	1			T2	2		T9	7		T11	2
valid_sources[0x77]	12309	1			T2	3		T9	17		T11	6
valid_sources[0x78]	15664	1			T9	6		T11	12		T12	1
valid_sources[0x79]	13274	1			T2	4		T9	11		T11	1
valid_sources[0x7a]	13371	1			T2	1		T9	14		T11	3
valid_sources[0x7b]	13690	1			T2	6		T9	9		T11	16
valid_sources[0x7c]	12445	1			T2	12		T9	8		T11	14
valid_sources[0x7d]	12848	1			T2	8		T9	12		T11	5
valid_sources[0x7e]	14067	1			T2	10		T9	8		T11	2
valid_sources[0x7f]	12627	1			T2	5		T9	9		T11	7
valid_sources[0x80]	12388	1			T2	1		T9	5		T11	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1804985

1

T2

211

T3

57

T9

1160

values[0x0]

all_enables

biggest_size

151307

1

T2

84

T3

41

T9

215

values[0x1]

all_enables

biggest_size

150990

1

T2

93

T3

68

T9

225