Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	118058612	14617	0	0
claim_transition_if_regwen_rd_A	118058612	1118	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118058612	14617	0	0
T7	39484	0	0	0
T15	169261	4	0	0
T16	170448	9	0	0
T23	119915	0	0	0
T24	135729	0	0	0
T33	49619	0	0	0
T34	1837	0	0	0
T90	10826	0	0	0
T95	0	2	0	0
T109	0	3	0	0
T146	0	1	0	0
T147	0	18	0	0
T148	0	2	0	0
T149	0	13	0	0
T150	0	2	0	0
T151	0	1	0	0
T152	52091	0	0	0
T153	6172	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118058612	1118	0	0
T42	231636	0	0	0
T43	265376	0	0	0
T51	12343	0	0	0
T71	3769	0	0	0
T111	0	50	0	0
T126	0	18	0	0
T133	0	74	0	0
T154	314591	1	0	0
T155	0	2	0	0
T156	0	12	0	0
T157	0	25	0	0
T158	0	4	0	0
T159	0	5	0	0
T160	0	226	0	0
T161	23699	0	0	0
T162	21453	0	0	0
T163	1120	0	0	0
T164	26370	0	0	0
T165	1503	0	0	0