Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	987791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1176391

1

T1

75

T2

761

T3

2664

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1873426	1			T1	138		T2	569		T3	4432
values[0x0]	144919	1			T1	9		T2	303		T3	247
values[0x1]	145837	1			T1	17		T2	281		T3	225

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	782740	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1381442

1

T1

87

T2

868

T3

3141

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6956	1			T2	5		T3	18		T4	8
valid_sources[0x01]	8088	1			T2	1		T3	13		T4	5
valid_sources[0x02]	6550	1			T2	1		T3	17		T12	32
valid_sources[0x03]	8390	1			T2	2		T3	14		T10	17
valid_sources[0x04]	6903	1			T2	12		T3	15		T4	4
valid_sources[0x05]	26806	1			T2	2		T3	14		T4	7
valid_sources[0x06]	6751	1			T2	9		T3	17		T14	13
valid_sources[0x07]	6477	1			T2	2		T3	21		T4	2
valid_sources[0x08]	6690	1			T2	7		T3	19		T4	5
valid_sources[0x09]	6904	1			T2	3		T3	21		T4	6
valid_sources[0x0a]	7038	1			T2	3		T3	21		T4	16
valid_sources[0x0b]	6407	1			T2	2		T3	20		T4	14
valid_sources[0x0c]	6682	1			T2	4		T3	19		T10	17
valid_sources[0x0d]	6805	1			T2	7		T3	17		T4	21
valid_sources[0x0e]	6872	1			T3	23		T4	20		T14	4
valid_sources[0x0f]	6988	1			T2	8		T3	16		T4	30
valid_sources[0x10]	6646	1			T2	3		T3	26		T4	9
valid_sources[0x11]	6917	1			T2	5		T3	14		T4	4
valid_sources[0x12]	6548	1			T2	4		T3	13		T4	3
valid_sources[0x13]	10732	1			T2	1		T3	19		T4	3
valid_sources[0x14]	6671	1			T2	2		T3	16		T4	2
valid_sources[0x15]	7864	1			T2	5		T3	14		T4	3
valid_sources[0x16]	6551	1			T2	7		T3	17		T4	7
valid_sources[0x17]	6906	1			T2	4		T3	18		T4	11
valid_sources[0x18]	7128	1			T2	7		T3	20		T14	8
valid_sources[0x19]	8424	1			T2	4		T3	16		T14	9
valid_sources[0x1a]	6630	1			T2	6		T3	24		T4	3
valid_sources[0x1b]	6652	1			T2	3		T3	20		T4	15
valid_sources[0x1c]	7623	1			T2	1		T3	17		T4	15
valid_sources[0x1d]	10417	1			T2	10		T3	23		T4	5
valid_sources[0x1e]	6878	1			T2	2		T3	21		T4	11
valid_sources[0x1f]	6487	1			T2	3		T3	19		T4	8
valid_sources[0x20]	22691	1			T2	5		T3	20		T4	8
valid_sources[0x21]	9222	1			T2	10		T3	18		T4	5
valid_sources[0x22]	37983	1			T2	4		T3	21		T4	13
valid_sources[0x23]	6909	1			T3	15		T4	26		T12	1
valid_sources[0x24]	7434	1			T2	3		T3	17		T4	35
valid_sources[0x25]	10772	1			T2	2		T3	24		T10	3842
valid_sources[0x26]	6500	1			T2	4		T3	23		T4	10
valid_sources[0x27]	6371	1			T2	8		T3	21		T4	7
valid_sources[0x28]	6892	1			T3	19		T4	21		T12	1
valid_sources[0x29]	6661	1			T2	3		T3	13		T4	5
valid_sources[0x2a]	6592	1			T2	8		T3	24		T4	14
valid_sources[0x2b]	6398	1			T2	5		T3	24		T4	13
valid_sources[0x2c]	7156	1			T3	27		T4	7		T12	1
valid_sources[0x2d]	7631	1			T2	8		T3	19		T4	11
valid_sources[0x2e]	6891	1			T2	10		T3	26		T4	31
valid_sources[0x2f]	6966	1			T2	3		T3	17		T4	22
valid_sources[0x30]	7749	1			T2	9		T3	13		T4	1
valid_sources[0x31]	6619	1			T2	1		T3	15		T4	14
valid_sources[0x32]	8816	1			T2	7		T3	10		T4	19
valid_sources[0x33]	6525	1			T2	9		T3	22		T4	18
valid_sources[0x34]	6556	1			T2	1		T3	24		T4	21
valid_sources[0x35]	7046	1			T2	6		T3	16		T4	10
valid_sources[0x36]	6727	1			T3	23		T4	11		T12	3
valid_sources[0x37]	9174	1			T2	5		T3	18		T4	2
valid_sources[0x38]	6513	1			T1	164		T2	4		T3	18
valid_sources[0x39]	6555	1			T2	5		T3	16		T12	9
valid_sources[0x3a]	6681	1			T2	1		T3	18		T4	5
valid_sources[0x3b]	7070	1			T2	9		T3	18		T4	20
valid_sources[0x3c]	7321	1			T2	5		T3	15		T10	17
valid_sources[0x3d]	6627	1			T2	5		T3	13		T4	8
valid_sources[0x3e]	6562	1			T2	3		T3	20		T4	4
valid_sources[0x3f]	8960	1			T2	8		T3	19		T13	12
valid_sources[0x40]	6639	1			T2	2		T3	16		T4	2
valid_sources[0x41]	7033	1			T2	9		T3	24		T4	2
valid_sources[0x42]	6674	1			T2	13		T3	10		T14	9
valid_sources[0x43]	6492	1			T2	8		T3	17		T4	2
valid_sources[0x44]	7718	1			T2	11		T3	16		T4	21
valid_sources[0x45]	6605	1			T2	2		T3	16		T4	5
valid_sources[0x46]	6871	1			T3	12		T4	3		T14	3
valid_sources[0x47]	6404	1			T2	6		T3	18		T4	2
valid_sources[0x48]	6819	1			T2	12		T3	23		T4	5
valid_sources[0x49]	7569	1			T2	3		T3	19		T4	13
valid_sources[0x4a]	7468	1			T2	3		T3	27		T4	7
valid_sources[0x4b]	6682	1			T2	4		T3	22		T4	11
valid_sources[0x4c]	7455	1			T2	2		T3	22		T4	10
valid_sources[0x4d]	6693	1			T2	1		T3	22		T12	7
valid_sources[0x4e]	6330	1			T2	1		T3	16		T4	2
valid_sources[0x4f]	6718	1			T2	5		T3	18		T4	19
valid_sources[0x50]	6593	1			T2	4		T3	26		T4	7
valid_sources[0x51]	9069	1			T2	1		T3	16		T4	18
valid_sources[0x52]	12040	1			T3	20		T4	13		T12	8
valid_sources[0x53]	6584	1			T2	1		T3	23		T4	14
valid_sources[0x54]	6134	1			T2	2		T3	21		T4	15
valid_sources[0x55]	6375	1			T2	5		T3	19		T4	25
valid_sources[0x56]	6295	1			T2	6		T3	15		T4	5
valid_sources[0x57]	6656	1			T2	3		T3	18		T4	8
valid_sources[0x58]	7392	1			T2	10		T3	17		T4	17
valid_sources[0x59]	6392	1			T2	4		T3	23		T4	18
valid_sources[0x5a]	8334	1			T2	10		T3	24		T4	3
valid_sources[0x5b]	6917	1			T2	6		T3	16		T4	17
valid_sources[0x5c]	6586	1			T2	6		T3	15		T4	25
valid_sources[0x5d]	6572	1			T2	9		T3	18		T4	7
valid_sources[0x5e]	6591	1			T2	3		T3	12		T4	14
valid_sources[0x5f]	8400	1			T2	4		T3	10		T4	45
valid_sources[0x60]	6538	1			T2	1		T3	13		T4	1
valid_sources[0x61]	7090	1			T2	8		T3	19		T4	5
valid_sources[0x62]	6635	1			T2	1		T3	15		T4	9
valid_sources[0x63]	6652	1			T2	6		T3	18		T4	39
valid_sources[0x64]	6812	1			T2	9		T3	9		T4	2
valid_sources[0x65]	7461	1			T2	24		T3	25		T4	19
valid_sources[0x66]	6353	1			T2	2		T3	26		T14	8
valid_sources[0x67]	21080	1			T2	3		T3	27		T4	32
valid_sources[0x68]	6725	1			T2	4		T3	23		T4	21
valid_sources[0x69]	7927	1			T2	1		T3	17		T4	16
valid_sources[0x6a]	6195	1			T2	2		T3	14		T4	4
valid_sources[0x6b]	7956	1			T2	6		T3	18		T14	13
valid_sources[0x6c]	63902	1			T2	1		T3	11		T14	7
valid_sources[0x6d]	7278	1			T3	22		T4	12		T12	4
valid_sources[0x6e]	6438	1			T2	7		T3	16		T4	10
valid_sources[0x6f]	9768	1			T2	7		T3	21		T4	20
valid_sources[0x70]	7789	1			T2	6		T3	23		T4	30
valid_sources[0x71]	7172	1			T2	2		T3	21		T4	64
valid_sources[0x72]	6297	1			T2	9		T3	15		T10	17
valid_sources[0x73]	8276	1			T2	2		T3	22		T4	20
valid_sources[0x74]	10595	1			T2	9		T3	17		T4	26
valid_sources[0x75]	6879	1			T2	9		T3	12		T4	19
valid_sources[0x76]	6527	1			T2	3		T3	15		T4	13
valid_sources[0x77]	6698	1			T2	6		T3	17		T4	13
valid_sources[0x78]	6653	1			T2	8		T3	15		T4	1
valid_sources[0x79]	6334	1			T2	5		T3	17		T14	11
valid_sources[0x7a]	7055	1			T2	3		T3	18		T4	12
valid_sources[0x7b]	6421	1			T2	2		T3	19		T4	9
valid_sources[0x7c]	6307	1			T2	5		T3	20		T4	4
valid_sources[0x7d]	6573	1			T2	4		T3	15		T4	4
valid_sources[0x7e]	7566	1			T2	6		T3	15		T4	13
valid_sources[0x7f]	6337	1			T2	8		T3	23		T4	17
valid_sources[0x80]	6302	1			T2	2		T3	22		T4	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

926343

1

T1

54

T2

244

T3

2261

values[0x0]

all_enables

biggest_size

125632

1

T1

9

T2

272

T3

212

values[0x1]

all_enables

biggest_size

124416

1

T1

12

T2

245

T3

191