Group : dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg
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Group Instance : mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 1 5 83.33


Variables for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 1 5 83.33 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 1 5 83.33


Variables for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 1 5 83.33 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 1 5 83.33


Variables for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 1 5 83.33 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[0].lc_tx_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[0].lc_tx_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[0].lc_tx_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[1].lc_tx_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[1].lc_tx_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[1].lc_tx_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 1 5 83.33


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
false 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 287 1 T3 6 T45 2 T46 2
others[1] 324 1 T3 4 T45 6 T46 4
others[2] 328 1 T3 4 T45 9 T46 5
others[3] 489 1 T3 8 T45 16 T46 10
true 44749 1 T1 3 T2 86 T3 60


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 1 5 83.33


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 275 1 T45 4 T46 2 T139 6
others[1] 293 1 T3 8 T45 2 T46 4
others[2] 259 1 T3 10 T45 7 T46 4
others[3] 542 1 T3 2 T45 18 T46 8
false 44751 1 T1 3 T2 86 T3 58


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 1 5 83.33


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
false 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 308 1 T3 6 T45 6 T46 6
others[1] 312 1 T3 2 T45 6 T46 8
others[2] 322 1 T3 6 T45 4 T139 4
others[3] 530 1 T3 6 T45 16 T46 10
true 44738 1 T1 3 T2 86 T3 57


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 152 1 T3 1 T45 2 T46 2
others[1] 174 1 T3 3 T45 6 T46 5
others[2] 168 1 T3 3 T45 2 T46 3
others[3] 224 1 T3 3 T45 2 T139 3
false 743530 1 T1 5 T2 86 T3 70
true 697941 1 T1 2 T4 5 T13 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 180 1 T3 8 T45 1 T46 4
others[1] 151 1 T3 3 T45 4 T46 4
others[2] 171 1 T3 4 T45 8 T46 3
others[3] 280 1 T3 5 T45 4 T46 4
false 1887456 1 T1 3 T2 86 T3 78
true 1841954 1 T3 2 T10 2 T4 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 180 1 T3 8 T45 1 T46 4
others[1] 151 1 T3 3 T45 4 T46 4
others[2] 171 1 T3 4 T45 8 T46 3
others[3] 280 1 T3 5 T45 4 T46 4
false 1887456 1 T1 3 T2 86 T3 78
true 1841954 1 T3 2 T10 2 T4 5

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