Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	67107912	14025	0	0
claim_transition_if_regwen_rd_A	67107912	910	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67107912	14025	0	0
T19	338776	21	0	0
T46	32563	0	0	0
T85	6684	0	0	0
T89	0	1	0	0
T90	0	16	0	0
T101	0	15	0	0
T102	0	13	0	0
T105	0	8	0	0
T133	0	2	0	0
T134	0	19	0	0
T135	0	2	0	0
T136	0	2	0	0
T137	1702	0	0	0
T138	1369	0	0	0
T139	22878	0	0	0
T140	40260	0	0	0
T141	36048	0	0	0
T142	28453	0	0	0
T143	8526	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67107912	910	0	0
T8	115322	0	0	0
T53	41722	0	0	0
T56	22372	0	0	0
T59	36843	0	0	0
T75	7299	0	0	0
T89	74026	6	0	0
T93	1385	0	0	0
T94	7927	0	0	0
T95	4239	0	0	0
T100	0	16	0	0
T103	0	12	0	0
T107	0	13	0	0
T133	0	2	0	0
T136	0	5	0	0
T144	0	33	0	0
T145	0	60	0	0
T146	0	5	0	0
T147	0	5	0	0
T148	1154	0	0	0