Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	657988	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

838667

1

T1

1385

T2

30

T3

185

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1211765	1			T1	1665		T2	22		T3	150
values[0x0]	142272	1			T1	316		T2	10		T3	70
values[0x1]	142618	1			T1	308		T2	8		T3	74

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	518788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

977867

1

T1

1572

T2

33

T3

210

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5040	1			T1	15		T4	9		T11	14
valid_sources[0x01]	5025	1			T1	12		T3	1		T4	10
valid_sources[0x02]	5049	1			T1	16		T4	3		T12	6
valid_sources[0x03]	4967	1			T1	14		T3	3		T4	3
valid_sources[0x04]	6538	1			T1	18		T4	8		T11	7
valid_sources[0x05]	5208	1			T1	1		T4	9		T11	1
valid_sources[0x06]	5177	1			T4	3		T11	4		T12	6
valid_sources[0x07]	6804	1			T1	12		T2	1		T3	1
valid_sources[0x08]	5010	1			T1	6		T3	1		T4	12
valid_sources[0x09]	5343	1			T1	3		T3	2		T4	6
valid_sources[0x0a]	5010	1			T1	13		T3	1		T4	13
valid_sources[0x0b]	7693	1			T1	14		T3	2		T4	16
valid_sources[0x0c]	4889	1			T1	4		T4	5		T11	3
valid_sources[0x0d]	4878	1			T1	2		T3	4		T4	11
valid_sources[0x0e]	4661	1			T1	10		T3	1		T4	2
valid_sources[0x0f]	5150	1			T1	7		T4	12		T11	3
valid_sources[0x10]	5080	1			T1	4		T3	1		T4	10
valid_sources[0x11]	4900	1			T1	6		T3	1		T4	9
valid_sources[0x12]	6744	1			T1	10		T4	10		T11	1
valid_sources[0x13]	6028	1			T1	6		T3	4		T4	11
valid_sources[0x14]	5161	1			T1	19		T3	2		T4	8
valid_sources[0x15]	6106	1			T1	27		T3	1		T4	6
valid_sources[0x16]	6458	1			T1	2		T3	1		T4	5
valid_sources[0x17]	4918	1			T2	1		T3	2		T4	13
valid_sources[0x18]	4824	1			T1	4		T3	1		T4	3
valid_sources[0x19]	10373	1			T1	10		T3	1		T4	1
valid_sources[0x1a]	5506	1			T1	12		T4	9		T11	4
valid_sources[0x1b]	5052	1			T1	2		T3	2		T4	7
valid_sources[0x1c]	5418	1			T1	5		T4	10		T11	5
valid_sources[0x1d]	6664	1			T1	6		T2	2		T3	3
valid_sources[0x1e]	5038	1			T1	4		T3	1		T4	16
valid_sources[0x1f]	6521	1			T1	10		T2	1		T3	1
valid_sources[0x20]	6440	1			T1	9		T3	3		T4	2
valid_sources[0x21]	4935	1			T1	7		T3	3		T4	7
valid_sources[0x22]	5369	1			T1	13		T3	1		T4	3
valid_sources[0x23]	4926	1			T3	3		T4	9		T11	2
valid_sources[0x24]	5098	1			T1	1		T3	2		T4	7
valid_sources[0x25]	5453	1			T1	5		T3	1		T4	13
valid_sources[0x26]	5056	1			T1	13		T4	7		T11	5
valid_sources[0x27]	10496	1			T1	9		T3	1		T4	4
valid_sources[0x28]	5950	1			T1	1		T3	1		T11	3
valid_sources[0x29]	6491	1			T1	14		T4	3		T11	8
valid_sources[0x2a]	4904	1			T1	6		T2	1		T4	4
valid_sources[0x2b]	4917	1			T4	4		T11	6		T12	6
valid_sources[0x2c]	5042	1			T1	11		T3	2		T4	13
valid_sources[0x2d]	6472	1			T1	7		T3	4		T4	6
valid_sources[0x2e]	4835	1			T1	1		T3	2		T4	19
valid_sources[0x2f]	4992	1			T1	6		T4	8		T11	8
valid_sources[0x30]	4923	1			T1	21		T3	1		T4	4
valid_sources[0x31]	5097	1			T1	9		T4	8		T11	1
valid_sources[0x32]	8877	1			T1	17		T3	1		T4	10
valid_sources[0x33]	5240	1			T1	5		T4	8		T11	8
valid_sources[0x34]	5119	1			T1	2		T4	8		T11	3
valid_sources[0x35]	5017	1			T1	19		T3	4		T4	20
valid_sources[0x36]	5869	1			T1	19		T3	2		T4	6
valid_sources[0x37]	5181	1			T1	7		T4	8		T11	3
valid_sources[0x38]	4933	1			T1	6		T3	1		T4	11
valid_sources[0x39]	4918	1			T1	4		T2	2		T4	7
valid_sources[0x3a]	4745	1			T1	15		T4	14		T11	3
valid_sources[0x3b]	5065	1			T1	10		T3	1		T4	11
valid_sources[0x3c]	4878	1			T1	4		T3	2		T4	8
valid_sources[0x3d]	4817	1			T1	10		T3	1		T4	11
valid_sources[0x3e]	4897	1			T1	7		T3	1		T4	9
valid_sources[0x3f]	13240	1			T1	12		T2	1		T3	1
valid_sources[0x40]	5048	1			T1	21		T4	11		T11	2
valid_sources[0x41]	5120	1			T1	15		T4	12		T11	8
valid_sources[0x42]	4810	1			T1	12		T2	1		T3	1
valid_sources[0x43]	4893	1			T1	19		T3	1		T4	6
valid_sources[0x44]	5206	1			T3	2		T4	7		T11	4
valid_sources[0x45]	5000	1			T1	14		T2	1		T3	2
valid_sources[0x46]	4930	1			T1	24		T3	2		T4	10
valid_sources[0x47]	4863	1			T1	11		T3	1		T4	15
valid_sources[0x48]	5310	1			T1	13		T3	2		T4	5
valid_sources[0x49]	5040	1			T1	3		T3	1		T4	9
valid_sources[0x4a]	5244	1			T1	2		T4	17		T12	11
valid_sources[0x4b]	7225	1			T1	11		T3	1		T4	5
valid_sources[0x4c]	4717	1			T1	7		T3	2		T4	11
valid_sources[0x4d]	8143	1			T1	4		T3	2		T4	8
valid_sources[0x4e]	4957	1			T1	9		T3	1		T4	4
valid_sources[0x4f]	8544	1			T3	2		T4	6		T11	1
valid_sources[0x50]	4816	1			T1	25		T3	2		T4	3
valid_sources[0x51]	5183	1			T1	13		T3	1		T4	13
valid_sources[0x52]	4870	1			T1	3		T3	2		T4	4
valid_sources[0x53]	13334	1			T1	17		T3	1		T4	11
valid_sources[0x54]	8027	1			T1	5		T3	1		T4	10
valid_sources[0x55]	5244	1			T1	14		T3	2		T4	8
valid_sources[0x56]	5242	1			T1	12		T4	7		T11	1
valid_sources[0x57]	5008	1			T1	8		T2	2		T4	12
valid_sources[0x58]	5035	1			T1	2		T2	2		T3	2
valid_sources[0x59]	4905	1			T1	10		T3	3		T4	5
valid_sources[0x5a]	9815	1			T1	5		T3	1		T4	5
valid_sources[0x5b]	5050	1			T1	4		T3	3		T4	7
valid_sources[0x5c]	4841	1			T1	10		T4	8		T11	8
valid_sources[0x5d]	4875	1			T1	4		T3	2		T4	6
valid_sources[0x5e]	5082	1			T1	6		T3	1		T4	4
valid_sources[0x5f]	5003	1			T1	12		T3	1		T4	12
valid_sources[0x60]	5094	1			T1	10		T3	2		T4	10
valid_sources[0x61]	4971	1			T1	2		T2	1		T3	3
valid_sources[0x62]	4911	1			T1	17		T3	1		T4	6
valid_sources[0x63]	5108	1			T1	4		T3	1		T4	12
valid_sources[0x64]	4774	1			T1	5		T3	1		T4	8
valid_sources[0x65]	5057	1			T1	24		T4	7		T11	7
valid_sources[0x66]	4921	1			T1	25		T3	1		T4	8
valid_sources[0x67]	4817	1			T1	14		T4	7		T11	10
valid_sources[0x68]	5187	1			T1	4		T3	1		T4	11
valid_sources[0x69]	5193	1			T1	2		T4	2		T11	2
valid_sources[0x6a]	5109	1			T1	3		T3	2		T4	12
valid_sources[0x6b]	4825	1			T1	12		T2	1		T4	7
valid_sources[0x6c]	6564	1			T1	7		T3	2		T4	8
valid_sources[0x6d]	4796	1			T1	3		T4	4		T11	1
valid_sources[0x6e]	5219	1			T1	3		T3	1		T4	11
valid_sources[0x6f]	5188	1			T1	29		T4	10		T11	4
valid_sources[0x70]	6819	1			T4	6		T11	9		T12	3
valid_sources[0x71]	4828	1			T2	1		T3	2		T4	16
valid_sources[0x72]	4961	1			T1	4		T3	2		T4	8
valid_sources[0x73]	5363	1			T1	6		T3	1		T4	13
valid_sources[0x74]	7601	1			T1	14		T3	2		T4	9
valid_sources[0x75]	5006	1			T1	28		T4	17		T11	5
valid_sources[0x76]	8828	1			T1	18		T3	2		T4	12
valid_sources[0x77]	9166	1			T1	11		T3	1		T4	10
valid_sources[0x78]	4934	1			T4	4		T11	5		T12	7
valid_sources[0x79]	5101	1			T1	8		T3	2		T4	10
valid_sources[0x7a]	4942	1			T1	18		T4	12		T11	1
valid_sources[0x7b]	5036	1			T1	6		T3	1		T4	17
valid_sources[0x7c]	4912	1			T1	15		T4	7		T11	9
valid_sources[0x7d]	10237	1			T1	1		T3	2		T4	8
valid_sources[0x7e]	5920	1			T1	13		T3	1		T4	11
valid_sources[0x7f]	4724	1			T3	3		T4	10		T11	7
valid_sources[0x80]	9334	1			T1	5		T3	1		T4	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

593637

1

T1

839

T2

16

T3

59

values[0x0]

all_enables

biggest_size

123325

1

T1

276

T2

8

T3

63

values[0x1]

all_enables

biggest_size

121705

1

T1

270

T2

6

T3

63