Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	57018670	14278	0	0
claim_transition_if_regwen_rd_A	57018670	1083	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57018670	14278	0	0
T18	130148	10	0	0
T21	6411	0	0	0
T26	391641	0	0	0
T37	30601	0	0	0
T57	342946	19	0	0
T59	3533	0	0	0
T88	0	5	0	0
T95	0	13	0	0
T111	16086	0	0	0
T138	0	10	0	0
T139	0	6	0	0
T140	0	4	0	0
T141	0	1	0	0
T142	0	16	0	0
T143	0	2	0	0
T144	6986	0	0	0
T145	1186	0	0	0
T146	17122	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57018670	1083	0	0
T19	37220	0	0	0
T40	29336	0	0	0
T49	21909	0	0	0
T81	0	6	0	0
T86	2310	0	0	0
T88	552079	1	0	0
T101	0	15	0	0
T102	0	31	0	0
T109	0	21	0	0
T110	0	9	0	0
T115	0	11	0	0
T147	0	2	0	0
T148	0	33	0	0
T149	0	9	0	0
T150	26827	0	0	0
T151	1181	0	0	0
T152	11721	0	0	0
T153	71765	0	0	0
T154	1182	0	0	0