Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	736373	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

922841

1

T1

246

T2

1365

T3

2216

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1368881	1			T1	205		T2	1774		T3	4210
values[0x0]	144698	1			T1	90		T2	283		T3	82
values[0x1]	145635	1			T1	81		T2	285		T3	84

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	581476	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1077738

1

T1

277

T2

1587

T3

2635

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6087	1			T1	4		T2	7		T3	12
valid_sources[0x01]	5132	1			T1	8		T2	17		T3	25
valid_sources[0x02]	8371	1			T2	15		T3	17		T10	1
valid_sources[0x03]	4786	1			T2	7		T3	15		T4	3
valid_sources[0x04]	7726	1			T2	12		T3	21		T4	3
valid_sources[0x05]	6409	1			T1	2		T2	3		T3	13
valid_sources[0x06]	5881	1			T1	1		T2	2		T3	18
valid_sources[0x07]	7067	1			T1	1		T2	8		T3	18
valid_sources[0x08]	4672	1			T2	2		T3	17		T4	4
valid_sources[0x09]	4528	1			T1	2		T2	11		T3	8
valid_sources[0x0a]	4695	1			T2	7		T3	17		T4	3
valid_sources[0x0b]	4789	1			T1	3		T2	3		T3	11
valid_sources[0x0c]	4957	1			T2	4		T3	24		T4	2
valid_sources[0x0d]	17383	1			T2	14		T3	22		T4	1
valid_sources[0x0e]	4740	1			T1	8		T2	8		T3	26
valid_sources[0x0f]	4538	1			T1	3		T2	5		T3	24
valid_sources[0x10]	4766	1			T1	1		T2	5		T3	13
valid_sources[0x11]	4722	1			T2	8		T3	24		T4	1
valid_sources[0x12]	6070	1			T1	3		T2	11		T3	22
valid_sources[0x13]	4974	1			T2	9		T3	7		T4	3
valid_sources[0x14]	8802	1			T2	8		T3	14		T4	1
valid_sources[0x15]	4588	1			T2	4		T3	19		T4	2
valid_sources[0x16]	4523	1			T1	7		T2	8		T3	16
valid_sources[0x17]	5875	1			T1	6		T2	4		T3	11
valid_sources[0x18]	4924	1			T2	13		T3	12		T4	5
valid_sources[0x19]	4514	1			T1	2		T2	14		T3	15
valid_sources[0x1a]	6800	1			T1	1		T2	10		T3	16
valid_sources[0x1b]	4670	1			T1	2		T2	2		T3	18
valid_sources[0x1c]	13062	1			T1	1		T2	12		T3	22
valid_sources[0x1d]	7539	1			T2	10		T3	16		T4	2
valid_sources[0x1e]	4644	1			T1	3		T2	6		T3	22
valid_sources[0x1f]	4561	1			T2	10		T3	18		T4	4
valid_sources[0x20]	4951	1			T1	3		T2	17		T3	16
valid_sources[0x21]	4645	1			T2	12		T3	18		T4	3
valid_sources[0x22]	6474	1			T2	6		T3	24		T13	16
valid_sources[0x23]	4728	1			T2	8		T3	16		T4	1
valid_sources[0x24]	4763	1			T1	1		T2	8		T3	19
valid_sources[0x25]	5082	1			T1	1		T2	7		T3	18
valid_sources[0x26]	4488	1			T1	1		T2	12		T3	20
valid_sources[0x27]	4846	1			T1	2		T2	8		T3	8
valid_sources[0x28]	4729	1			T2	8		T3	17		T10	5
valid_sources[0x29]	4859	1			T1	2		T2	9		T3	18
valid_sources[0x2a]	4788	1			T1	4		T2	5		T3	18
valid_sources[0x2b]	5047	1			T2	6		T3	16		T13	34
valid_sources[0x2c]	17209	1			T2	4		T3	16		T4	1
valid_sources[0x2d]	6474	1			T2	8		T3	14		T13	24
valid_sources[0x2e]	4461	1			T2	10		T3	17		T4	7
valid_sources[0x2f]	4718	1			T1	8		T2	9		T3	17
valid_sources[0x30]	4573	1			T2	3		T3	12		T4	5
valid_sources[0x31]	7798	1			T1	3		T2	8		T3	17
valid_sources[0x32]	4977	1			T1	2		T2	3		T3	23
valid_sources[0x33]	4949	1			T2	7		T3	20		T10	2
valid_sources[0x34]	5967	1			T2	10		T3	12		T4	1
valid_sources[0x35]	4662	1			T2	7		T3	13		T13	46
valid_sources[0x36]	4485	1			T1	2		T2	11		T3	18
valid_sources[0x37]	4779	1			T2	17		T3	16		T13	25
valid_sources[0x38]	4926	1			T1	4		T2	7		T3	21
valid_sources[0x39]	4517	1			T2	5		T3	15		T4	2
valid_sources[0x3a]	4537	1			T1	1		T2	11		T3	23
valid_sources[0x3b]	5751	1			T2	11		T3	18		T4	5
valid_sources[0x3c]	6399	1			T1	1		T2	10		T3	19
valid_sources[0x3d]	4709	1			T2	6		T3	15		T4	4
valid_sources[0x3e]	4841	1			T1	9		T2	11		T3	16
valid_sources[0x3f]	5021	1			T2	11		T3	13		T4	2
valid_sources[0x40]	4643	1			T2	6		T3	19		T4	2
valid_sources[0x41]	6230	1			T2	15		T3	16		T4	1
valid_sources[0x42]	5576	1			T2	3		T3	17		T4	2
valid_sources[0x43]	7798	1			T1	2		T2	12		T3	15
valid_sources[0x44]	5183	1			T2	6		T3	23		T10	3
valid_sources[0x45]	5031	1			T1	6		T2	16		T3	25
valid_sources[0x46]	4736	1			T2	4		T3	19		T4	2
valid_sources[0x47]	4654	1			T2	8		T3	23		T14	15
valid_sources[0x48]	5092	1			T2	5		T3	17		T13	5
valid_sources[0x49]	5040	1			T2	4		T3	25		T6	1
valid_sources[0x4a]	6986	1			T2	8		T3	27		T4	3
valid_sources[0x4b]	5960	1			T2	5		T3	24		T4	2
valid_sources[0x4c]	4694	1			T2	8		T3	19		T4	4
valid_sources[0x4d]	4658	1			T2	3		T3	15		T13	15
valid_sources[0x4e]	7678	1			T1	10		T2	6		T3	14
valid_sources[0x4f]	7829	1			T1	4		T2	12		T3	22
valid_sources[0x50]	4800	1			T2	9		T3	23		T4	3
valid_sources[0x51]	4918	1			T2	15		T3	13		T4	2
valid_sources[0x52]	5174	1			T2	6		T3	13		T4	1
valid_sources[0x53]	4898	1			T1	6		T2	5		T3	16
valid_sources[0x54]	4670	1			T1	2		T2	6		T3	15
valid_sources[0x55]	6499	1			T2	14		T3	9		T4	1
valid_sources[0x56]	4679	1			T2	7		T3	14		T4	1
valid_sources[0x57]	5509	1			T2	18		T3	11		T4	7
valid_sources[0x58]	4795	1			T1	2		T2	7		T3	16
valid_sources[0x59]	4387	1			T1	4		T2	15		T3	13
valid_sources[0x5a]	7877	1			T1	2		T2	12		T3	22
valid_sources[0x5b]	4851	1			T2	5		T3	20		T4	2
valid_sources[0x5c]	5987	1			T1	2		T2	4		T3	21
valid_sources[0x5d]	6240	1			T2	7		T3	15		T4	4
valid_sources[0x5e]	4853	1			T2	8		T3	16		T4	2
valid_sources[0x5f]	4578	1			T1	1		T2	11		T3	18
valid_sources[0x60]	4794	1			T1	5		T2	6		T3	16
valid_sources[0x61]	6027	1			T1	1		T2	15		T3	17
valid_sources[0x62]	5060	1			T2	12		T3	16		T4	4
valid_sources[0x63]	4888	1			T2	14		T3	19		T4	2
valid_sources[0x64]	16202	1			T1	2		T2	7		T3	14
valid_sources[0x65]	4458	1			T1	1		T2	14		T3	16
valid_sources[0x66]	4626	1			T1	4		T2	21		T3	19
valid_sources[0x67]	6256	1			T2	8		T3	15		T13	9
valid_sources[0x68]	4983	1			T1	4		T2	10		T3	16
valid_sources[0x69]	4876	1			T1	3		T2	16		T3	14
valid_sources[0x6a]	4751	1			T2	17		T3	14		T4	6
valid_sources[0x6b]	7776	1			T2	13		T3	20		T4	5
valid_sources[0x6c]	4744	1			T1	4		T2	11		T3	14
valid_sources[0x6d]	7771	1			T1	6		T2	5		T3	22
valid_sources[0x6e]	5964	1			T1	1		T2	5		T3	11
valid_sources[0x6f]	4614	1			T1	2		T2	19		T3	16
valid_sources[0x70]	14636	1			T1	1		T2	10		T3	12
valid_sources[0x71]	7055	1			T2	4		T3	14		T13	11
valid_sources[0x72]	4910	1			T1	1		T2	4		T3	13
valid_sources[0x73]	4491	1			T1	1		T2	10		T3	20
valid_sources[0x74]	5858	1			T1	5		T2	13		T3	15
valid_sources[0x75]	4528	1			T2	7		T3	16		T10	1
valid_sources[0x76]	7001	1			T2	13		T3	17		T4	3
valid_sources[0x77]	4601	1			T2	16		T3	14		T4	1
valid_sources[0x78]	4870	1			T2	9		T3	17		T4	1
valid_sources[0x79]	4860	1			T2	7		T3	13		T10	2
valid_sources[0x7a]	7558	1			T2	12		T3	17		T4	5
valid_sources[0x7b]	6731	1			T1	1		T2	9		T3	14
valid_sources[0x7c]	209736	1			T2	6		T3	12		T10	1
valid_sources[0x7d]	6551	1			T1	5		T2	10		T3	21
valid_sources[0x7e]	4705	1			T2	7		T3	23		T4	2
valid_sources[0x7f]	6662	1			T1	1		T2	9		T3	20
valid_sources[0x80]	4908	1			T2	2		T3	11		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

672999

1

T1

111

T2

874

T3

2074

values[0x0]

all_enables

biggest_size

125504

1

T1

73

T2

244

T3

68

values[0x1]

all_enables

biggest_size

124338

1

T1

62

T2

247

T3

74