Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	54349695	13152	0	0
claim_transition_if_regwen_rd_A	54349695	1078	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54349695	13152	0	0
T34	788408	0	0	0
T50	0	12	0	0
T52	125537	11	0	0
T82	194226	1	0	0
T86	1026	0	0	0
T89	0	4	0	0
T90	0	2	0	0
T143	0	4	0	0
T144	0	6	0	0
T145	0	10	0	0
T146	0	5	0	0
T147	0	11	0	0
T148	31796	0	0	0
T149	8788	0	0	0
T150	4337	0	0	0
T151	8294	0	0	0
T152	34148	0	0	0
T153	22563	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54349695	1078	0	0
T46	29383	0	0	0
T89	308478	12	0	0
T90	0	9	0	0
T111	0	17	0	0
T112	0	38	0	0
T116	0	30	0	0
T122	0	97	0	0
T146	0	23	0	0
T154	0	6	0	0
T155	0	10	0	0
T156	0	15	0	0
T157	43286	0	0	0
T158	25264	0	0	0
T159	1291	0	0	0
T160	25712	0	0	0
T161	210441	0	0	0
T162	36960	0	0	0
T163	1020	0	0	0
T164	36298	0	0	0