Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	967095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1153865

1

T1

553

T2

945

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1831416	1			T1	416		T2	798		T3	58
values[0x0]	144391	1			T1	182		T2	338		T3	2
values[0x1]	145153	1			T1	210		T2	294		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	766541	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1354419

1

T1

621

T2

1059

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6309	1			T5	3		T12	9		T18	1
valid_sources[0x01]	6608	1			T12	7		T18	2		T20	2
valid_sources[0x02]	6137	1			T5	2		T12	2		T18	4
valid_sources[0x03]	6525	1			T5	1		T12	4		T18	10
valid_sources[0x04]	6968	1			T5	1		T12	7		T18	4
valid_sources[0x05]	6087	1			T4	1		T10	1		T5	2
valid_sources[0x06]	6521	1			T12	4		T18	2		T20	2
valid_sources[0x07]	7872	1			T5	1		T12	1		T18	11
valid_sources[0x08]	6326	1			T5	1		T12	8		T18	3
valid_sources[0x09]	6026	1			T5	1		T12	5		T18	5
valid_sources[0x0a]	6244	1			T5	4		T12	5		T18	2
valid_sources[0x0b]	6286	1			T5	1		T12	3		T18	4
valid_sources[0x0c]	6179	1			T11	1		T12	8		T18	12
valid_sources[0x0d]	6425	1			T10	1		T18	7		T20	2
valid_sources[0x0e]	6068	1			T5	2		T12	6		T18	6
valid_sources[0x0f]	6182	1			T5	6		T12	3		T18	4
valid_sources[0x10]	7821	1			T4	2		T5	2		T12	8
valid_sources[0x11]	6336	1			T1	26		T5	1		T12	3
valid_sources[0x12]	5973	1			T10	2		T11	1		T5	1
valid_sources[0x13]	6654	1			T11	1		T12	2		T18	2
valid_sources[0x14]	6239	1			T5	2		T12	6		T18	2
valid_sources[0x15]	6347	1			T5	1		T12	4		T18	1
valid_sources[0x16]	6514	1			T5	1		T12	8		T18	4
valid_sources[0x17]	6209	1			T1	47		T3	2		T5	5
valid_sources[0x18]	5929	1			T10	1		T5	1		T12	1
valid_sources[0x19]	8445	1			T10	1		T12	5		T18	5
valid_sources[0x1a]	7762	1			T5	3		T12	4		T18	10
valid_sources[0x1b]	6799	1			T5	5		T12	4		T18	14
valid_sources[0x1c]	7256	1			T12	9		T18	6		T19	4
valid_sources[0x1d]	6179	1			T11	1		T12	2		T18	5
valid_sources[0x1e]	6443	1			T1	38		T10	1		T5	2
valid_sources[0x1f]	6196	1			T5	1		T12	2		T18	3
valid_sources[0x20]	6121	1			T1	11		T4	1		T10	1
valid_sources[0x21]	7509	1			T3	2		T12	8		T27	2
valid_sources[0x22]	7484	1			T18	2		T20	9		T22	2
valid_sources[0x23]	6384	1			T3	2		T12	14		T18	3
valid_sources[0x24]	6013	1			T10	1		T12	5		T18	1
valid_sources[0x25]	6118	1			T5	1		T18	4		T19	1
valid_sources[0x26]	6068	1			T12	18		T18	5		T19	2
valid_sources[0x27]	7609	1			T10	1		T5	1		T12	3
valid_sources[0x28]	6326	1			T3	3		T10	1		T5	1
valid_sources[0x29]	6006	1			T5	1		T12	15		T18	12
valid_sources[0x2a]	6428	1			T4	1		T5	2		T12	3
valid_sources[0x2b]	6188	1			T3	2		T5	3		T12	9
valid_sources[0x2c]	7056	1			T5	3		T12	9		T18	11
valid_sources[0x2d]	6074	1			T4	2		T5	1		T12	4
valid_sources[0x2e]	6287	1			T12	5		T18	5		T20	2
valid_sources[0x2f]	42750	1			T5	1		T12	21		T18	3
valid_sources[0x30]	7071	1			T1	3		T12	2		T18	4
valid_sources[0x31]	6210	1			T4	3		T10	1		T5	2
valid_sources[0x32]	6603	1			T4	3		T5	2		T12	5
valid_sources[0x33]	7776	1			T4	3		T5	1		T12	2
valid_sources[0x34]	6890	1			T12	5		T18	5		T19	2
valid_sources[0x35]	5855	1			T5	1		T12	6		T18	6
valid_sources[0x36]	6074	1			T12	10		T18	3		T20	7
valid_sources[0x37]	6419	1			T1	5		T3	1		T18	4
valid_sources[0x38]	10120	1			T3	1		T12	10		T18	5
valid_sources[0x39]	8264	1			T10	1		T18	3		T19	4
valid_sources[0x3a]	6208	1			T4	1		T5	3		T12	3
valid_sources[0x3b]	6366	1			T1	6		T12	1		T18	5
valid_sources[0x3c]	6119	1			T1	34		T10	1		T5	2
valid_sources[0x3d]	6263	1			T12	26		T18	5		T19	7
valid_sources[0x3e]	5819	1			T5	2		T12	15		T18	3
valid_sources[0x3f]	6105	1			T1	78		T3	1		T10	1
valid_sources[0x40]	6088	1			T1	12		T5	1		T18	5
valid_sources[0x41]	7564	1			T2	1430		T4	1		T5	3
valid_sources[0x42]	6540	1			T5	4		T12	1		T18	1
valid_sources[0x43]	6474	1			T12	2		T18	6		T20	5
valid_sources[0x44]	8436	1			T4	1		T11	1		T5	3
valid_sources[0x45]	5975	1			T5	1		T12	13		T18	2
valid_sources[0x46]	6223	1			T3	1		T5	1		T12	7
valid_sources[0x47]	13230	1			T5	5		T18	6		T19	11
valid_sources[0x48]	9197	1			T5	6		T12	9		T18	3
valid_sources[0x49]	5963	1			T4	1		T12	12		T18	3
valid_sources[0x4a]	7276	1			T3	1		T5	1		T12	4
valid_sources[0x4b]	8863	1			T18	5		T19	16		T22	3
valid_sources[0x4c]	7916	1			T5	3		T12	2		T18	14
valid_sources[0x4d]	6466	1			T11	1		T5	1		T12	4
valid_sources[0x4e]	6593	1			T3	2		T12	2		T18	6
valid_sources[0x4f]	12939	1			T5	3		T18	5		T19	7
valid_sources[0x50]	6049	1			T11	1		T5	1		T12	6
valid_sources[0x51]	7684	1			T5	1		T12	14		T18	5
valid_sources[0x52]	7234	1			T1	13		T5	2		T12	6
valid_sources[0x53]	5842	1			T5	4		T12	7		T18	4
valid_sources[0x54]	8814	1			T10	1		T5	4		T18	6
valid_sources[0x55]	5910	1			T1	7		T5	1		T12	2
valid_sources[0x56]	6388	1			T10	1		T5	7		T12	8
valid_sources[0x57]	6268	1			T12	2		T27	1		T18	11
valid_sources[0x58]	17063	1			T4	1		T11	2		T12	5
valid_sources[0x59]	9915	1			T4	1		T12	5		T18	7
valid_sources[0x5a]	6031	1			T11	1		T12	11		T18	1
valid_sources[0x5b]	6137	1			T5	1		T12	1		T18	6
valid_sources[0x5c]	6055	1			T5	2		T12	4		T27	1
valid_sources[0x5d]	6174	1			T3	7		T12	4		T18	8
valid_sources[0x5e]	6525	1			T11	1		T5	1		T18	4
valid_sources[0x5f]	6268	1			T12	4		T18	8		T20	10
valid_sources[0x60]	7383	1			T1	25		T4	2		T12	5
valid_sources[0x61]	6052	1			T3	1		T5	3		T12	8
valid_sources[0x62]	6266	1			T3	1		T5	2		T18	8
valid_sources[0x63]	6324	1			T5	1		T12	5		T18	2
valid_sources[0x64]	6242	1			T4	1		T5	1		T12	4
valid_sources[0x65]	6631	1			T4	1		T10	1		T5	2
valid_sources[0x66]	5920	1			T5	1		T12	4		T18	5
valid_sources[0x67]	6122	1			T5	1		T12	2		T18	4
valid_sources[0x68]	7978	1			T5	2		T18	6		T20	12
valid_sources[0x69]	13734	1			T11	2		T5	1		T12	4
valid_sources[0x6a]	6974	1			T5	3		T12	4		T18	3
valid_sources[0x6b]	7207	1			T5	1		T12	18		T18	10
valid_sources[0x6c]	8954	1			T12	12		T18	10		T19	1
valid_sources[0x6d]	6393	1			T4	2		T5	5		T12	6
valid_sources[0x6e]	7218	1			T1	67		T11	1		T18	3
valid_sources[0x6f]	6205	1			T3	1		T5	3		T12	4
valid_sources[0x70]	6380	1			T5	4		T12	1		T18	2
valid_sources[0x71]	70505	1			T1	14		T4	1		T12	1
valid_sources[0x72]	5942	1			T4	3		T10	1		T5	1
valid_sources[0x73]	6081	1			T1	17		T5	1		T18	1
valid_sources[0x74]	7603	1			T3	1		T4	3		T12	6
valid_sources[0x75]	5893	1			T5	1		T12	2		T18	8
valid_sources[0x76]	6307	1			T4	1		T5	3		T12	20
valid_sources[0x77]	6439	1			T18	2		T19	13		T20	21
valid_sources[0x78]	6216	1			T10	1		T11	1		T5	2
valid_sources[0x79]	6075	1			T5	1		T12	10		T27	4
valid_sources[0x7a]	6317	1			T3	2		T12	9		T18	4
valid_sources[0x7b]	6106	1			T1	4		T5	1		T12	1
valid_sources[0x7c]	7826	1			T1	8		T10	1		T12	13
valid_sources[0x7d]	6247	1			T12	2		T18	2		T20	6
valid_sources[0x7e]	7991	1			T10	1		T5	1		T12	1
valid_sources[0x7f]	8357	1			T12	3		T18	7		T19	15
valid_sources[0x80]	6220	1			T1	7		T10	1		T5	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

904335

1

T1

216

T2

401

T4

19

values[0x0]

all_enables

biggest_size

125142

1

T1

160

T2

295

T3

2

values[0x1]

all_enables

biggest_size

124388

1

T1

177

T2

249

T3

3