Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	62028192	12300	0	0
claim_transition_if_regwen_rd_A	62028192	1377	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62028192	12300	0	0
T7	346916	6	0	0
T8	87383	0	0	0
T9	50710	0	0	0
T14	25924	0	0	0
T15	144481	0	0	0
T16	10962	0	0	0
T17	0	3	0	0
T21	18070	0	0	0
T35	20604	0	0	0
T36	1550	0	0	0
T54	1930	0	0	0
T80	0	3	0	0
T81	0	3	0	0
T91	0	9	0	0
T130	0	1	0	0
T132	0	2	0	0
T133	0	2	0	0
T134	0	9	0	0
T135	0	6	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62028192	1377	0	0
T17	480371	5	0	0
T32	94269	0	0	0
T87	28794	0	0	0
T88	1112	0	0	0
T89	29935	0	0	0
T90	28410	0	0	0
T93	941448	0	0	0
T100	0	81	0	0
T104	0	20	0	0
T132	0	16	0	0
T136	0	4	0	0
T137	0	6	0	0
T138	0	48	0	0
T139	0	26	0	0
T140	0	61	0	0
T141	0	6	0	0
T142	6301	0	0	0
T143	32814	0	0	0
T144	35501	0	0	0