Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	882096	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1071702

1

T1

2169

T2

964

T3

666

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1660402	1			T1	4107		T2	769		T3	497
values[0x0]	146092	1			T1	71		T2	349		T3	242
values[0x1]	147304	1			T1	65		T2	331		T3	230

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	699188	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1254610

1

T1

2598

T2

1079

T3

718

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	73751	1			T1	15		T2	13		T3	2
valid_sources[0x01]	5853	1			T1	9		T2	5		T3	1
valid_sources[0x02]	7869	1			T1	27		T2	2		T3	4
valid_sources[0x03]	6532	1			T1	10		T2	14		T3	4
valid_sources[0x04]	9224	1			T1	16		T2	4		T3	5
valid_sources[0x05]	5964	1			T1	24		T2	7		T3	3
valid_sources[0x06]	5968	1			T1	15		T2	3		T3	5
valid_sources[0x07]	5824	1			T1	15		T2	6		T3	7
valid_sources[0x08]	6251	1			T1	23		T2	4		T3	2
valid_sources[0x09]	6079	1			T1	10		T2	5		T3	1
valid_sources[0x0a]	7326	1			T1	15		T2	6		T3	3
valid_sources[0x0b]	6062	1			T1	10		T2	3		T3	2
valid_sources[0x0c]	12042	1			T1	20		T2	5		T3	7
valid_sources[0x0d]	5896	1			T1	17		T2	8		T3	2
valid_sources[0x0e]	6180	1			T1	28		T2	1		T3	4
valid_sources[0x0f]	5979	1			T1	15		T2	10		T6	2
valid_sources[0x10]	5640	1			T1	23		T2	8		T3	4
valid_sources[0x11]	6018	1			T1	29		T2	6		T3	7
valid_sources[0x12]	5878	1			T1	14		T2	1		T3	6
valid_sources[0x13]	18387	1			T1	20		T2	1		T3	12
valid_sources[0x14]	7003	1			T1	5		T2	10		T3	10
valid_sources[0x15]	6095	1			T1	25		T2	9		T3	9
valid_sources[0x16]	5916	1			T1	33		T19	2		T17	5
valid_sources[0x17]	6123	1			T1	5		T2	5		T3	2
valid_sources[0x18]	7047	1			T1	6		T2	9		T3	1
valid_sources[0x19]	6757	1			T1	18		T2	10		T3	1
valid_sources[0x1a]	5818	1			T1	25		T2	10		T3	3
valid_sources[0x1b]	5996	1			T1	9		T2	2		T3	5
valid_sources[0x1c]	7310	1			T1	5		T2	3		T3	2
valid_sources[0x1d]	9549	1			T1	16		T2	3		T3	7
valid_sources[0x1e]	5821	1			T1	41		T2	4		T3	6
valid_sources[0x1f]	5608	1			T1	1		T2	12		T3	7
valid_sources[0x20]	9143	1			T1	14		T2	1		T3	2
valid_sources[0x21]	7521	1			T1	18		T2	7		T3	5
valid_sources[0x22]	5531	1			T1	13		T2	10		T3	4
valid_sources[0x23]	5759	1			T1	13		T2	8		T3	3
valid_sources[0x24]	7131	1			T1	10		T2	1		T3	4
valid_sources[0x25]	5763	1			T1	22		T2	3		T3	4
valid_sources[0x26]	6024	1			T1	13		T2	8		T3	4
valid_sources[0x27]	5722	1			T1	22		T2	14		T3	6
valid_sources[0x28]	5889	1			T1	9		T2	6		T19	1
valid_sources[0x29]	5753	1			T1	5		T2	2		T3	5
valid_sources[0x2a]	13180	1			T1	6		T2	4		T3	2
valid_sources[0x2b]	8665	1			T1	4		T2	2		T3	1
valid_sources[0x2c]	11008	1			T1	15		T2	3		T3	1
valid_sources[0x2d]	6101	1			T1	30		T2	2		T17	3
valid_sources[0x2e]	5954	1			T1	27		T2	5		T3	3
valid_sources[0x2f]	6150	1			T1	21		T2	5		T3	1
valid_sources[0x30]	8025	1			T1	19		T2	3		T3	1
valid_sources[0x31]	7019	1			T1	18		T2	10		T3	5
valid_sources[0x32]	11327	1			T1	11		T2	12		T3	4
valid_sources[0x33]	6145	1			T1	14		T2	5		T3	8
valid_sources[0x34]	6477	1			T1	16		T2	15		T3	4
valid_sources[0x35]	6380	1			T1	12		T2	4		T3	6
valid_sources[0x36]	5631	1			T1	10		T2	4		T3	1
valid_sources[0x37]	5886	1			T1	12		T2	6		T3	2
valid_sources[0x38]	6898	1			T1	14		T2	1		T3	3
valid_sources[0x39]	5929	1			T1	8		T2	9		T3	4
valid_sources[0x3a]	6315	1			T1	3		T2	2		T3	5
valid_sources[0x3b]	5899	1			T1	24		T2	2		T3	3
valid_sources[0x3c]	5554	1			T1	7		T2	10		T3	5
valid_sources[0x3d]	7652	1			T1	14		T2	2		T3	4
valid_sources[0x3e]	5649	1			T1	15		T2	4		T3	1
valid_sources[0x3f]	5665	1			T1	9		T2	4		T3	7
valid_sources[0x40]	5943	1			T1	35		T2	9		T3	7
valid_sources[0x41]	6070	1			T1	35		T2	6		T3	6
valid_sources[0x42]	6185	1			T1	20		T2	6		T3	4
valid_sources[0x43]	5405	1			T1	18		T2	7		T3	7
valid_sources[0x44]	5935	1			T1	16		T2	8		T3	2
valid_sources[0x45]	7962	1			T1	14		T2	2		T3	1
valid_sources[0x46]	6211	1			T1	17		T2	2		T3	6
valid_sources[0x47]	7424	1			T1	3		T2	4		T3	2
valid_sources[0x48]	7038	1			T1	4		T2	4		T3	4
valid_sources[0x49]	6304	1			T1	18		T2	8		T3	2
valid_sources[0x4a]	5527	1			T1	12		T2	7		T3	5
valid_sources[0x4b]	6610	1			T1	5		T2	10		T3	2
valid_sources[0x4c]	5873	1			T1	16		T2	1		T3	3
valid_sources[0x4d]	5761	1			T1	30		T2	9		T3	3
valid_sources[0x4e]	7452	1			T1	5		T2	7		T3	7
valid_sources[0x4f]	6207	1			T1	25		T2	2		T3	3
valid_sources[0x50]	7381	1			T1	14		T2	3		T3	4
valid_sources[0x51]	9063	1			T1	12		T2	5		T3	4
valid_sources[0x52]	5899	1			T1	22		T2	3		T13	2
valid_sources[0x53]	7969	1			T1	37		T2	18		T3	6
valid_sources[0x54]	10585	1			T1	26		T2	3		T6	2
valid_sources[0x55]	5783	1			T1	16		T2	8		T3	2
valid_sources[0x56]	9966	1			T1	18		T2	3		T3	2
valid_sources[0x57]	5657	1			T1	26		T2	2		T3	7
valid_sources[0x58]	5987	1			T1	14		T2	4		T13	1
valid_sources[0x59]	12676	1			T1	13		T2	9		T3	3
valid_sources[0x5a]	6928	1			T1	22		T2	8		T3	2
valid_sources[0x5b]	6267	1			T1	25		T2	3		T3	8
valid_sources[0x5c]	5910	1			T1	24		T2	4		T3	9
valid_sources[0x5d]	7406	1			T1	15		T2	3		T3	2
valid_sources[0x5e]	6849	1			T1	9		T2	3		T3	6
valid_sources[0x5f]	5900	1			T1	22		T2	3		T19	1
valid_sources[0x60]	79254	1			T1	26		T2	8		T3	1
valid_sources[0x61]	6220	1			T1	22		T2	5		T3	9
valid_sources[0x62]	6190	1			T1	14		T2	7		T3	4
valid_sources[0x63]	6055	1			T1	20		T2	13		T3	6
valid_sources[0x64]	5835	1			T1	18		T2	3		T3	6
valid_sources[0x65]	6104	1			T1	6		T2	1		T3	3
valid_sources[0x66]	5725	1			T1	21		T2	6		T3	3
valid_sources[0x67]	5427	1			T1	10		T2	7		T3	1
valid_sources[0x68]	5653	1			T1	11		T2	1		T3	3
valid_sources[0x69]	5888	1			T1	27		T2	7		T3	12
valid_sources[0x6a]	6084	1			T1	6		T2	3		T3	3
valid_sources[0x6b]	6449	1			T1	6		T2	11		T3	8
valid_sources[0x6c]	7141	1			T1	10		T2	5		T3	4
valid_sources[0x6d]	6931	1			T1	10		T2	5		T3	11
valid_sources[0x6e]	6960	1			T1	36		T2	4		T3	1
valid_sources[0x6f]	8075	1			T1	22		T2	6		T3	2
valid_sources[0x70]	5733	1			T1	29		T2	5		T3	4
valid_sources[0x71]	6043	1			T1	20		T2	8		T3	5
valid_sources[0x72]	5819	1			T1	8		T2	15		T3	1
valid_sources[0x73]	7162	1			T1	7		T2	4		T3	7
valid_sources[0x74]	6007	1			T1	15		T3	3		T13	1
valid_sources[0x75]	5801	1			T1	18		T2	2		T3	3
valid_sources[0x76]	6628	1			T1	8		T2	4		T3	1
valid_sources[0x77]	6947	1			T1	22		T2	10		T17	5
valid_sources[0x78]	6135	1			T1	13		T2	6		T3	5
valid_sources[0x79]	6182	1			T1	8		T2	3		T3	10
valid_sources[0x7a]	5566	1			T1	36		T2	8		T3	3
valid_sources[0x7b]	5828	1			T1	14		T2	4		T3	3
valid_sources[0x7c]	5900	1			T1	12		T2	7		T3	3
valid_sources[0x7d]	6803	1			T1	15		T2	5		T3	11
valid_sources[0x7e]	6216	1			T1	14		T2	6		T3	1
valid_sources[0x7f]	5711	1			T1	19		T2	6		T13	1
valid_sources[0x80]	5813	1			T1	14		T2	6		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

819207

1

T1

2055

T2

362

T3

251

values[0x0]

all_enables

biggest_size

126601

1

T1

63

T2

312

T3

209

values[0x1]

all_enables

biggest_size

125894

1

T1

51

T2

290

T3

206