Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	59239481	16034	0	0
claim_transition_if_regwen_rd_A	59239481	1319	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59239481	16034	0	0
T9	50080	0	0	0
T44	51006	0	0	0
T55	203033	2	0	0
T66	934	0	0	0
T75	184648	2	0	0
T76	34740	0	0	0
T81	0	1	0	0
T82	0	5	0	0
T83	0	8	0	0
T94	0	11	0	0
T130	0	21	0	0
T131	0	5	0	0
T132	0	2	0	0
T133	0	2	0	0
T134	29810	0	0	0
T135	30713	0	0	0
T136	37037	0	0	0
T137	31661	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59239481	1319	0	0
T9	50080	0	0	0
T44	51006	0	0	0
T66	934	0	0	0
T75	184648	3	0	0
T76	34740	0	0	0
T81	0	2	0	0
T92	0	42	0	0
T97	0	81	0	0
T102	0	21	0	0
T128	0	3	0	0
T134	29810	0	0	0
T135	30713	0	0	0
T136	37037	0	0	0
T137	31661	0	0	0
T138	0	2	0	0
T139	0	17	0	0
T140	0	13	0	0
T141	0	4	0	0
T142	7143	0	0	0