Unified Coverage Report :: Module :: lc_ctrl_signal_decode

Module : lc_ctrl_signal_decode

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_signal_decode

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.67	98.17	91.67		100.00	98.53	100.00	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_flop_keymgr_div	100.00	100.00				100.00
u_prim_lc_sender_cpu_en	100.00	100.00				100.00
u_prim_lc_sender_creator_seed_sw_rw_en	100.00	100.00				100.00
u_prim_lc_sender_dft_en	100.00	100.00				100.00
u_prim_lc_sender_escalate_en	100.00	100.00				100.00
u_prim_lc_sender_hw_debug_en	100.00	100.00				100.00
u_prim_lc_sender_iso_part_sw_rd_en	100.00	100.00				100.00
u_prim_lc_sender_iso_part_sw_wr_en	100.00	100.00				100.00
u_prim_lc_sender_keymgr_en	100.00	100.00				100.00
u_prim_lc_sender_nvm_debug_en	100.00	100.00				100.00
u_prim_lc_sender_owner_seed_sw_rw_en	100.00	100.00				100.00
u_prim_lc_sender_raw_test_rma	100.00	100.00				100.00
u_prim_lc_sender_seed_hw_rd_en	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : lc_ctrl_signal_decode

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
ALWAYS	60	62	62	100.00
CONT_ASSIGN	296	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
72	1	1
74	1	1
76	1	1
79	1	1
92	1	1
93	1	1
104	1	1
116	1	1
117	1	1
118	1	1
119	1	1
120	1	1
121	1	1
122	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
145	1	1
149	1	1
152	1	1
159	1	1
160	1	1
161	1	1
162	1	1
163	1	1
164	1	1
168	1	1
171	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
187	1	1
197	1	1
204	1	1
211	1	1
296	1	1

---

Branch Coverage for Module : lc_ctrl_signal_decode

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	76	12	12	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_signal_decode.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	case (fsm_state_i)
-2-:	92	if (lc_state_valid_i)
-3-:	93	case (lc_state_i)

Branches:

-1-	-2-	-3-	Status	Tests
ResetSt	-	-	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	CASEITEM-1: LcStRaw LcStTestLocked0 LcStTestLocked1 LcStTestLocked2 LcStTestLocked3 LcStTestLocked4 LcStTestLocked5 LcStTestLocked6	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	CASEITEM-2: LcStTestUnlocked0 LcStTestUnlocked1 LcStTestUnlocked2 LcStTestUnlocked3 LcStTestUnlocked4 LcStTestUnlocked5 LcStTestUnlocked6	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStTestUnlocked7	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStProd LcStProdEnd	Covered	T2,T3,T10
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStDev	Covered	T2,T3,T10
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	LcStRma	Covered	T1,T2,T3
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	1	default	Covered	T1,T10,T4
CASEITEM-2: IdleSt ClkMuxSt CntIncrSt CntProgSt TransCheckSt FlashRmaSt TokenHashSt TokenCheck0St TokenCheck1St TransProgSt	0	-	Covered	T188
PostTransSt	-	-	Covered	T1,T2,T3
ScrapSt EscalateSt InvalidSt	-	-	Covered	T1,T3,T10
default	-	-	Covered	T10,T16,T35

---

Assert Coverage for Module : lc_ctrl_signal_decode

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmInScrap_A	57073174	11455411	0	0
LcKeymgrDivUnique0_A	817	817	0	0
LcKeymgrDivUnique1_A	817	817	0	0
LcKeymgrDivUnique2_A	817	817	0	0
LcKeymgrDivUnique3_A	817	817	0	0
SignalsAreOffWhenNotEnabled_A	57073174	1225062	0	0
StateInScrap_A	57073174	4214	0	0

FsmInScrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57073174	11455411	0	0
T1	31010	50	0	0
T2	36274	0	0	0
T3	25383	1554	0	0
T4	50164	13011	0	0
T5	26458	0	0	0
T6	37798	0	0	0
T10	25245	12687	0	0
T11	1629	0	0	0
T12	996	0	0	0
T13	1538	14	0	0
T14	0	1609	0	0
T16	0	242992	0	0
T18	0	3996	0	0
T20	0	5946	0	0
T35	0	3541	0	0

LcKeymgrDivUnique0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	817	817	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

LcKeymgrDivUnique1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	817	817	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

LcKeymgrDivUnique2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	817	817	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

LcKeymgrDivUnique3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	817	817	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

SignalsAreOffWhenNotEnabled_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57073174	1225062	0	0
T1	31010	10	0	0
T2	36274	86	0	0
T3	25383	60	0	0
T4	50164	2783	0	0
T5	26458	5	0	0
T6	37798	1	0	0
T10	25245	322	0	0
T11	1629	1	0	0
T12	996	1	0	0
T13	1538	6	0	0

StateInScrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57073174	4214	0	0
T1	31010	2	0	0
T2	36274	0	0	0
T3	25383	0	0	0
T4	50164	1	0	0
T5	26458	0	0	0
T6	37798	0	0	0
T10	25245	36	0	0
T11	1629	0	0	0
T12	996	0	0	0
T13	1538	1	0	0
T16	0	63	0	0
T27	0	2	0	0
T35	0	13	0	0
T58	0	1	0	0
T74	0	1	0	0
T77	0	20	0	0