Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	686061	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

871154

1

T1

23

T2

676

T3

220

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1272984	1			T1	74		T2	344		T3	206
values[0x0]	142089	1			T2	303		T3	65		T11	30
values[0x1]	142142	1			T2	289		T3	71		T11	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	541900	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1015315

1

T1

40

T2

747

T3

258

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4476	1			T2	1		T3	2		T15	5
valid_sources[0x01]	4870	1			T1	2		T3	4		T15	6
valid_sources[0x02]	6988	1			T2	5		T15	4		T16	1
valid_sources[0x03]	8702	1			T1	1		T2	5		T15	10
valid_sources[0x04]	4372	1			T2	3		T15	4		T16	12
valid_sources[0x05]	4174	1			T1	2		T2	3		T15	6
valid_sources[0x06]	4133	1			T2	1		T3	1		T15	5
valid_sources[0x07]	6281	1			T2	6		T15	9		T16	26
valid_sources[0x08]	4486	1			T2	5		T3	6		T15	5
valid_sources[0x09]	5890	1			T2	2		T13	17		T15	13
valid_sources[0x0a]	4083	1			T2	2		T15	7		T16	32
valid_sources[0x0b]	5199	1			T15	8		T16	15		T21	8
valid_sources[0x0c]	6080	1			T2	1		T16	49		T21	5
valid_sources[0x0d]	4734	1			T12	6		T15	5		T16	17
valid_sources[0x0e]	3974	1			T2	1		T15	3		T21	6
valid_sources[0x0f]	5382	1			T2	1		T3	6		T15	6
valid_sources[0x10]	4164	1			T3	5		T15	5		T16	38
valid_sources[0x11]	4445	1			T2	8		T15	8		T16	25
valid_sources[0x12]	4144	1			T2	9		T3	7		T15	4
valid_sources[0x13]	4301	1			T2	8		T15	6		T21	6
valid_sources[0x14]	18106	1			T1	1		T12	6		T15	1
valid_sources[0x15]	4486	1			T2	4		T3	4		T15	13
valid_sources[0x16]	4346	1			T2	3		T3	7		T12	2
valid_sources[0x17]	5002	1			T2	1		T3	6		T12	4
valid_sources[0x18]	6655	1			T2	3		T3	3		T15	7
valid_sources[0x19]	4334	1			T2	1		T3	5		T15	6
valid_sources[0x1a]	6086	1			T1	1		T2	9		T15	3
valid_sources[0x1b]	5890	1			T3	1		T12	2		T15	3
valid_sources[0x1c]	4211	1			T2	1		T3	2		T15	8
valid_sources[0x1d]	4332	1			T2	4		T15	5		T16	4
valid_sources[0x1e]	4315	1			T1	2		T2	3		T3	1
valid_sources[0x1f]	5686	1			T2	1		T15	5		T16	18
valid_sources[0x20]	10481	1			T1	1		T2	8		T11	1553
valid_sources[0x21]	4359	1			T2	9		T15	5		T16	10
valid_sources[0x22]	5054	1			T2	5		T15	5		T16	6
valid_sources[0x23]	4383	1			T2	4		T15	4		T16	7
valid_sources[0x24]	4486	1			T2	1		T3	2		T15	5
valid_sources[0x25]	4440	1			T2	9		T12	2		T15	6
valid_sources[0x26]	7930	1			T2	8		T3	3		T15	10
valid_sources[0x27]	4082	1			T2	4		T3	2		T15	6
valid_sources[0x28]	13079	1			T2	12		T3	1		T15	6
valid_sources[0x29]	4333	1			T2	2		T3	3		T15	5
valid_sources[0x2a]	6304	1			T2	9		T15	4		T16	37
valid_sources[0x2b]	4276	1			T2	4		T3	2		T12	3
valid_sources[0x2c]	4616	1			T2	4		T15	3		T16	19
valid_sources[0x2d]	19418	1			T1	1		T2	6		T15	7
valid_sources[0x2e]	6478	1			T2	1		T3	3		T15	2
valid_sources[0x2f]	6618	1			T2	3		T15	5		T16	57
valid_sources[0x30]	4149	1			T2	5		T3	2		T15	4
valid_sources[0x31]	5724	1			T1	1		T2	1		T15	5
valid_sources[0x32]	4497	1			T2	2		T3	2		T15	5
valid_sources[0x33]	8951	1			T2	1		T3	1		T15	7
valid_sources[0x34]	6136	1			T1	1		T2	9		T3	2
valid_sources[0x35]	4400	1			T3	2		T15	12		T16	29
valid_sources[0x36]	7233	1			T15	2		T16	1		T21	4
valid_sources[0x37]	4208	1			T2	1		T15	11		T21	8
valid_sources[0x38]	4546	1			T2	1		T15	6		T16	7
valid_sources[0x39]	4136	1			T2	5		T3	2		T15	6
valid_sources[0x3a]	4453	1			T2	9		T15	7		T16	18
valid_sources[0x3b]	5395	1			T2	1		T3	14		T15	4
valid_sources[0x3c]	10363	1			T2	5		T15	2		T16	18
valid_sources[0x3d]	4150	1			T1	1		T2	1		T15	4
valid_sources[0x3e]	5337	1			T2	2		T3	1		T15	9
valid_sources[0x3f]	4178	1			T1	2		T15	8		T16	42
valid_sources[0x40]	4541	1			T1	2		T2	5		T3	2
valid_sources[0x41]	4084	1			T2	5		T13	17		T15	8
valid_sources[0x42]	4845	1			T2	1		T15	5		T16	25
valid_sources[0x43]	4331	1			T2	6		T15	10		T16	12
valid_sources[0x44]	4033	1			T2	3		T15	9		T16	10
valid_sources[0x45]	4030	1			T2	10		T3	2		T15	11
valid_sources[0x46]	4773	1			T2	2		T15	7		T16	10
valid_sources[0x47]	12717	1			T2	5		T3	1		T15	3
valid_sources[0x48]	8584	1			T2	7		T3	3		T15	5
valid_sources[0x49]	4717	1			T1	1		T2	7		T3	2
valid_sources[0x4a]	5304	1			T2	4		T3	5		T15	3
valid_sources[0x4b]	4569	1			T2	6		T3	3		T15	3
valid_sources[0x4c]	4425	1			T1	1		T15	8		T16	8
valid_sources[0x4d]	4272	1			T2	3		T15	8		T16	5
valid_sources[0x4e]	4760	1			T2	3		T3	1		T13	17
valid_sources[0x4f]	4383	1			T2	2		T15	7		T16	19
valid_sources[0x50]	4155	1			T2	6		T15	3		T16	30
valid_sources[0x51]	5547	1			T1	2		T2	7		T15	7
valid_sources[0x52]	4391	1			T1	1		T2	4		T15	4
valid_sources[0x53]	7731	1			T2	2		T3	1		T15	4
valid_sources[0x54]	4529	1			T1	1		T12	3		T15	4
valid_sources[0x55]	4566	1			T1	1		T2	2		T3	4
valid_sources[0x56]	4152	1			T2	8		T3	2		T15	9
valid_sources[0x57]	4186	1			T2	14		T3	1		T15	3
valid_sources[0x58]	4404	1			T2	3		T15	6		T16	21
valid_sources[0x59]	4512	1			T1	1		T2	9		T3	4
valid_sources[0x5a]	5313	1			T2	3		T15	5		T16	38
valid_sources[0x5b]	4360	1			T1	1		T2	1		T15	3
valid_sources[0x5c]	4187	1			T1	2		T2	2		T3	1
valid_sources[0x5d]	5253	1			T2	3		T15	5		T16	27
valid_sources[0x5e]	4560	1			T2	2		T15	3		T16	3
valid_sources[0x5f]	4442	1			T2	1		T3	3		T15	1
valid_sources[0x60]	4380	1			T3	3		T15	7		T16	11
valid_sources[0x61]	5202	1			T2	2		T12	1		T15	5
valid_sources[0x62]	186218	1			T2	10		T15	5		T16	3
valid_sources[0x63]	4197	1			T1	2		T2	11		T15	1
valid_sources[0x64]	5526	1			T3	3		T15	4		T16	19
valid_sources[0x65]	5898	1			T15	13		T21	4		T23	5
valid_sources[0x66]	4538	1			T2	2		T15	7		T16	11
valid_sources[0x67]	4309	1			T2	3		T13	17		T15	3
valid_sources[0x68]	5181	1			T2	4		T3	1		T15	4
valid_sources[0x69]	4208	1			T15	2		T16	21		T21	6
valid_sources[0x6a]	7384	1			T2	2		T15	4		T21	10
valid_sources[0x6b]	5530	1			T2	2		T15	5		T16	17
valid_sources[0x6c]	4306	1			T2	6		T3	6		T15	8
valid_sources[0x6d]	4497	1			T2	1		T15	5		T16	11
valid_sources[0x6e]	4588	1			T2	3		T15	2		T16	15
valid_sources[0x6f]	4266	1			T1	1		T2	5		T15	5
valid_sources[0x70]	5340	1			T15	8		T21	12		T23	14
valid_sources[0x71]	4694	1			T1	1		T2	1		T3	3
valid_sources[0x72]	4450	1			T2	11		T12	3		T15	4
valid_sources[0x73]	4699	1			T3	2		T12	1		T15	8
valid_sources[0x74]	5469	1			T1	1		T2	4		T15	8
valid_sources[0x75]	4366	1			T1	4		T2	3		T3	2
valid_sources[0x76]	4648	1			T2	3		T15	9		T16	44
valid_sources[0x77]	4849	1			T2	8		T15	6		T16	22
valid_sources[0x78]	4509	1			T1	1		T2	1		T3	3
valid_sources[0x79]	5117	1			T1	1		T2	3		T3	1
valid_sources[0x7a]	4874	1			T2	1		T15	10		T16	5
valid_sources[0x7b]	4534	1			T2	8		T15	5		T16	34
valid_sources[0x7c]	4213	1			T2	1		T3	1		T15	4
valid_sources[0x7d]	4802	1			T2	4		T15	3		T16	23
valid_sources[0x7e]	5260	1			T15	3		T21	3		T19	2
valid_sources[0x7f]	4595	1			T2	3		T15	9		T16	61
valid_sources[0x80]	4314	1			T1	1		T2	7		T15	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

626604

1

T1

23

T2

153

T3

101

values[0x0]

all_enables

biggest_size

123091

1

T2

273

T3

56

T11

28

values[0x1]

all_enables

biggest_size

121459

1

T2

250

T3

63

T11

21