Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	59650397	13736	0	0
claim_transition_if_regwen_rd_A	59650397	1525	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59650397	13736	0	0
T8	6499	0	0	0
T9	90992	0	0	0
T30	178570	10	0	0
T43	6736	0	0	0
T44	28342	0	0	0
T48	208237	0	0	0
T52	23810	0	0	0
T85	1535	0	0	0
T86	0	1	0	0
T87	0	3	0	0
T94	0	9	0	0
T127	7393	0	0	0
T130	0	4	0	0
T131	0	12	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	2	0	0
T135	0	2	0	0
T136	873	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59650397	1525	0	0
T54	22620	0	0	0
T86	178777	1	0	0
T87	317097	0	0	0
T92	0	45	0	0
T93	0	78	0	0
T96	0	2	0	0
T99	0	12	0	0
T101	0	53	0	0
T107	0	222	0	0
T132	0	5	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	10080	0	0	0
T140	43374	0	0	0
T141	34548	0	0	0
T142	1792	0	0	0
T143	11344	0	0	0
T144	8614	0	0	0
T145	623858	0	0	0