Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	97.92	95.75	93.40	100.00	98.52	98.76	96.11

Total test records in report: 1002

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4143604788			Aug 17 06:28:40 PM PDT 24	Aug 17 06:28:41 PM PDT 24	41573489 ps
T1002	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4217967633			Aug 17 06:28:50 PM PDT 24	Aug 17 06:28:51 PM PDT 24	25443583 ps

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_mux.3400287907
Short name	T2
Test name
Test status
Simulation time	3645820251 ps
CPU time	10.57 seconds
Started	Aug 17 06:32:08 PM PDT 24
Finished	Aug 17 06:32:18 PM PDT 24
Peak memory	226052 kb
Host	smart-bd656bae-dd58-4e16-9619-d29dbc57a583
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400287907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3 400287907
Directory	/workspace/6.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3172225426
Short name	T4
Test name
Test status
Simulation time	1525485902 ps
CPU time	11.92 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:35 PM PDT 24
Peak memory	250856 kb
Host	smart-7fe50b50-9992-47df-8211-3a9a5343aee7
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172225426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _jtag_state_post_trans.3172225426
Directory	/workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/15.lc_ctrl_security_escalation.769472757
Short name	T24
Test name
Test status
Simulation time	1021129944 ps
CPU time	9.44 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:29 PM PDT 24
Peak memory	218344 kb
Host	smart-9fa0f241-39ab-4179-8fde-12dc0c4b1dd9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=769472757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.769472757
Directory	/workspace/15.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_mubi.3078716059
Short name	T19
Test name
Test status
Simulation time	346069735 ps
CPU time	15.13 seconds
Started	Aug 17 06:32:14 PM PDT 24
Finished	Aug 17 06:32:34 PM PDT 24
Peak memory	226004 kb
Host	smart-000d67e4-2b9c-4093-a6c2-89aac62cec0c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078716059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3078716059
Directory	/workspace/6.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/38.lc_ctrl_stress_all.2437710537
Short name	T58
Test name
Test status
Simulation time	12512392877 ps
CPU time	108.52 seconds
Started	Aug 17 06:33:14 PM PDT 24
Finished	Aug 17 06:35:03 PM PDT 24
Peak memory	283472 kb
Host	smart-04ab3edb-44fd-4775-a519-822565df1d93
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437710537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all.2437710537
Directory	/workspace/38.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.3361917617
Short name	T30
Test name
Test status
Simulation time	7142842604 ps
CPU time	59.17 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:33:18 PM PDT 24
Peak memory	226172 kb
Host	smart-19df89d3-1129-4625-9e73-0179abc37290
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3361917617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.3361917617
Directory	/workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.lc_ctrl_security_escalation.2188680404
Short name	T196
Test name
Test status
Simulation time	453755763 ps
CPU time	14.2 seconds
Started	Aug 17 06:31:48 PM PDT 24
Finished	Aug 17 06:32:02 PM PDT 24
Peak memory	226064 kb
Host	smart-fad6adf2-9241-4b8c-877c-3c15c0e39fb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188680404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2188680404
Directory	/workspace/0.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_cm.2442496341
Short name	T54
Test name
Test status
Simulation time	461656922 ps
CPU time	37.73 seconds
Started	Aug 17 06:31:43 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	283332 kb
Host	smart-b930e9a6-f4a5-4d21-9d28-d17e103202e9
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442496341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2442496341
Directory	/workspace/0.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2629721503
Short name	T93
Test name
Test status
Simulation time	1373950888 ps
CPU time	4.13 seconds
Started	Aug 17 06:29:11 PM PDT 24
Finished	Aug 17 06:29:15 PM PDT 24
Peak memory	218124 kb
Host	smart-ee366c35-b184-4c89-a0cd-a4c0438a0a9c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629721503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg _err.2629721503
Directory	/workspace/16.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1851060447
Short name	T131
Test name
Test status
Simulation time	1325738953 ps
CPU time	50.7 seconds
Started	Aug 17 06:33:07 PM PDT 24
Finished	Aug 17 06:33:58 PM PDT 24
Peak memory	251092 kb
Host	smart-d4bdcd39-5816-4b01-b3b7-98562c288900
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1851060447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.1851060447
Directory	/workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.lc_ctrl_jtag_access.3629819209
Short name	T7
Test name
Test status
Simulation time	334105120 ps
CPU time	9.04 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:24 PM PDT 24
Peak memory	217120 kb
Host	smart-76892499-b177-4887-be23-ada7455a9827
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629819209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3629819209
Directory	/workspace/45.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/9.lc_ctrl_stress_all.655404999
Short name	T61
Test name
Test status
Simulation time	1354683817 ps
CPU time	43.86 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:33:07 PM PDT 24
Peak memory	250896 kb
Host	smart-369f03c4-239a-412f-8cd4-5bff4e927203
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655404999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all.655404999
Directory	/workspace/9.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.lc_ctrl_security_escalation.1291594196
Short name	T146
Test name
Test status
Simulation time	323631115 ps
CPU time	8.12 seconds
Started	Aug 17 06:32:50 PM PDT 24
Finished	Aug 17 06:32:59 PM PDT 24
Peak memory	226164 kb
Host	smart-aef1985b-fd7f-4a8f-b77b-c29d75d766ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291594196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1291594196
Directory	/workspace/31.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2955500854
Short name	T91
Test name
Test status
Simulation time	98663886 ps
CPU time	2.25 seconds
Started	Aug 17 06:29:10 PM PDT 24
Finished	Aug 17 06:29:12 PM PDT 24
Peak memory	218132 kb
Host	smart-3778d3bc-c9b8-40e3-99b1-943a9699cd5a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955500854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2955500854
Directory	/workspace/14.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/26.lc_ctrl_alert_test.2674550626
Short name	T32
Test name
Test status
Simulation time	80116364 ps
CPU time	0.97 seconds
Started	Aug 17 06:32:47 PM PDT 24
Finished	Aug 17 06:32:48 PM PDT 24
Peak memory	208828 kb
Host	smart-fd846f6f-25cd-47e0-901c-4edf5e32f2d5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674550626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2674550626
Directory	/workspace/26.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_errors.115635788
Short name	T6
Test name
Test status
Simulation time	7819495393 ps
CPU time	32.38 seconds
Started	Aug 17 06:32:15 PM PDT 24
Finished	Aug 17 06:32:47 PM PDT 24
Peak memory	218920 kb
Host	smart-5e84e416-e7e1-47a0-8483-071d5fbcfc39
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115635788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er rors.115635788
Directory	/workspace/12.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.4280821422
Short name	T172
Test name
Test status
Simulation time	18187377 ps
CPU time	1.18 seconds
Started	Aug 17 06:28:43 PM PDT 24
Finished	Aug 17 06:28:45 PM PDT 24
Peak memory	209932 kb
Host	smart-4ef9050b-aa1b-407e-b821-7c2cf69fa378
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280821422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin g.4280821422
Directory	/workspace/0.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3405359021
Short name	T124
Test name
Test status
Simulation time	2077916879 ps
CPU time	12.66 seconds
Started	Aug 17 06:28:39 PM PDT 24
Finished	Aug 17 06:28:52 PM PDT 24
Peak memory	209724 kb
Host	smart-c9717bc2-1dab-48ed-8d7a-826d79757132
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405359021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3405359021
Directory	/workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/default/1.lc_ctrl_stress_all.1966658897
Short name	T84
Test name
Test status
Simulation time	43311417883 ps
CPU time	162.65 seconds
Started	Aug 17 06:31:59 PM PDT 24
Finished	Aug 17 06:34:41 PM PDT 24
Peak memory	296740 kb
Host	smart-2d968e61-a940-4acf-99f2-f26d3256d1b5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966658897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all.1966658897
Directory	/workspace/1.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3659025004
Short name	T109
Test name
Test status
Simulation time	213438518 ps
CPU time	4.29 seconds
Started	Aug 17 06:28:46 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	218128 kb
Host	smart-2d8c9cb8-b3e5-4a1a-ae16-c9e69806c9c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659025004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg _err.3659025004
Directory	/workspace/18.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1110511208
Short name	T105
Test name
Test status
Simulation time	50591516 ps
CPU time	2.05 seconds
Started	Aug 17 06:28:43 PM PDT 24
Finished	Aug 17 06:28:46 PM PDT 24
Peak memory	222640 kb
Host	smart-854a1342-c34c-4a3d-aca3-c4f113c19bdc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110511208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg _err.1110511208
Directory	/workspace/11.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all.2972443230
Short name	T145
Test name
Test status
Simulation time	13863385450 ps
CPU time	237.95 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:36:16 PM PDT 24
Peak memory	270676 kb
Host	smart-796b26e0-561e-452c-b9cc-3e499e444490
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972443230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all.2972443230
Directory	/workspace/13.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_mubi.105183399
Short name	T23
Test name
Test status
Simulation time	967921573 ps
CPU time	11.86 seconds
Started	Aug 17 06:33:00 PM PDT 24
Finished	Aug 17 06:33:12 PM PDT 24
Peak memory	226068 kb
Host	smart-10fac558-0f01-45e6-b445-7504f49ffaca
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105183399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.105183399
Directory	/workspace/38.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/22.lc_ctrl_stress_all.1369158267
Short name	T90
Test name
Test status
Simulation time	15618547349 ps
CPU time	521.5 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:41:02 PM PDT 24
Peak memory	340036 kb
Host	smart-d30323c1-908b-46df-be30-ddc1e0e7fe1d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369158267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all.1369158267
Directory	/workspace/22.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/9.lc_ctrl_regwen_during_op.3554722445
Short name	T13
Test name
Test status
Simulation time	3939495346 ps
CPU time	7.63 seconds
Started	Aug 17 06:32:06 PM PDT 24
Finished	Aug 17 06:32:14 PM PDT 24
Peak memory	214656 kb
Host	smart-8bf3136e-0f71-472b-a157-19840c96b1e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554722445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3554722445
Directory	/workspace/9.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3527624251
Short name	T117
Test name
Test status
Simulation time	73281810 ps
CPU time	2.66 seconds
Started	Aug 17 06:28:49 PM PDT 24
Finished	Aug 17 06:28:52 PM PDT 24
Peak memory	218124 kb
Host	smart-d61e381b-62b3-4609-9397-2624ae3382cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527624251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg _err.3527624251
Directory	/workspace/13.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1020101101
Short name	T104
Test name
Test status
Simulation time	509300418 ps
CPU time	4.1 seconds
Started	Aug 17 06:28:56 PM PDT 24
Finished	Aug 17 06:29:00 PM PDT 24
Peak memory	218188 kb
Host	smart-fb678871-0571-45ac-9cd2-52421bceec85
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020101101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg _err.1020101101
Directory	/workspace/17.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1794570657
Short name	T100
Test name
Test status
Simulation time	43021742 ps
CPU time	0.96 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	217868 kb
Host	smart-09a22740-aae8-4d1e-a1df-de4a1a75fea8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794570657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1794570657
Directory	/workspace/0.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/default/0.lc_ctrl_smoke.2872725426
Short name	T553
Test name
Test status
Simulation time	500821261 ps
CPU time	5.97 seconds
Started	Aug 17 06:31:54 PM PDT 24
Finished	Aug 17 06:32:00 PM PDT 24
Peak memory	217584 kb
Host	smart-192d0164-1302-4766-b6b2-ae9c98c0b80c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872725426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2872725426
Directory	/workspace/0.lc_ctrl_smoke/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2481896132
Short name	T885
Test name
Test status
Simulation time	158862397 ps
CPU time	2.63 seconds
Started	Aug 17 06:28:39 PM PDT 24
Finished	Aug 17 06:28:47 PM PDT 24
Peak memory	218120 kb
Host	smart-5c212c11-8b39-42f8-8f46-b0dd8dffb886
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481896132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2481896132
Directory	/workspace/0.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1075386868
Short name	T120
Test name
Test status
Simulation time	110190261 ps
CPU time	3.48 seconds
Started	Aug 17 06:28:37 PM PDT 24
Finished	Aug 17 06:28:40 PM PDT 24
Peak memory	223092 kb
Host	smart-b9431aa6-a54f-4014-96b7-05a54aaf119f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075386868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_ err.1075386868
Directory	/workspace/1.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1687160834
Short name	T118
Test name
Test status
Simulation time	182839076 ps
CPU time	3.01 seconds
Started	Aug 17 06:29:03 PM PDT 24
Finished	Aug 17 06:29:06 PM PDT 24
Peak memory	222820 kb
Host	smart-2a55572c-acac-4f93-8c7a-8543ba1cdb02
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687160834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg _err.1687160834
Directory	/workspace/19.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.139596282
Short name	T226
Test name
Test status
Simulation time	33926486 ps
CPU time	0.91 seconds
Started	Aug 17 06:31:28 PM PDT 24
Finished	Aug 17 06:31:29 PM PDT 24
Peak memory	211756 kb
Host	smart-19c84cb3-24d3-4621-9dce-ad22c10d4423
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139596282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr l_volatile_unlock_smoke.139596282
Directory	/workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_claim_transition_if.2836343838
Short name	T187
Test name
Test status
Simulation time	10568252 ps
CPU time	0.94 seconds
Started	Aug 17 06:31:50 PM PDT 24
Finished	Aug 17 06:31:51 PM PDT 24
Peak memory	208672 kb
Host	smart-40f04d73-9fcb-4c70-95d8-418c740f7110
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2836343838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2836343838
Directory	/workspace/4.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/5.lc_ctrl_claim_transition_if.2364961495
Short name	T189
Test name
Test status
Simulation time	19504301 ps
CPU time	0.8 seconds
Started	Aug 17 06:32:10 PM PDT 24
Finished	Aug 17 06:32:11 PM PDT 24
Peak memory	208896 kb
Host	smart-4993b76d-3c75-4978-b482-36600d647e14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2364961495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2364961495
Directory	/workspace/5.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/8.lc_ctrl_claim_transition_if.58442681
Short name	T188
Test name
Test status
Simulation time	36842077 ps
CPU time	0.87 seconds
Started	Aug 17 06:32:16 PM PDT 24
Finished	Aug 17 06:32:17 PM PDT 24
Peak memory	208744 kb
Host	smart-19ec3f0f-e6ab-40ce-97ca-f25ea476edb2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=58442681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.58442681
Directory	/workspace/8.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3374191991
Short name	T97
Test name
Test status
Simulation time	78770455 ps
CPU time	2.6 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:44 PM PDT 24
Peak memory	218152 kb
Host	smart-ff9a3264-4088-445c-8c9c-c6ef84e8df8a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374191991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_ err.3374191991
Directory	/workspace/0.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3633362632
Short name	T92
Test name
Test status
Simulation time	220390765 ps
CPU time	1.92 seconds
Started	Aug 17 06:28:47 PM PDT 24
Finished	Aug 17 06:28:49 PM PDT 24
Peak memory	222384 kb
Host	smart-220f81a2-9d6c-4739-93ef-4346300da72e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633362632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg _err.3633362632
Directory	/workspace/10.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1605243413
Short name	T112
Test name
Test status
Simulation time	372593077 ps
CPU time	1.77 seconds
Started	Aug 17 06:29:12 PM PDT 24
Finished	Aug 17 06:29:14 PM PDT 24
Peak memory	221976 kb
Host	smart-d0a969c8-b9db-449d-af4f-63e6c5233a2d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605243413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg _err.1605243413
Directory	/workspace/15.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4275666205
Short name	T116
Test name
Test status
Simulation time	44686004 ps
CPU time	1.89 seconds
Started	Aug 17 06:28:45 PM PDT 24
Finished	Aug 17 06:28:47 PM PDT 24
Peak memory	222108 kb
Host	smart-75044ef0-8eac-4c27-aa64-ff0a15a6e6b0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275666205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_ err.4275666205
Directory	/workspace/3.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3179981878
Short name	T110
Test name
Test status
Simulation time	152352779 ps
CPU time	2.65 seconds
Started	Aug 17 06:28:57 PM PDT 24
Finished	Aug 17 06:29:00 PM PDT 24
Peak memory	222656 kb
Host	smart-e9c7821b-3bd2-463e-bd94-1e509f99ee92
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179981878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_ err.3179981878
Directory	/workspace/4.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2243837071
Short name	T121
Test name
Test status
Simulation time	56452425 ps
CPU time	2.5 seconds
Started	Aug 17 06:29:07 PM PDT 24
Finished	Aug 17 06:29:09 PM PDT 24
Peak memory	218220 kb
Host	smart-fa8fcad4-a46e-4e1f-8811-9f1467313806
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243837071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_ err.2243837071
Directory	/workspace/5.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1350835633
Short name	T122
Test name
Test status
Simulation time	44745901 ps
CPU time	2.26 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:44 PM PDT 24
Peak memory	222716 kb
Host	smart-60a19aca-219a-442e-b4b7-3365242a5f13
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350835633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_ err.1350835633
Directory	/workspace/7.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_post_trans.4202457216
Short name	T202
Test name
Test status
Simulation time	557184123 ps
CPU time	7.58 seconds
Started	Aug 17 06:32:03 PM PDT 24
Finished	Aug 17 06:32:10 PM PDT 24
Peak memory	250904 kb
Host	smart-4f2f4011-e5de-4371-9e92-d55220d92798
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4202457216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.4202457216
Directory	/workspace/10.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/26.lc_ctrl_smoke.3767244067
Short name	T11
Test name
Test status
Simulation time	186852218 ps
CPU time	3.53 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:27 PM PDT 24
Peak memory	217580 kb
Host	smart-8c444ef6-1c98-47e1-b330-02f9fd401188
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3767244067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3767244067
Directory	/workspace/26.lc_ctrl_smoke/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.4017489228
Short name	T107
Test name
Test status
Simulation time	197302227 ps
CPU time	1.35 seconds
Started	Aug 17 06:28:48 PM PDT 24
Finished	Aug 17 06:28:49 PM PDT 24
Peak memory	209916 kb
Host	smart-38339047-693c-4130-bda3-da953e591ea6
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017489228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas h.4017489228
Directory	/workspace/0.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1855551181
Short name	T934
Test name
Test status
Simulation time	30823052 ps
CPU time	1.17 seconds
Started	Aug 17 06:28:46 PM PDT 24
Finished	Aug 17 06:28:47 PM PDT 24
Peak memory	218528 kb
Host	smart-9c146bcc-5eeb-4899-a778-d9746765d99b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855551181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese t.1855551181
Directory	/workspace/0.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1546059080
Short name	T897
Test name
Test status
Simulation time	27770951 ps
CPU time	1.69 seconds
Started	Aug 17 06:28:35 PM PDT 24
Finished	Aug 17 06:28:37 PM PDT 24
Peak memory	218600 kb
Host	smart-85be1a94-da59-4d51-b0c3-0ab3221b1f74
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546059080 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1546059080
Directory	/workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1250916183
Short name	T980
Test name
Test status
Simulation time	205106645 ps
CPU time	1.8 seconds
Started	Aug 17 06:28:44 PM PDT 24
Finished	Aug 17 06:28:46 PM PDT 24
Peak memory	209864 kb
Host	smart-ccc2dd52-491b-4015-9a01-6e51f69f8d3c
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250916183 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1250916183
Directory	/workspace/0.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3752319375
Short name	T942
Test name
Test status
Simulation time	1171283158 ps
CPU time	7.33 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:48 PM PDT 24
Peak memory	209128 kb
Host	smart-2aab05de-eda3-4a43-9db9-f56a9f834820
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752319375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3752319375
Directory	/workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3438632581
Short name	T927
Test name
Test status
Simulation time	1523825677 ps
CPU time	8.18 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:49 PM PDT 24
Peak memory	209692 kb
Host	smart-5f7910f2-fd0c-4575-b7e3-658e4f02e9ad
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438632581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3438632581
Directory	/workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1539093999
Short name	T916
Test name
Test status
Simulation time	751150918 ps
CPU time	1.91 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:43 PM PDT 24
Peak memory	211540 kb
Host	smart-2a1e9f93-3b9c-4358-a590-24ce9e727c14
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539093999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1539093999
Directory	/workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.122644872
Short name	T996
Test name
Test status
Simulation time	67604041 ps
CPU time	2.38 seconds
Started	Aug 17 06:28:38 PM PDT 24
Finished	Aug 17 06:28:41 PM PDT 24
Peak memory	219980 kb
Host	smart-7721a909-5fcc-4653-b193-e0a364c57603
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122644 872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.122644872
Directory	/workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2742992709
Short name	T129
Test name
Test status
Simulation time	77787466 ps
CPU time	1.08 seconds
Started	Aug 17 06:28:49 PM PDT 24
Finished	Aug 17 06:28:50 PM PDT 24
Peak memory	209796 kb
Host	smart-1d9c953a-f9e8-4da1-b1cb-2361efce5447
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742992709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_rw.2742992709
Directory	/workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3738745750
Short name	T924
Test name
Test status
Simulation time	116780935 ps
CPU time	1.36 seconds
Started	Aug 17 06:28:39 PM PDT 24
Finished	Aug 17 06:28:41 PM PDT 24
Peak memory	211636 kb
Host	smart-48ddd53a-6d73-4db5-a4a8-040ef46dd90f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738745750 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3738745750
Directory	/workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1204943769
Short name	T999
Test name
Test status
Simulation time	38819444 ps
CPU time	1.44 seconds
Started	Aug 17 06:28:51 PM PDT 24
Finished	Aug 17 06:28:53 PM PDT 24
Peak memory	209980 kb
Host	smart-850d81e9-969d-4e31-a4dd-dae396b06cb0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204943769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _same_csr_outstanding.1204943769
Directory	/workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.372888416
Short name	T955
Test name
Test status
Simulation time	42908455 ps
CPU time	1.32 seconds
Started	Aug 17 06:28:46 PM PDT 24
Finished	Aug 17 06:28:48 PM PDT 24
Peak memory	209240 kb
Host	smart-b1a63af0-910d-4822-923b-87180f48fcfa
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372888416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing .372888416
Directory	/workspace/1.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2410634480
Short name	T925
Test name
Test status
Simulation time	62766581 ps
CPU time	1.11 seconds
Started	Aug 17 06:29:05 PM PDT 24
Finished	Aug 17 06:29:06 PM PDT 24
Peak memory	209900 kb
Host	smart-ec4c61ad-0847-4c69-b4c9-70d8366ea259
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410634480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas h.2410634480
Directory	/workspace/1.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.263597106
Short name	T166
Test name
Test status
Simulation time	18770265 ps
CPU time	0.97 seconds
Started	Aug 17 06:28:47 PM PDT 24
Finished	Aug 17 06:28:48 PM PDT 24
Peak memory	210480 kb
Host	smart-7ff51e38-0a3d-4ae3-bf59-32c1da50a717
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263597106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset .263597106
Directory	/workspace/1.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2786224013
Short name	T99
Test name
Test status
Simulation time	55735354 ps
CPU time	1.59 seconds
Started	Aug 17 06:28:39 PM PDT 24
Finished	Aug 17 06:28:45 PM PDT 24
Peak memory	219376 kb
Host	smart-67ffe171-7de4-4cbb-95da-b7568af8c0f3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786224013 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2786224013
Directory	/workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3004868568
Short name	T881
Test name
Test status
Simulation time	15262723 ps
CPU time	1.01 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:41 PM PDT 24
Peak memory	209936 kb
Host	smart-93a6323a-bd24-4cac-8a96-26f86f1490b4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004868568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3004868568
Directory	/workspace/1.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1805947266
Short name	T945
Test name
Test status
Simulation time	134278831 ps
CPU time	2.16 seconds
Started	Aug 17 06:28:36 PM PDT 24
Finished	Aug 17 06:28:44 PM PDT 24
Peak memory	209848 kb
Host	smart-683a9365-86fb-4ede-9417-f37bd9999474
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805947266 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1805947266
Directory	/workspace/1.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4173989285
Short name	T108
Test name
Test status
Simulation time	1091403486 ps
CPU time	5.67 seconds
Started	Aug 17 06:28:38 PM PDT 24
Finished	Aug 17 06:28:49 PM PDT 24
Peak memory	209672 kb
Host	smart-239d1945-a373-46d7-9c6e-91fbd59619ba
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173989285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.4173989285
Directory	/workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2927284477
Short name	T882
Test name
Test status
Simulation time	560563904 ps
CPU time	13 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:53 PM PDT 24
Peak memory	209720 kb
Host	smart-054d451b-82ba-4373-aa14-44993321c0ee
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927284477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2927284477
Directory	/workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1725315910
Short name	T878
Test name
Test status
Simulation time	97517703 ps
CPU time	1.95 seconds
Started	Aug 17 06:28:44 PM PDT 24
Finished	Aug 17 06:28:46 PM PDT 24
Peak memory	211372 kb
Host	smart-7f8884ed-e0bd-42f4-94a6-528d0fc11e5c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725315910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1725315910
Directory	/workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1585763634
Short name	T946
Test name
Test status
Simulation time	200967226 ps
CPU time	3.5 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:45 PM PDT 24
Peak memory	223668 kb
Host	smart-8d2f2e6a-c21c-4d62-96c1-13aa08823804
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158576 3634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1585763634
Directory	/workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1456721717
Short name	T900
Test name
Test status
Simulation time	495738849 ps
CPU time	3.69 seconds
Started	Aug 17 06:28:36 PM PDT 24
Finished	Aug 17 06:28:39 PM PDT 24
Peak memory	209852 kb
Host	smart-90d17eea-fd35-46ee-b66c-ba39c5efa589
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456721717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_rw.1456721717
Directory	/workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2130729820
Short name	T994
Test name
Test status
Simulation time	30604577 ps
CPU time	1.08 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:42 PM PDT 24
Peak memory	209936 kb
Host	smart-e2134213-8c46-4d22-afbd-b4de47729f59
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130729820 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2130729820
Directory	/workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.453320647
Short name	T910
Test name
Test status
Simulation time	21241514 ps
CPU time	1.38 seconds
Started	Aug 17 06:28:38 PM PDT 24
Finished	Aug 17 06:28:40 PM PDT 24
Peak memory	210048 kb
Host	smart-510b88eb-d207-4b67-8b06-8cdd4f9fa2b8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453320647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ same_csr_outstanding.453320647
Directory	/workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2362009679
Short name	T921
Test name
Test status
Simulation time	49881890 ps
CPU time	2.26 seconds
Started	Aug 17 06:28:39 PM PDT 24
Finished	Aug 17 06:28:41 PM PDT 24
Peak memory	218584 kb
Host	smart-70bd168b-133d-45d3-a5eb-c2396fafa796
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362009679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2362009679
Directory	/workspace/1.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1304729514
Short name	T961
Test name
Test status
Simulation time	27800310 ps
CPU time	1.5 seconds
Started	Aug 17 06:28:52 PM PDT 24
Finished	Aug 17 06:28:53 PM PDT 24
Peak memory	218328 kb
Host	smart-bc6a6824-925c-48ce-9a9b-7de205ee6bbf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304729514 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1304729514
Directory	/workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2655115511
Short name	T170
Test name
Test status
Simulation time	16009268 ps
CPU time	0.86 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	209908 kb
Host	smart-f4d5e718-77a1-485b-b488-f40767ce96c3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655115511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2655115511
Directory	/workspace/10.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3464449715
Short name	T180
Test name
Test status
Simulation time	34359433 ps
CPU time	1.28 seconds
Started	Aug 17 06:28:43 PM PDT 24
Finished	Aug 17 06:28:44 PM PDT 24
Peak memory	209936 kb
Host	smart-50822911-e60b-4e91-8626-fbaea0955ca0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464449715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_same_csr_outstanding.3464449715
Directory	/workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3193024741
Short name	T889
Test name
Test status
Simulation time	107276756 ps
CPU time	1.77 seconds
Started	Aug 17 06:28:43 PM PDT 24
Finished	Aug 17 06:28:45 PM PDT 24
Peak memory	218088 kb
Host	smart-152e8982-621b-4d6d-b89f-318cdccca113
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193024741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3193024741
Directory	/workspace/10.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3615515297
Short name	T941
Test name
Test status
Simulation time	54204410 ps
CPU time	1.25 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:52 PM PDT 24
Peak memory	218392 kb
Host	smart-4984a1de-5308-4709-ba6b-3beb4b65ac81
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615515297 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3615515297
Directory	/workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1497295800
Short name	T167
Test name
Test status
Simulation time	113786785 ps
CPU time	0.86 seconds
Started	Aug 17 06:28:42 PM PDT 24
Finished	Aug 17 06:28:43 PM PDT 24
Peak memory	209632 kb
Host	smart-570632c5-2fa3-4134-b45a-c08b536571f5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497295800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1497295800
Directory	/workspace/11.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.255471912
Short name	T948
Test name
Test status
Simulation time	15068683 ps
CPU time	1.16 seconds
Started	Aug 17 06:28:39 PM PDT 24
Finished	Aug 17 06:28:40 PM PDT 24
Peak memory	209904 kb
Host	smart-7d88d26f-fe5d-4059-982f-2c5ed69dd4f6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255471912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl _same_csr_outstanding.255471912
Directory	/workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.298608894
Short name	T931
Test name
Test status
Simulation time	29895303 ps
CPU time	1.83 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:52 PM PDT 24
Peak memory	219192 kb
Host	smart-2a78a97b-a106-4300-8bea-e254e9ba96f4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298608894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.298608894
Directory	/workspace/11.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.616480196
Short name	T967
Test name
Test status
Simulation time	16204883 ps
CPU time	1.19 seconds
Started	Aug 17 06:28:54 PM PDT 24
Finished	Aug 17 06:28:55 PM PDT 24
Peak memory	218164 kb
Host	smart-fe8ebcbb-5663-426b-9e86-67f8fc9776d0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616480196 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.616480196
Directory	/workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.4220929880
Short name	T169
Test name
Test status
Simulation time	30165413 ps
CPU time	0.86 seconds
Started	Aug 17 06:29:04 PM PDT 24
Finished	Aug 17 06:29:05 PM PDT 24
Peak memory	209752 kb
Host	smart-4a1f2aa0-efd2-4e2f-a42e-773dfae23ab9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220929880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.4220929880
Directory	/workspace/12.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1729126306
Short name	T896
Test name
Test status
Simulation time	76588093 ps
CPU time	1.35 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:43 PM PDT 24
Peak memory	209912 kb
Host	smart-8187aee0-f216-4a99-96be-d7d5b54bf0f2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729126306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr l_same_csr_outstanding.1729126306
Directory	/workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3073528021
Short name	T98
Test name
Test status
Simulation time	99549351 ps
CPU time	2.38 seconds
Started	Aug 17 06:28:43 PM PDT 24
Finished	Aug 17 06:28:46 PM PDT 24
Peak memory	218060 kb
Host	smart-b21a4950-5a43-4ecc-98be-2105ab844386
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073528021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3073528021
Directory	/workspace/12.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.101774774
Short name	T922
Test name
Test status
Simulation time	462334934 ps
CPU time	2.21 seconds
Started	Aug 17 06:28:43 PM PDT 24
Finished	Aug 17 06:28:45 PM PDT 24
Peak memory	218124 kb
Host	smart-53b8780d-2ce5-40de-8616-d2c82c73b30e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101774774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_ err.101774774
Directory	/workspace/12.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2605374076
Short name	T969
Test name
Test status
Simulation time	28179096 ps
CPU time	1.46 seconds
Started	Aug 17 06:28:56 PM PDT 24
Finished	Aug 17 06:28:58 PM PDT 24
Peak memory	219276 kb
Host	smart-23b49046-7a47-4753-a865-06ea7e58c4dc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605374076 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2605374076
Directory	/workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1091077473
Short name	T970
Test name
Test status
Simulation time	18064822 ps
CPU time	0.87 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	209792 kb
Host	smart-a8e6e8a2-84c5-409a-a21f-e2f0bacbe037
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091077473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1091077473
Directory	/workspace/13.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1051635249
Short name	T991
Test name
Test status
Simulation time	45437499 ps
CPU time	0.98 seconds
Started	Aug 17 06:28:52 PM PDT 24
Finished	Aug 17 06:28:54 PM PDT 24
Peak memory	209936 kb
Host	smart-b4a96aa8-6c5f-4151-a857-984c74f44e14
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051635249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr l_same_csr_outstanding.1051635249
Directory	/workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1172768373
Short name	T914
Test name
Test status
Simulation time	321721871 ps
CPU time	3.98 seconds
Started	Aug 17 06:29:22 PM PDT 24
Finished	Aug 17 06:29:26 PM PDT 24
Peak memory	218128 kb
Host	smart-b797d7f9-aecc-497a-9bda-7a053f39755b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172768373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1172768373
Directory	/workspace/13.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.267306215
Short name	T904
Test name
Test status
Simulation time	29926029 ps
CPU time	1.66 seconds
Started	Aug 17 06:28:51 PM PDT 24
Finished	Aug 17 06:28:53 PM PDT 24
Peak memory	218372 kb
Host	smart-d04ff98e-52f1-4c10-baed-b30a58261e04
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267306215 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.267306215
Directory	/workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1650545685
Short name	T181
Test name
Test status
Simulation time	13864940 ps
CPU time	0.82 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:46 PM PDT 24
Peak memory	209836 kb
Host	smart-16c1e7a8-9144-4ef1-a1c0-11ddba3a8ecc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650545685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1650545685
Directory	/workspace/14.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4146356680
Short name	T177
Test name
Test status
Simulation time	256473655 ps
CPU time	1.17 seconds
Started	Aug 17 06:28:58 PM PDT 24
Finished	Aug 17 06:28:59 PM PDT 24
Peak memory	209940 kb
Host	smart-9461ec20-56bc-47a1-b118-4f4e4f082b7c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146356680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr l_same_csr_outstanding.4146356680
Directory	/workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1528917073
Short name	T192
Test name
Test status
Simulation time	126719719 ps
CPU time	2.64 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:43 PM PDT 24
Peak memory	218148 kb
Host	smart-4e2575de-6786-4cba-8b01-1e2c4d3b7e36
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528917073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg _err.1528917073
Directory	/workspace/14.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1748171364
Short name	T947
Test name
Test status
Simulation time	17157418 ps
CPU time	1.07 seconds
Started	Aug 17 06:28:51 PM PDT 24
Finished	Aug 17 06:28:52 PM PDT 24
Peak memory	218212 kb
Host	smart-b07d5dea-5d6d-454e-8a24-83560554365e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748171364 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1748171364
Directory	/workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2292870523
Short name	T939
Test name
Test status
Simulation time	47235618 ps
CPU time	0.86 seconds
Started	Aug 17 06:28:54 PM PDT 24
Finished	Aug 17 06:28:55 PM PDT 24
Peak memory	217928 kb
Host	smart-5bbeea00-3086-48da-a0fc-779dfa6cd78b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292870523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2292870523
Directory	/workspace/15.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3806663329
Short name	T993
Test name
Test status
Simulation time	133137137 ps
CPU time	1.27 seconds
Started	Aug 17 06:28:51 PM PDT 24
Finished	Aug 17 06:28:52 PM PDT 24
Peak memory	209944 kb
Host	smart-c4c1281c-e732-4f2b-997b-b28b73fe4e03
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806663329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr l_same_csr_outstanding.3806663329
Directory	/workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.482910240
Short name	T935
Test name
Test status
Simulation time	203727202 ps
CPU time	4.23 seconds
Started	Aug 17 06:28:48 PM PDT 24
Finished	Aug 17 06:28:53 PM PDT 24
Peak memory	218060 kb
Host	smart-1203494a-baf2-4d3f-867a-35414d09bb48
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482910240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.482910240
Directory	/workspace/15.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.296489388
Short name	T995
Test name
Test status
Simulation time	66274342 ps
CPU time	1.2 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:42 PM PDT 24
Peak memory	218268 kb
Host	smart-b537a0ec-580f-4b5f-b58e-d64e3064434a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296489388 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.296489388
Directory	/workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.665533935
Short name	T875
Test name
Test status
Simulation time	19912984 ps
CPU time	0.95 seconds
Started	Aug 17 06:28:48 PM PDT 24
Finished	Aug 17 06:28:49 PM PDT 24
Peak memory	209956 kb
Host	smart-a270a90f-7ae2-4ce3-8dd8-9887785f561c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665533935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.665533935
Directory	/workspace/16.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3427774973
Short name	T176
Test name
Test status
Simulation time	25391040 ps
CPU time	1.48 seconds
Started	Aug 17 06:29:19 PM PDT 24
Finished	Aug 17 06:29:20 PM PDT 24
Peak memory	210016 kb
Host	smart-b4043ce3-ab22-4b24-8edc-6fd2ff135f69
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427774973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_same_csr_outstanding.3427774973
Directory	/workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.46208434
Short name	T1000
Test name
Test status
Simulation time	54150116 ps
CPU time	2.13 seconds
Started	Aug 17 06:28:49 PM PDT 24
Finished	Aug 17 06:28:52 PM PDT 24
Peak memory	218232 kb
Host	smart-86175c68-b409-4b68-982c-6c9940bba864
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46208434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.46208434
Directory	/workspace/16.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3225577617
Short name	T953
Test name
Test status
Simulation time	467031221 ps
CPU time	1.76 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:42 PM PDT 24
Peak memory	219180 kb
Host	smart-b198bd60-e763-4477-8d74-7c1695b4e9d5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225577617 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3225577617
Directory	/workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1137932736
Short name	T966
Test name
Test status
Simulation time	40595556 ps
CPU time	0.99 seconds
Started	Aug 17 06:29:19 PM PDT 24
Finished	Aug 17 06:29:20 PM PDT 24
Peak memory	209936 kb
Host	smart-037c2be8-2eb1-4cff-a013-9e783a45a3f8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137932736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1137932736
Directory	/workspace/17.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2666706659
Short name	T920
Test name
Test status
Simulation time	87242059 ps
CPU time	1.11 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	210076 kb
Host	smart-804a6a30-0fe2-4251-8e8c-c45c6a6183fd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666706659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr l_same_csr_outstanding.2666706659
Directory	/workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3855514019
Short name	T115
Test name
Test status
Simulation time	143565273 ps
CPU time	2.37 seconds
Started	Aug 17 06:29:02 PM PDT 24
Finished	Aug 17 06:29:04 PM PDT 24
Peak memory	218396 kb
Host	smart-9cb9ea4e-d332-4897-9ab3-207c17bcc547
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855514019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3855514019
Directory	/workspace/17.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1296869699
Short name	T998
Test name
Test status
Simulation time	62456896 ps
CPU time	1.26 seconds
Started	Aug 17 06:29:00 PM PDT 24
Finished	Aug 17 06:29:01 PM PDT 24
Peak memory	218220 kb
Host	smart-2d2fcfe5-62c6-4a6e-adce-78b693a7b5e4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296869699 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1296869699
Directory	/workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.46578017
Short name	T992
Test name
Test status
Simulation time	26227289 ps
CPU time	1.07 seconds
Started	Aug 17 06:28:58 PM PDT 24
Finished	Aug 17 06:28:59 PM PDT 24
Peak memory	209900 kb
Host	smart-79f23c8a-f14f-44ff-9e55-269ef9035322
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46578017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.46578017
Directory	/workspace/18.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2539718191
Short name	T983
Test name
Test status
Simulation time	29514506 ps
CPU time	1.04 seconds
Started	Aug 17 06:29:07 PM PDT 24
Finished	Aug 17 06:29:08 PM PDT 24
Peak memory	210036 kb
Host	smart-681bcec8-e07f-4359-823d-ace6a3210f58
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539718191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr l_same_csr_outstanding.2539718191
Directory	/workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1854607347
Short name	T989
Test name
Test status
Simulation time	41827917 ps
CPU time	2.71 seconds
Started	Aug 17 06:29:21 PM PDT 24
Finished	Aug 17 06:29:24 PM PDT 24
Peak memory	218120 kb
Host	smart-eaa74c84-5c79-43c5-9ae4-7d6023943881
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854607347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1854607347
Directory	/workspace/18.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3391192769
Short name	T956
Test name
Test status
Simulation time	56094293 ps
CPU time	1.62 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:42 PM PDT 24
Peak memory	218204 kb
Host	smart-320c0357-6514-45ca-a2c4-d1654172c505
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391192769 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3391192769
Directory	/workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1534462357
Short name	T171
Test name
Test status
Simulation time	24420870 ps
CPU time	0.92 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	209588 kb
Host	smart-9de05e55-acfa-49c9-b97c-eb867043251d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534462357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1534462357
Directory	/workspace/19.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1003395649
Short name	T933
Test name
Test status
Simulation time	41283377 ps
CPU time	1.22 seconds
Started	Aug 17 06:28:51 PM PDT 24
Finished	Aug 17 06:28:52 PM PDT 24
Peak memory	209856 kb
Host	smart-d2fa9734-b562-4414-8984-1c0930a4e35f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003395649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr l_same_csr_outstanding.1003395649
Directory	/workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2732450126
Short name	T928
Test name
Test status
Simulation time	73875745 ps
CPU time	2.2 seconds
Started	Aug 17 06:29:15 PM PDT 24
Finished	Aug 17 06:29:17 PM PDT 24
Peak memory	218136 kb
Host	smart-f366ceae-8a81-48a0-9216-ed645f7580f4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732450126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2732450126
Directory	/workspace/19.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.787322461
Short name	T949
Test name
Test status
Simulation time	119215021 ps
CPU time	1.05 seconds
Started	Aug 17 06:28:44 PM PDT 24
Finished	Aug 17 06:28:45 PM PDT 24
Peak memory	209936 kb
Host	smart-cbf1738b-9613-4c2f-9af1-f50d3c63d9fb
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787322461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing .787322461
Directory	/workspace/2.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3363377741
Short name	T917
Test name
Test status
Simulation time	77003211 ps
CPU time	1.85 seconds
Started	Aug 17 06:28:43 PM PDT 24
Finished	Aug 17 06:28:45 PM PDT 24
Peak memory	209900 kb
Host	smart-23ad5fab-e8c1-4f94-913f-f5e988a0c35a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363377741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas h.3363377741
Directory	/workspace/2.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.803953081
Short name	T887
Test name
Test status
Simulation time	66287859 ps
CPU time	0.95 seconds
Started	Aug 17 06:28:56 PM PDT 24
Finished	Aug 17 06:28:57 PM PDT 24
Peak memory	210556 kb
Host	smart-724e5d99-f006-4010-9121-bc1adfd540f2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803953081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset .803953081
Directory	/workspace/2.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3386065325
Short name	T929
Test name
Test status
Simulation time	27870732 ps
CPU time	1.52 seconds
Started	Aug 17 06:28:39 PM PDT 24
Finished	Aug 17 06:28:41 PM PDT 24
Peak memory	218204 kb
Host	smart-3b390c90-5ee2-485b-a9bb-84f76be74d17
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386065325 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3386065325
Directory	/workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2025454505
Short name	T173
Test name
Test status
Simulation time	23324063 ps
CPU time	0.9 seconds
Started	Aug 17 06:28:56 PM PDT 24
Finished	Aug 17 06:28:57 PM PDT 24
Peak memory	209912 kb
Host	smart-a7168fa9-bc19-4d29-a754-072b9156b3e9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025454505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2025454505
Directory	/workspace/2.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2025560810
Short name	T926
Test name
Test status
Simulation time	163436237 ps
CPU time	2.49 seconds
Started	Aug 17 06:28:46 PM PDT 24
Finished	Aug 17 06:28:48 PM PDT 24
Peak memory	209876 kb
Host	smart-aa8e05bc-92b0-447b-9a84-b1b5f412b431
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025560810 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2025560810
Directory	/workspace/2.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.4075810122
Short name	T973
Test name
Test status
Simulation time	1977445452 ps
CPU time	5.37 seconds
Started	Aug 17 06:28:43 PM PDT 24
Finished	Aug 17 06:28:48 PM PDT 24
Peak memory	209560 kb
Host	smart-5f6fc4ed-2e43-4d62-8d84-6b19311cf017
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075810122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.4075810122
Directory	/workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2059878929
Short name	T886
Test name
Test status
Simulation time	3469687753 ps
CPU time	20.14 seconds
Started	Aug 17 06:28:38 PM PDT 24
Finished	Aug 17 06:28:59 PM PDT 24
Peak memory	209264 kb
Host	smart-5f89ef3d-0ae6-4b60-adfc-8bc108e34a44
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059878929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.2059878929
Directory	/workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.357144397
Short name	T965
Test name
Test status
Simulation time	406515806 ps
CPU time	2.44 seconds
Started	Aug 17 06:28:56 PM PDT 24
Finished	Aug 17 06:28:58 PM PDT 24
Peak memory	211568 kb
Host	smart-0a3144af-7ba5-48d8-b57a-e819f32d533c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357144397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.357144397
Directory	/workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1684827488
Short name	T975
Test name
Test status
Simulation time	426076475 ps
CPU time	2.52 seconds
Started	Aug 17 06:28:47 PM PDT 24
Finished	Aug 17 06:28:50 PM PDT 24
Peak memory	218244 kb
Host	smart-3f7eeca0-5d85-4211-9b44-a89d9b95cc99
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168482 7488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1684827488
Directory	/workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1144013313
Short name	T879
Test name
Test status
Simulation time	182900118 ps
CPU time	4.71 seconds
Started	Aug 17 06:28:56 PM PDT 24
Finished	Aug 17 06:29:01 PM PDT 24
Peak memory	209868 kb
Host	smart-76e075f7-ff29-4fad-a36b-df9ec14346a2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144013313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_rw.1144013313
Directory	/workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4294468853
Short name	T902
Test name
Test status
Simulation time	24599886 ps
CPU time	1.08 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:42 PM PDT 24
Peak memory	209296 kb
Host	smart-f49cdf1b-bf56-4d5a-895c-1347825a7acc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294468853 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4294468853
Directory	/workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1945046706
Short name	T899
Test name
Test status
Simulation time	56911168 ps
CPU time	1.12 seconds
Started	Aug 17 06:28:48 PM PDT 24
Finished	Aug 17 06:28:50 PM PDT 24
Peak memory	209936 kb
Host	smart-38772a1a-98ac-4710-9d64-a427c33e9f68
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945046706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl _same_csr_outstanding.1945046706
Directory	/workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2310399924
Short name	T951
Test name
Test status
Simulation time	79481060 ps
CPU time	2.48 seconds
Started	Aug 17 06:28:35 PM PDT 24
Finished	Aug 17 06:28:38 PM PDT 24
Peak memory	217972 kb
Host	smart-1caa971b-a69e-4356-8bdc-dc8f59e0379a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310399924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2310399924
Directory	/workspace/2.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.687216203
Short name	T113
Test name
Test status
Simulation time	215944068 ps
CPU time	3.58 seconds
Started	Aug 17 06:28:36 PM PDT 24
Finished	Aug 17 06:28:40 PM PDT 24
Peak memory	218120 kb
Host	smart-e62faac9-468c-47a3-b87b-35b432eca7ef
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687216203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e rr.687216203
Directory	/workspace/2.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4217967633
Short name	T1002
Test name
Test status
Simulation time	25443583 ps
CPU time	1.33 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	210000 kb
Host	smart-b0802850-e9a7-4857-a70d-2aaaf927621c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217967633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin g.4217967633
Directory	/workspace/3.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3608881335
Short name	T892
Test name
Test status
Simulation time	72670156 ps
CPU time	1.25 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:48 PM PDT 24
Peak memory	209812 kb
Host	smart-83440ec4-a746-4a42-b3ad-64370332ee9a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608881335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas h.3608881335
Directory	/workspace/3.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3855629446
Short name	T168
Test name
Test status
Simulation time	61828870 ps
CPU time	1.07 seconds
Started	Aug 17 06:28:42 PM PDT 24
Finished	Aug 17 06:28:44 PM PDT 24
Peak memory	219868 kb
Host	smart-c5bc47e2-8cd4-4b22-a546-9b4bbc16d34c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855629446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese t.3855629446
Directory	/workspace/3.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3778486347
Short name	T940
Test name
Test status
Simulation time	65472720 ps
CPU time	1.73 seconds
Started	Aug 17 06:28:42 PM PDT 24
Finished	Aug 17 06:28:44 PM PDT 24
Peak memory	218840 kb
Host	smart-6ca4323f-3290-4724-beaa-26f3468159ba
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778486347 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3778486347
Directory	/workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2963267040
Short name	T988
Test name
Test status
Simulation time	18932483 ps
CPU time	0.93 seconds
Started	Aug 17 06:28:39 PM PDT 24
Finished	Aug 17 06:28:40 PM PDT 24
Peak memory	209940 kb
Host	smart-30aa87e2-2e5e-4629-8372-f15bbada65d0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963267040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2963267040
Directory	/workspace/3.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1223380271
Short name	T919
Test name
Test status
Simulation time	22804258 ps
CPU time	0.89 seconds
Started	Aug 17 06:28:44 PM PDT 24
Finished	Aug 17 06:28:45 PM PDT 24
Peak memory	209840 kb
Host	smart-5b4b9010-1760-41b5-ba4a-0c7f3a235dce
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223380271 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1223380271
Directory	/workspace/3.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.390641571
Short name	T877
Test name
Test status
Simulation time	1808579364 ps
CPU time	14.49 seconds
Started	Aug 17 06:28:45 PM PDT 24
Finished	Aug 17 06:29:00 PM PDT 24
Peak memory	209652 kb
Host	smart-fb3d09cf-e303-4428-a141-4fd7a26be401
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390641571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.390641571
Directory	/workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2606073813
Short name	T979
Test name
Test status
Simulation time	46047686 ps
CPU time	1.25 seconds
Started	Aug 17 06:28:44 PM PDT 24
Finished	Aug 17 06:28:46 PM PDT 24
Peak memory	211400 kb
Host	smart-2b40758b-9335-41ce-b5f3-4e6a57283a5d
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606073813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2606073813
Directory	/workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3981948166
Short name	T982
Test name
Test status
Simulation time	140146278 ps
CPU time	4.34 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:46 PM PDT 24
Peak memory	219564 kb
Host	smart-85548abd-c5e2-445e-9be0-89a54f246975
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398194 8166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3981948166
Directory	/workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3573929177
Short name	T906
Test name
Test status
Simulation time	200607522 ps
CPU time	1.53 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:43 PM PDT 24
Peak memory	209700 kb
Host	smart-69165494-d51e-44e5-ac27-f117fd12e787
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573929177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_rw.3573929177
Directory	/workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1800117701
Short name	T954
Test name
Test status
Simulation time	157544201 ps
CPU time	1.28 seconds
Started	Aug 17 06:28:42 PM PDT 24
Finished	Aug 17 06:28:44 PM PDT 24
Peak memory	210020 kb
Host	smart-023f25c4-6e88-47a5-bf8c-e10bb66ad0d3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800117701 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1800117701
Directory	/workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2579900369
Short name	T972
Test name
Test status
Simulation time	42163077 ps
CPU time	1.09 seconds
Started	Aug 17 06:28:47 PM PDT 24
Finished	Aug 17 06:28:48 PM PDT 24
Peak memory	209972 kb
Host	smart-e2d237bd-82da-4606-a579-48fcbb77983c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579900369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl _same_csr_outstanding.2579900369
Directory	/workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2353428995
Short name	T936
Test name
Test status
Simulation time	273288086 ps
CPU time	3.32 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:44 PM PDT 24
Peak memory	218120 kb
Host	smart-d77e1a33-88cd-4276-879a-00e8af73571d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353428995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2353428995
Directory	/workspace/3.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.709600934
Short name	T874
Test name
Test status
Simulation time	127490354 ps
CPU time	1.22 seconds
Started	Aug 17 06:28:42 PM PDT 24
Finished	Aug 17 06:28:43 PM PDT 24
Peak memory	209948 kb
Host	smart-dc0378c7-cdae-4e94-83ef-286a5d4e6221
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709600934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing .709600934
Directory	/workspace/4.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.744046330
Short name	T957
Test name
Test status
Simulation time	355235130 ps
CPU time	1.86 seconds
Started	Aug 17 06:28:57 PM PDT 24
Finished	Aug 17 06:28:59 PM PDT 24
Peak memory	209204 kb
Host	smart-34220fc0-0bdc-49d8-9961-4d8148eab524
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744046330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash .744046330
Directory	/workspace/4.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.963583840
Short name	T997
Test name
Test status
Simulation time	129649148 ps
CPU time	0.99 seconds
Started	Aug 17 06:29:01 PM PDT 24
Finished	Aug 17 06:29:02 PM PDT 24
Peak memory	211964 kb
Host	smart-94b1e594-6f8b-4f41-9e77-bba8f56b82d5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963583840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset .963583840
Directory	/workspace/4.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.234907867
Short name	T894
Test name
Test status
Simulation time	28156914 ps
CPU time	1.19 seconds
Started	Aug 17 06:28:43 PM PDT 24
Finished	Aug 17 06:28:44 PM PDT 24
Peak memory	218368 kb
Host	smart-ed58b89e-adc3-432c-bf77-8aa3c9b453f1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234907867 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.234907867
Directory	/workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3509970604
Short name	T174
Test name
Test status
Simulation time	49061167 ps
CPU time	0.99 seconds
Started	Aug 17 06:28:43 PM PDT 24
Finished	Aug 17 06:28:44 PM PDT 24
Peak memory	209956 kb
Host	smart-efd76ca8-9bf3-4e7a-b325-29176016a35c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509970604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3509970604
Directory	/workspace/4.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.455168797
Short name	T981
Test name
Test status
Simulation time	432747412 ps
CPU time	1.71 seconds
Started	Aug 17 06:28:39 PM PDT 24
Finished	Aug 17 06:28:41 PM PDT 24
Peak memory	209808 kb
Host	smart-24a686c8-0814-4991-97d6-0d3c5357f111
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455168797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.lc_ctrl_jtag_alert_test.455168797
Directory	/workspace/4.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4247069378
Short name	T978
Test name
Test status
Simulation time	1465914164 ps
CPU time	16.51 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:58 PM PDT 24
Peak memory	208376 kb
Host	smart-9690c47e-9817-4a1f-bc85-8cf331b3cd53
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247069378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.4247069378
Directory	/workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3158645227
Short name	T938
Test name
Test status
Simulation time	4271836130 ps
CPU time	24.25 seconds
Started	Aug 17 06:28:49 PM PDT 24
Finished	Aug 17 06:29:14 PM PDT 24
Peak memory	209244 kb
Host	smart-a8a123fd-55b1-40ab-8241-b37df0dc6b47
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158645227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3158645227
Directory	/workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3829620650
Short name	T907
Test name
Test status
Simulation time	264989089 ps
CPU time	6.5 seconds
Started	Aug 17 06:28:36 PM PDT 24
Finished	Aug 17 06:28:43 PM PDT 24
Peak memory	211628 kb
Host	smart-58f687ba-2711-4983-a403-16804c58f6fe
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829620650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3829620650
Directory	/workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2134796828
Short name	T888
Test name
Test status
Simulation time	127526321 ps
CPU time	2.43 seconds
Started	Aug 17 06:28:45 PM PDT 24
Finished	Aug 17 06:28:48 PM PDT 24
Peak memory	219920 kb
Host	smart-2ec751f3-e463-4d72-865d-4a3d08517bee
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213479 6828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2134796828
Directory	/workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1761450440
Short name	T880
Test name
Test status
Simulation time	1061613383 ps
CPU time	1.25 seconds
Started	Aug 17 06:28:49 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	209780 kb
Host	smart-46dd0c24-901e-4767-af56-24b8f36cfa1c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761450440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_rw.1761450440
Directory	/workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.828836403
Short name	T905
Test name
Test status
Simulation time	92229771 ps
CPU time	1.09 seconds
Started	Aug 17 06:28:48 PM PDT 24
Finished	Aug 17 06:28:50 PM PDT 24
Peak memory	209980 kb
Host	smart-a2d7fb4d-cdf4-4ca3-9a10-37c5b7972e16
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828836403 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.828836403
Directory	/workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.517594459
Short name	T179
Test name
Test status
Simulation time	181492679 ps
CPU time	1.93 seconds
Started	Aug 17 06:28:51 PM PDT 24
Finished	Aug 17 06:28:54 PM PDT 24
Peak memory	210028 kb
Host	smart-9bf90b04-a074-45fe-be6c-27521d7ff083
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517594459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ same_csr_outstanding.517594459
Directory	/workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3009847224
Short name	T937
Test name
Test status
Simulation time	143231888 ps
CPU time	2.85 seconds
Started	Aug 17 06:28:57 PM PDT 24
Finished	Aug 17 06:29:00 PM PDT 24
Peak memory	218056 kb
Host	smart-5ca269f9-38fc-412b-ac39-5a3f9f758b70
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009847224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3009847224
Directory	/workspace/4.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3415825027
Short name	T964
Test name
Test status
Simulation time	131453361 ps
CPU time	1.19 seconds
Started	Aug 17 06:28:47 PM PDT 24
Finished	Aug 17 06:28:49 PM PDT 24
Peak memory	218588 kb
Host	smart-0159129d-e90a-4490-8f86-4527952bdaf9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415825027 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3415825027
Directory	/workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.4120606374
Short name	T984
Test name
Test status
Simulation time	32883536 ps
CPU time	0.84 seconds
Started	Aug 17 06:28:42 PM PDT 24
Finished	Aug 17 06:28:42 PM PDT 24
Peak memory	209620 kb
Host	smart-46411971-1096-432c-a813-5d6eca6684ea
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120606374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.4120606374
Directory	/workspace/5.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.233638576
Short name	T958
Test name
Test status
Simulation time	36687357 ps
CPU time	1.57 seconds
Started	Aug 17 06:28:49 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	208572 kb
Host	smart-c492d408-2031-426d-9be0-a5373078d8e2
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233638576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.lc_ctrl_jtag_alert_test.233638576
Directory	/workspace/5.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2037954971
Short name	T912
Test name
Test status
Simulation time	443501652 ps
CPU time	11 seconds
Started	Aug 17 06:28:57 PM PDT 24
Finished	Aug 17 06:29:08 PM PDT 24
Peak memory	209672 kb
Host	smart-ac0d278d-74d3-4bc2-a711-4b0ccdcdc8a1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037954971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2037954971
Directory	/workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2550955675
Short name	T930
Test name
Test status
Simulation time	965669850 ps
CPU time	11.69 seconds
Started	Aug 17 06:28:47 PM PDT 24
Finished	Aug 17 06:28:59 PM PDT 24
Peak memory	209792 kb
Host	smart-9b06296c-4787-490d-9b52-5960d2d1273a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550955675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2550955675
Directory	/workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.765493292
Short name	T913
Test name
Test status
Simulation time	153777334 ps
CPU time	1.7 seconds
Started	Aug 17 06:28:47 PM PDT 24
Finished	Aug 17 06:28:49 PM PDT 24
Peak memory	211460 kb
Host	smart-ea92a59d-fbea-4d83-826e-606a054a1821
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765493292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.765493292
Directory	/workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2275008057
Short name	T915
Test name
Test status
Simulation time	421019018 ps
CPU time	2.44 seconds
Started	Aug 17 06:29:02 PM PDT 24
Finished	Aug 17 06:29:04 PM PDT 24
Peak memory	219936 kb
Host	smart-8b492962-379e-4031-aa5b-759b0d0ca9ff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227500 8057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2275008057
Directory	/workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.537931564
Short name	T986
Test name
Test status
Simulation time	42618883 ps
CPU time	1.24 seconds
Started	Aug 17 06:28:47 PM PDT 24
Finished	Aug 17 06:28:49 PM PDT 24
Peak memory	209828 kb
Host	smart-d0a107b8-a92a-42da-84c0-2f219749dee9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537931564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_rw.537931564
Directory	/workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4143604788
Short name	T1001
Test name
Test status
Simulation time	41573489 ps
CPU time	0.94 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:41 PM PDT 24
Peak memory	209680 kb
Host	smart-11b8b2a5-f62e-4b75-8771-7d91c03eecac
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143604788 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.4143604788
Directory	/workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2159273601
Short name	T178
Test name
Test status
Simulation time	296428191 ps
CPU time	1.73 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:42 PM PDT 24
Peak memory	218148 kb
Host	smart-d4928a3b-9189-4846-afe9-074bdfab88d7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159273601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl _same_csr_outstanding.2159273601
Directory	/workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.957698964
Short name	T963
Test name
Test status
Simulation time	205604395 ps
CPU time	2.17 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:43 PM PDT 24
Peak memory	218052 kb
Host	smart-84a20fcc-b4b3-4d22-b66a-34d54ab42853
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957698964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.957698964
Directory	/workspace/5.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.963351675
Short name	T96
Test name
Test status
Simulation time	47800880 ps
CPU time	1.02 seconds
Started	Aug 17 06:28:43 PM PDT 24
Finished	Aug 17 06:28:49 PM PDT 24
Peak memory	218180 kb
Host	smart-f753ff3b-fbda-4d4f-92be-4bd50c85d4bc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963351675 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.963351675
Directory	/workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.96290727
Short name	T883
Test name
Test status
Simulation time	31399873 ps
CPU time	0.97 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	209944 kb
Host	smart-ebff71b2-b12c-429b-9062-e2f9478ecf7e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96290727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.96290727
Directory	/workspace/6.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2951131989
Short name	T898
Test name
Test status
Simulation time	30587454 ps
CPU time	0.98 seconds
Started	Aug 17 06:28:46 PM PDT 24
Finished	Aug 17 06:28:47 PM PDT 24
Peak memory	209816 kb
Host	smart-f5781e78-a2b2-430d-8eaf-9a0a1cc63aef
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951131989 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2951131989
Directory	/workspace/6.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2620581044
Short name	T990
Test name
Test status
Simulation time	2373159115 ps
CPU time	2.66 seconds
Started	Aug 17 06:28:42 PM PDT 24
Finished	Aug 17 06:28:45 PM PDT 24
Peak memory	208568 kb
Host	smart-9bced4ee-b2e7-46b6-a26f-0190ae15b788
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620581044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2620581044
Directory	/workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3500652652
Short name	T950
Test name
Test status
Simulation time	628582798 ps
CPU time	14.87 seconds
Started	Aug 17 06:29:05 PM PDT 24
Finished	Aug 17 06:29:20 PM PDT 24
Peak memory	209104 kb
Host	smart-8d13f611-17ca-4e6c-9dcd-c836a5a6adca
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500652652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3500652652
Directory	/workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.252548583
Short name	T962
Test name
Test status
Simulation time	210679991 ps
CPU time	5.27 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:56 PM PDT 24
Peak memory	211608 kb
Host	smart-d36b1b8b-783e-4d26-8c83-ce12d5550efd
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252548583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.252548583
Directory	/workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2576037729
Short name	T971
Test name
Test status
Simulation time	1224643430 ps
CPU time	3.06 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:44 PM PDT 24
Peak memory	218204 kb
Host	smart-66e2cb76-df56-48ef-87cc-fcdf9e0a12aa
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257603 7729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2576037729
Directory	/workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1541473845
Short name	T903
Test name
Test status
Simulation time	38435006 ps
CPU time	1.56 seconds
Started	Aug 17 06:28:46 PM PDT 24
Finished	Aug 17 06:28:47 PM PDT 24
Peak memory	209784 kb
Host	smart-997dffb3-c249-408e-8018-33dd5068bb45
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541473845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_rw.1541473845
Directory	/workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3052308457
Short name	T952
Test name
Test status
Simulation time	143161652 ps
CPU time	1.31 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:42 PM PDT 24
Peak memory	209920 kb
Host	smart-2dbd733c-01e6-4fc8-ac85-bc90e324cd0e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052308457 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3052308457
Directory	/workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4161175230
Short name	T101
Test name
Test status
Simulation time	161630130 ps
CPU time	1.79 seconds
Started	Aug 17 06:28:47 PM PDT 24
Finished	Aug 17 06:28:49 PM PDT 24
Peak memory	209948 kb
Host	smart-b669a1ac-1354-41de-8372-0d665820e80c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161175230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl _same_csr_outstanding.4161175230
Directory	/workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1381612425
Short name	T111
Test name
Test status
Simulation time	139614219 ps
CPU time	2.18 seconds
Started	Aug 17 06:29:03 PM PDT 24
Finished	Aug 17 06:29:05 PM PDT 24
Peak memory	218376 kb
Host	smart-1271e4ea-ce64-4515-bbb1-065334d8ed5d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381612425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1381612425
Directory	/workspace/6.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.504919707
Short name	T103
Test name
Test status
Simulation time	56761497 ps
CPU time	2.57 seconds
Started	Aug 17 06:28:51 PM PDT 24
Finished	Aug 17 06:28:53 PM PDT 24
Peak memory	218080 kb
Host	smart-52d7dcbb-58c4-4f17-b7c6-124d5fd3bfe8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504919707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e rr.504919707
Directory	/workspace/6.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.848989873
Short name	T976
Test name
Test status
Simulation time	54162939 ps
CPU time	1.16 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:42 PM PDT 24
Peak memory	222772 kb
Host	smart-221d1966-2885-47a9-a0d5-30ed3374714d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848989873 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.848989873
Directory	/workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1518289029
Short name	T893
Test name
Test status
Simulation time	22946493 ps
CPU time	0.97 seconds
Started	Aug 17 06:28:42 PM PDT 24
Finished	Aug 17 06:28:43 PM PDT 24
Peak memory	209596 kb
Host	smart-dc491078-3655-4b3f-96ef-396544314410
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518289029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1518289029
Directory	/workspace/7.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3760250589
Short name	T974
Test name
Test status
Simulation time	53344018 ps
CPU time	1.39 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	208584 kb
Host	smart-374a0987-5269-463a-9978-858c169ee32d
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760250589 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3760250589
Directory	/workspace/7.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1778612882
Short name	T901
Test name
Test status
Simulation time	191131307 ps
CPU time	2.66 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:53 PM PDT 24
Peak memory	209600 kb
Host	smart-84bb9350-e3a5-4b23-bb12-eebcf6d5c43b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778612882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1778612882
Directory	/workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.705384124
Short name	T968
Test name
Test status
Simulation time	916212533 ps
CPU time	11.34 seconds
Started	Aug 17 06:29:10 PM PDT 24
Finished	Aug 17 06:29:21 PM PDT 24
Peak memory	209728 kb
Host	smart-8a0d2244-b601-4a30-bcd8-07ba185c81fc
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705384124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.705384124
Directory	/workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.772741473
Short name	T908
Test name
Test status
Simulation time	109141465 ps
CPU time	1.71 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:43 PM PDT 24
Peak memory	211616 kb
Host	smart-f43d7d10-e0d9-4ea8-87bd-a1d63e2097ec
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772741473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.772741473
Directory	/workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2762444261
Short name	T959
Test name
Test status
Simulation time	277559215 ps
CPU time	2 seconds
Started	Aug 17 06:28:49 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	223992 kb
Host	smart-1dac319a-4714-4a96-90f6-07d350195bc7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276244 4261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2762444261
Directory	/workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2941450562
Short name	T128
Test name
Test status
Simulation time	151565312 ps
CPU time	2.41 seconds
Started	Aug 17 06:28:46 PM PDT 24
Finished	Aug 17 06:28:49 PM PDT 24
Peak memory	209760 kb
Host	smart-102348d7-04f8-4590-8899-09264f3a3e19
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941450562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_rw.2941450562
Directory	/workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.966262384
Short name	T182
Test name
Test status
Simulation time	68375043 ps
CPU time	1.32 seconds
Started	Aug 17 06:28:49 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	209960 kb
Host	smart-657cd1c9-a21e-49af-b692-ce8b45eb2150
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966262384 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.966262384
Directory	/workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2405779589
Short name	T944
Test name
Test status
Simulation time	202086606 ps
CPU time	1.81 seconds
Started	Aug 17 06:28:41 PM PDT 24
Finished	Aug 17 06:28:43 PM PDT 24
Peak memory	209692 kb
Host	smart-3d071da6-deeb-4217-bad5-43e89c2dab11
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405779589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl _same_csr_outstanding.2405779589
Directory	/workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3937215952
Short name	T114
Test name
Test status
Simulation time	70318720 ps
CPU time	2.24 seconds
Started	Aug 17 06:28:46 PM PDT 24
Finished	Aug 17 06:28:49 PM PDT 24
Peak memory	218156 kb
Host	smart-4cba6761-4954-4c77-983f-cac5060be010
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937215952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3937215952
Directory	/workspace/7.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.695153085
Short name	T138
Test name
Test status
Simulation time	20949783 ps
CPU time	1.1 seconds
Started	Aug 17 06:28:39 PM PDT 24
Finished	Aug 17 06:28:40 PM PDT 24
Peak memory	218076 kb
Host	smart-176843cc-dc12-4b6c-b9e5-5ba330c33ab9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695153085 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.695153085
Directory	/workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3549284275
Short name	T985
Test name
Test status
Simulation time	23422142 ps
CPU time	1.01 seconds
Started	Aug 17 06:28:44 PM PDT 24
Finished	Aug 17 06:28:45 PM PDT 24
Peak memory	209912 kb
Host	smart-2d8da8f2-6a33-4c8c-8a2c-88acc8b1bc5c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549284275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3549284275
Directory	/workspace/8.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.786532750
Short name	T876
Test name
Test status
Simulation time	384520459 ps
CPU time	0.93 seconds
Started	Aug 17 06:28:51 PM PDT 24
Finished	Aug 17 06:28:52 PM PDT 24
Peak memory	209816 kb
Host	smart-115ac1f2-1257-434a-ada6-de18498ea729
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786532750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.lc_ctrl_jtag_alert_test.786532750
Directory	/workspace/8.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2897622751
Short name	T126
Test name
Test status
Simulation time	800808896 ps
CPU time	7.23 seconds
Started	Aug 17 06:28:46 PM PDT 24
Finished	Aug 17 06:28:53 PM PDT 24
Peak memory	209104 kb
Host	smart-b86a1001-a466-4deb-adaf-1f3ea9d96dc8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897622751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2897622751
Directory	/workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3706339084
Short name	T918
Test name
Test status
Simulation time	3021633169 ps
CPU time	10.21 seconds
Started	Aug 17 06:29:25 PM PDT 24
Finished	Aug 17 06:29:35 PM PDT 24
Peak memory	209964 kb
Host	smart-681686cd-ba9a-4776-8b65-0c212e4df329
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706339084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3706339084
Directory	/workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3698021505
Short name	T895
Test name
Test status
Simulation time	130298128 ps
CPU time	1.72 seconds
Started	Aug 17 06:29:06 PM PDT 24
Finished	Aug 17 06:29:08 PM PDT 24
Peak memory	210980 kb
Host	smart-4f1678df-8a77-41b9-bb12-8758ea6dea8a
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698021505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.3698021505
Directory	/workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.367449542
Short name	T890
Test name
Test status
Simulation time	162144833 ps
CPU time	2.05 seconds
Started	Aug 17 06:28:45 PM PDT 24
Finished	Aug 17 06:28:47 PM PDT 24
Peak memory	219696 kb
Host	smart-284dd29e-3e64-4c6c-baa8-7af6c664567c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367449 542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.367449542
Directory	/workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.679056544
Short name	T923
Test name
Test status
Simulation time	272990530 ps
CPU time	3.2 seconds
Started	Aug 17 06:28:42 PM PDT 24
Finished	Aug 17 06:28:45 PM PDT 24
Peak memory	209780 kb
Host	smart-b853d749-1540-4471-95e4-255e63b418ed
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679056544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_rw.679056544
Directory	/workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2309561218
Short name	T977
Test name
Test status
Simulation time	337338533 ps
CPU time	1.35 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:42 PM PDT 24
Peak memory	211992 kb
Host	smart-1b981d37-a4b5-43b9-87c7-03c43ed324b3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309561218 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2309561218
Directory	/workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4146775736
Short name	T183
Test name
Test status
Simulation time	76444600 ps
CPU time	1.22 seconds
Started	Aug 17 06:28:40 PM PDT 24
Finished	Aug 17 06:28:42 PM PDT 24
Peak memory	209864 kb
Host	smart-6a7eeff1-6813-4058-b9c1-f83ead61f48d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146775736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _same_csr_outstanding.4146775736
Directory	/workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.113145631
Short name	T106
Test name
Test status
Simulation time	51434646 ps
CPU time	3.88 seconds
Started	Aug 17 06:28:49 PM PDT 24
Finished	Aug 17 06:28:53 PM PDT 24
Peak memory	218160 kb
Host	smart-a0abf42a-2354-4ae4-ad41-f7f5d6f76a4e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113145631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.113145631
Directory	/workspace/8.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3655563652
Short name	T119
Test name
Test status
Simulation time	112527396 ps
CPU time	4.14 seconds
Started	Aug 17 06:28:46 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	218120 kb
Host	smart-dc8622f6-02da-412d-bc0a-57ef43a0a75a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655563652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_ err.3655563652
Directory	/workspace/8.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1415793608
Short name	T156
Test name
Test status
Simulation time	32072083 ps
CPU time	1.29 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:52 PM PDT 24
Peak memory	218136 kb
Host	smart-d4b33ca5-dcda-40bd-9430-470bfeb0d67f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415793608 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1415793608
Directory	/workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1781144251
Short name	T175
Test name
Test status
Simulation time	15275247 ps
CPU time	1.07 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:51 PM PDT 24
Peak memory	209920 kb
Host	smart-56de7d89-7ae7-4968-b23e-9ce3d0d719b1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781144251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1781144251
Directory	/workspace/9.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.661656979
Short name	T909
Test name
Test status
Simulation time	145438977 ps
CPU time	1.11 seconds
Started	Aug 17 06:28:50 PM PDT 24
Finished	Aug 17 06:28:56 PM PDT 24
Peak memory	209828 kb
Host	smart-8c989a65-b867-4ed7-9f21-f719cf12f749
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661656979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.lc_ctrl_jtag_alert_test.661656979
Directory	/workspace/9.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2062559689
Short name	T884
Test name
Test status
Simulation time	19974712230 ps
CPU time	12.71 seconds
Started	Aug 17 06:28:49 PM PDT 24
Finished	Aug 17 06:29:02 PM PDT 24
Peak memory	208784 kb
Host	smart-d208669a-6879-4bbd-9fcd-4ca8a96de38b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062559689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2062559689
Directory	/workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1387088982
Short name	T891
Test name
Test status
Simulation time	4662714843 ps
CPU time	51.96 seconds
Started	Aug 17 06:28:51 PM PDT 24
Finished	Aug 17 06:29:43 PM PDT 24
Peak memory	209888 kb
Host	smart-3b0d26fe-d077-48da-97f2-a2fb0c1117c8
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387088982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1387088982
Directory	/workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.369957744
Short name	T911
Test name
Test status
Simulation time	53202570 ps
CPU time	1.94 seconds
Started	Aug 17 06:28:44 PM PDT 24
Finished	Aug 17 06:28:46 PM PDT 24
Peak memory	211380 kb
Host	smart-426ed3e9-a341-4e15-9ca1-a92d01e0840c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369957744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.369957744
Directory	/workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.733915103
Short name	T125
Test name
Test status
Simulation time	321686367 ps
CPU time	1.57 seconds
Started	Aug 17 06:28:52 PM PDT 24
Finished	Aug 17 06:28:53 PM PDT 24
Peak memory	219416 kb
Host	smart-0c817c66-c282-49f2-a40d-59d40b38a69a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733915 103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.733915103
Directory	/workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.238199896
Short name	T943
Test name
Test status
Simulation time	310084830 ps
CPU time	2.55 seconds
Started	Aug 17 06:28:44 PM PDT 24
Finished	Aug 17 06:28:47 PM PDT 24
Peak memory	209836 kb
Host	smart-3ec5a7a3-8edf-4be6-9cd7-e65791e2ce38
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238199896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_rw.238199896
Directory	/workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.748284067
Short name	T960
Test name
Test status
Simulation time	193161091 ps
CPU time	1.99 seconds
Started	Aug 17 06:28:55 PM PDT 24
Finished	Aug 17 06:28:57 PM PDT 24
Peak memory	218108 kb
Host	smart-4289cc79-6916-4b59-96a7-6ffabe4d8001
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748284067 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.748284067
Directory	/workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2179816676
Short name	T932
Test name
Test status
Simulation time	86018914 ps
CPU time	1.18 seconds
Started	Aug 17 06:28:42 PM PDT 24
Finished	Aug 17 06:28:44 PM PDT 24
Peak memory	210004 kb
Host	smart-2be07ebf-8a97-425a-b383-c29883225dc4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179816676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl _same_csr_outstanding.2179816676
Directory	/workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2209189665
Short name	T987
Test name
Test status
Simulation time	152106110 ps
CPU time	1.63 seconds
Started	Aug 17 06:28:44 PM PDT 24
Finished	Aug 17 06:28:46 PM PDT 24
Peak memory	218168 kb
Host	smart-fd10e4b5-da0e-4ca4-b1ef-96882efae99b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209189665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2209189665
Directory	/workspace/9.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.712584872
Short name	T123
Test name
Test status
Simulation time	287573697 ps
CPU time	3.42 seconds
Started	Aug 17 06:28:59 PM PDT 24
Finished	Aug 17 06:29:03 PM PDT 24
Peak memory	222852 kb
Host	smart-592583d3-e765-4ba5-8f86-d1ef5c028b14
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712584872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e rr.712584872
Directory	/workspace/9.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.lc_ctrl_alert_test.1877780977
Short name	T658
Test name
Test status
Simulation time	34893909 ps
CPU time	1.14 seconds
Started	Aug 17 06:31:31 PM PDT 24
Finished	Aug 17 06:31:32 PM PDT 24
Peak memory	208980 kb
Host	smart-709cf313-4241-43d4-a00b-cd35c00591b9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877780977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1877780977
Directory	/workspace/0.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.lc_ctrl_claim_transition_if.2607717516
Short name	T664
Test name
Test status
Simulation time	16600261 ps
CPU time	0.76 seconds
Started	Aug 17 06:31:43 PM PDT 24
Finished	Aug 17 06:31:44 PM PDT 24
Peak memory	208876 kb
Host	smart-c46afba0-62a5-4a72-a2e2-dcb2b1cfc629
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607717516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2607717516
Directory	/workspace/0.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/0.lc_ctrl_errors.2464348435
Short name	T207
Test name
Test status
Simulation time	780480659 ps
CPU time	9.77 seconds
Started	Aug 17 06:32:01 PM PDT 24
Finished	Aug 17 06:32:11 PM PDT 24
Peak memory	226092 kb
Host	smart-bcc48c09-8b66-4172-ab99-27565b517760
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2464348435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2464348435
Directory	/workspace/0.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_access.2711514703
Short name	T811
Test name
Test status
Simulation time	4065343209 ps
CPU time	19.22 seconds
Started	Aug 17 06:31:34 PM PDT 24
Finished	Aug 17 06:31:53 PM PDT 24
Peak memory	217636 kb
Host	smart-fa97e12d-451b-47da-b075-cc17b3ff20ce
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711514703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2711514703
Directory	/workspace/0.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_errors.3214679600
Short name	T800
Test name
Test status
Simulation time	8632586619 ps
CPU time	57.06 seconds
Started	Aug 17 06:31:50 PM PDT 24
Finished	Aug 17 06:32:47 PM PDT 24
Peak memory	218804 kb
Host	smart-3ae3a402-8933-400d-98f9-fa542f6989ca
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214679600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er rors.3214679600
Directory	/workspace/0.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_priority.1748057339
Short name	T25
Test name
Test status
Simulation time	910779780 ps
CPU time	5.47 seconds
Started	Aug 17 06:31:21 PM PDT 24
Finished	Aug 17 06:31:26 PM PDT 24
Peak memory	217516 kb
Host	smart-ef5c01b9-3ddf-4489-8c03-51a9aee924db
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748057339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1 748057339
Directory	/workspace/0.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1122432744
Short name	T157
Test name
Test status
Simulation time	295971712 ps
CPU time	3.62 seconds
Started	Aug 17 06:31:29 PM PDT 24
Finished	Aug 17 06:31:32 PM PDT 24
Peak memory	218292 kb
Host	smart-29c3941f-88c4-45e4-bcf0-0887b3375e27
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122432744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag _prog_failure.1122432744
Directory	/workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3292431729
Short name	T68
Test name
Test status
Simulation time	2038170204 ps
CPU time	16.66 seconds
Started	Aug 17 06:31:46 PM PDT 24
Finished	Aug 17 06:32:03 PM PDT 24
Peak memory	217548 kb
Host	smart-76830c28-40d8-4312-bec3-5432519412c4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292431729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_regwen_during_op.3292431729
Directory	/workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_smoke.3913672135
Short name	T696
Test name
Test status
Simulation time	306701061 ps
CPU time	4.98 seconds
Started	Aug 17 06:31:24 PM PDT 24
Finished	Aug 17 06:31:31 PM PDT 24
Peak memory	217728 kb
Host	smart-7d315267-7cd5-4653-b0e7-7a0091eeb32c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913672135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke. 3913672135
Directory	/workspace/0.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3725795273
Short name	T314
Test name
Test status
Simulation time	1343312102 ps
CPU time	63.35 seconds
Started	Aug 17 06:31:36 PM PDT 24
Finished	Aug 17 06:32:39 PM PDT 24
Peak memory	267192 kb
Host	smart-4a38de40-a741-44e1-b3a1-53707c78227d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725795273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta g_state_failure.3725795273
Directory	/workspace/0.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.4144594151
Short name	T486
Test name
Test status
Simulation time	795928689 ps
CPU time	14.62 seconds
Started	Aug 17 06:31:28 PM PDT 24
Finished	Aug 17 06:31:43 PM PDT 24
Peak memory	250800 kb
Host	smart-d76fd847-bca8-40f7-87c4-d0e75fbf0a1f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144594151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_state_post_trans.4144594151
Directory	/workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_prog_failure.1350724264
Short name	T748
Test name
Test status
Simulation time	65403052 ps
CPU time	2.53 seconds
Started	Aug 17 06:31:55 PM PDT 24
Finished	Aug 17 06:31:58 PM PDT 24
Peak memory	218252 kb
Host	smart-39d8131c-0516-4515-82b1-af81da3735a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1350724264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1350724264
Directory	/workspace/0.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_regwen_during_op.2282657304
Short name	T16
Test name
Test status
Simulation time	1435658335 ps
CPU time	14.73 seconds
Started	Aug 17 06:31:37 PM PDT 24
Finished	Aug 17 06:31:52 PM PDT 24
Peak memory	214828 kb
Host	smart-a94b40fa-505c-4391-be7c-ad8a5383c7fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282657304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2282657304
Directory	/workspace/0.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_mubi.3896832918
Short name	T413
Test name
Test status
Simulation time	1329243269 ps
CPU time	11.82 seconds
Started	Aug 17 06:31:23 PM PDT 24
Finished	Aug 17 06:31:36 PM PDT 24
Peak memory	218208 kb
Host	smart-bd22ee83-37ae-409c-90a1-a32c02f649ab
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896832918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3896832918
Directory	/workspace/0.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_digest.2977549005
Short name	T455
Test name
Test status
Simulation time	1430073659 ps
CPU time	10.22 seconds
Started	Aug 17 06:31:26 PM PDT 24
Finished	Aug 17 06:31:37 PM PDT 24
Peak memory	225784 kb
Host	smart-e9c80acf-959a-45ba-a2f6-97e189b0bf29
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977549005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di gest.2977549005
Directory	/workspace/0.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/0.lc_ctrl_sec_token_mux.3234525143
Short name	T318
Test name
Test status
Simulation time	171421917 ps
CPU time	6.81 seconds
Started	Aug 17 06:31:42 PM PDT 24
Finished	Aug 17 06:31:49 PM PDT 24
Peak memory	225048 kb
Host	smart-4809f9ff-dda1-40d9-93c6-e6877fe1642c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234525143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3 234525143
Directory	/workspace/0.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_failure.2267748575
Short name	T249
Test name
Test status
Simulation time	1254718977 ps
CPU time	26.08 seconds
Started	Aug 17 06:31:23 PM PDT 24
Finished	Aug 17 06:31:51 PM PDT 24
Peak memory	250904 kb
Host	smart-77d31d15-1c14-467e-894c-8bf3353e2964
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2267748575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2267748575
Directory	/workspace/0.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/0.lc_ctrl_state_post_trans.270253707
Short name	T331
Test name
Test status
Simulation time	81965770 ps
CPU time	3.13 seconds
Started	Aug 17 06:31:25 PM PDT 24
Finished	Aug 17 06:31:30 PM PDT 24
Peak memory	222360 kb
Host	smart-2b6c9442-df1f-48b6-8710-e8ec829ed5ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=270253707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.270253707
Directory	/workspace/0.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/0.lc_ctrl_stress_all.1804526578
Short name	T561
Test name
Test status
Simulation time	1481884875 ps
CPU time	50.8 seconds
Started	Aug 17 06:31:24 PM PDT 24
Finished	Aug 17 06:32:16 PM PDT 24
Peak memory	267388 kb
Host	smart-45c1f46c-660e-4a48-9be7-bffe8d48107b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804526578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all.1804526578
Directory	/workspace/0.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.85773762
Short name	T536
Test name
Test status
Simulation time	37282344 ps
CPU time	0.9 seconds
Started	Aug 17 06:31:22 PM PDT 24
Finished	Aug 17 06:31:23 PM PDT 24
Peak memory	211848 kb
Host	smart-46d22a63-4218-442a-bffe-560d7692ccea
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85773762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _volatile_unlock_smoke.85773762
Directory	/workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_alert_test.3659900518
Short name	T506
Test name
Test status
Simulation time	20029079 ps
CPU time	1.17 seconds
Started	Aug 17 06:31:24 PM PDT 24
Finished	Aug 17 06:31:27 PM PDT 24
Peak memory	208944 kb
Host	smart-02c26455-dfb4-4059-a919-83b237aba4fa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659900518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3659900518
Directory	/workspace/1.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.lc_ctrl_claim_transition_if.817306413
Short name	T577
Test name
Test status
Simulation time	11096552 ps
CPU time	0.8 seconds
Started	Aug 17 06:31:33 PM PDT 24
Finished	Aug 17 06:31:34 PM PDT 24
Peak memory	208540 kb
Host	smart-6d6a269d-1002-4c58-9dbb-045f070b2488
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=817306413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.817306413
Directory	/workspace/1.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/1.lc_ctrl_errors.623942081
Short name	T750
Test name
Test status
Simulation time	277879523 ps
CPU time	9.84 seconds
Started	Aug 17 06:32:01 PM PDT 24
Finished	Aug 17 06:32:11 PM PDT 24
Peak memory	226068 kb
Host	smart-37cbb0ab-58d9-4790-a864-0dc37f760643
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623942081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.623942081
Directory	/workspace/1.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_access.342200254
Short name	T639
Test name
Test status
Simulation time	882683014 ps
CPU time	4.25 seconds
Started	Aug 17 06:31:21 PM PDT 24
Finished	Aug 17 06:31:25 PM PDT 24
Peak memory	217144 kb
Host	smart-fdd9e904-219f-47b5-b4cd-7725fb7cdb94
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342200254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.342200254
Directory	/workspace/1.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_errors.2224967268
Short name	T661
Test name
Test status
Simulation time	19284121933 ps
CPU time	112.76 seconds
Started	Aug 17 06:31:31 PM PDT 24
Finished	Aug 17 06:33:24 PM PDT 24
Peak memory	219956 kb
Host	smart-06e541e8-af09-4662-990f-1b425985621b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224967268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er rors.2224967268
Directory	/workspace/1.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_priority.985406028
Short name	T400
Test name
Test status
Simulation time	2924944550 ps
CPU time	17.92 seconds
Started	Aug 17 06:31:22 PM PDT 24
Finished	Aug 17 06:31:50 PM PDT 24
Peak memory	217748 kb
Host	smart-3cd6105c-17ff-46b8-862c-0b154807183a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985406028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.985406028
Directory	/workspace/1.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2331560870
Short name	T709
Test name
Test status
Simulation time	225316568 ps
CPU time	3.96 seconds
Started	Aug 17 06:31:26 PM PDT 24
Finished	Aug 17 06:31:31 PM PDT 24
Peak memory	218172 kb
Host	smart-060f2b7a-61ba-447f-acae-60ccc318bf59
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331560870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag _prog_failure.2331560870
Directory	/workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2889227040
Short name	T514
Test name
Test status
Simulation time	2222505475 ps
CPU time	14.91 seconds
Started	Aug 17 06:31:25 PM PDT 24
Finished	Aug 17 06:31:41 PM PDT 24
Peak memory	217608 kb
Host	smart-7eb8cd60-1647-42fa-94d6-8c0a6b0c9858
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889227040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_regwen_during_op.2889227040
Directory	/workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_smoke.395710389
Short name	T495
Test name
Test status
Simulation time	322801695 ps
CPU time	4.86 seconds
Started	Aug 17 06:31:26 PM PDT 24
Finished	Aug 17 06:31:32 PM PDT 24
Peak memory	217548 kb
Host	smart-6b3a1d0f-4df1-485b-8bc1-d9478afa69a1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395710389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.395710389
Directory	/workspace/1.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3012943770
Short name	T307
Test name
Test status
Simulation time	1667733560 ps
CPU time	35.48 seconds
Started	Aug 17 06:31:26 PM PDT 24
Finished	Aug 17 06:32:03 PM PDT 24
Peak memory	250796 kb
Host	smart-8153d705-e1a3-4966-9b83-9f3b9de3d52f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012943770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta g_state_failure.3012943770
Directory	/workspace/1.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2353079912
Short name	T735
Test name
Test status
Simulation time	2628774866 ps
CPU time	10.67 seconds
Started	Aug 17 06:31:36 PM PDT 24
Finished	Aug 17 06:31:47 PM PDT 24
Peak memory	246420 kb
Host	smart-8e84a5c3-d3e3-4c28-9842-e119c53bdca6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353079912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_ jtag_state_post_trans.2353079912
Directory	/workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_prog_failure.1954287508
Short name	T273
Test name
Test status
Simulation time	255473814 ps
CPU time	2.79 seconds
Started	Aug 17 06:31:37 PM PDT 24
Finished	Aug 17 06:31:40 PM PDT 24
Peak memory	218264 kb
Host	smart-f4c2dbe8-9f37-4cd5-946b-355d7230990d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954287508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1954287508
Directory	/workspace/1.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_regwen_during_op.1511566158
Short name	T405
Test name
Test status
Simulation time	349381251 ps
CPU time	14.48 seconds
Started	Aug 17 06:31:29 PM PDT 24
Finished	Aug 17 06:31:43 PM PDT 24
Peak memory	217628 kb
Host	smart-493fa41a-6f72-4389-b993-5ba442e3d729
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1511566158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1511566158
Directory	/workspace/1.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_cm.4230724644
Short name	T1
Test name
Test status
Simulation time	209865480 ps
CPU time	22.12 seconds
Started	Aug 17 06:31:22 PM PDT 24
Finished	Aug 17 06:31:45 PM PDT 24
Peak memory	268300 kb
Host	smart-4b6c237a-7985-4eda-95af-43e30288643e
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230724644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4230724644
Directory	/workspace/1.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_mubi.3425865143
Short name	T466
Test name
Test status
Simulation time	283642818 ps
CPU time	11.12 seconds
Started	Aug 17 06:31:32 PM PDT 24
Finished	Aug 17 06:31:44 PM PDT 24
Peak memory	226048 kb
Host	smart-8237e5c8-578b-4403-8166-cffa22625c56
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425865143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3425865143
Directory	/workspace/1.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_digest.778171464
Short name	T657
Test name
Test status
Simulation time	9306192447 ps
CPU time	17.7 seconds
Started	Aug 17 06:31:45 PM PDT 24
Finished	Aug 17 06:32:03 PM PDT 24
Peak memory	226024 kb
Host	smart-c2c6e497-e58c-4fa7-b152-8225b4d99a12
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778171464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig est.778171464
Directory	/workspace/1.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/1.lc_ctrl_sec_token_mux.2800182444
Short name	T587
Test name
Test status
Simulation time	2134037033 ps
CPU time	10.25 seconds
Started	Aug 17 06:31:52 PM PDT 24
Finished	Aug 17 06:32:02 PM PDT 24
Peak memory	218220 kb
Host	smart-968cb2bb-a954-42ae-8889-4c10abbf766b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800182444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2 800182444
Directory	/workspace/1.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/1.lc_ctrl_security_escalation.1766592570
Short name	T325
Test name
Test status
Simulation time	372478853 ps
CPU time	8.7 seconds
Started	Aug 17 06:31:41 PM PDT 24
Finished	Aug 17 06:31:49 PM PDT 24
Peak memory	226088 kb
Host	smart-cdec7b0a-e682-4754-8d7e-2dd49497f74e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1766592570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1766592570
Directory	/workspace/1.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/1.lc_ctrl_smoke.2030267378
Short name	T269
Test name
Test status
Simulation time	32813826 ps
CPU time	1.18 seconds
Started	Aug 17 06:31:34 PM PDT 24
Finished	Aug 17 06:31:36 PM PDT 24
Peak memory	217540 kb
Host	smart-e6a4019d-e25e-4964-94f3-16fc510152da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2030267378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2030267378
Directory	/workspace/1.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_failure.3679563053
Short name	T434
Test name
Test status
Simulation time	244356284 ps
CPU time	25.05 seconds
Started	Aug 17 06:32:11 PM PDT 24
Finished	Aug 17 06:32:36 PM PDT 24
Peak memory	250896 kb
Host	smart-59bf5b3f-73af-4e0c-b0a9-875feeb5d3c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679563053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3679563053
Directory	/workspace/1.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/1.lc_ctrl_state_post_trans.597960563
Short name	T723
Test name
Test status
Simulation time	71773965 ps
CPU time	8.75 seconds
Started	Aug 17 06:31:40 PM PDT 24
Finished	Aug 17 06:31:49 PM PDT 24
Peak memory	250900 kb
Host	smart-5d959738-e086-436f-bc21-75a4248930a7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=597960563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.597960563
Directory	/workspace/1.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2689756640
Short name	T377
Test name
Test status
Simulation time	32262453 ps
CPU time	1.15 seconds
Started	Aug 17 06:32:13 PM PDT 24
Finished	Aug 17 06:32:14 PM PDT 24
Peak memory	217692 kb
Host	smart-eec4b55c-ac2c-4c25-a5da-e121b020ab71
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689756640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct rl_volatile_unlock_smoke.2689756640
Directory	/workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_alert_test.4018954266
Short name	T72
Test name
Test status
Simulation time	65548890 ps
CPU time	0.89 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	208820 kb
Host	smart-56c82647-c426-4e21-bed2-070aaf4b4971
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018954266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.4018954266
Directory	/workspace/10.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.lc_ctrl_errors.1050724626
Short name	T446
Test name
Test status
Simulation time	630198357 ps
CPU time	15.39 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:34 PM PDT 24
Peak memory	218280 kb
Host	smart-1a76e2ba-ca30-4379-b678-e6f478c49179
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050724626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1050724626
Directory	/workspace/10.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_access.2505077959
Short name	T855
Test name
Test status
Simulation time	1751201026 ps
CPU time	6.33 seconds
Started	Aug 17 06:32:06 PM PDT 24
Finished	Aug 17 06:32:12 PM PDT 24
Peak memory	217276 kb
Host	smart-7729109d-e3a5-4134-ae84-a0c4f382ae8e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505077959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2505077959
Directory	/workspace/10.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_errors.4145958392
Short name	T457
Test name
Test status
Simulation time	3212545517 ps
CPU time	83.92 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:33:41 PM PDT 24
Peak memory	218176 kb
Host	smart-ce7c97dc-cdf1-4f78-a836-3bd5dca8a592
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145958392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e rrors.4145958392
Directory	/workspace/10.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.3795650919
Short name	T777
Test name
Test status
Simulation time	283127373 ps
CPU time	5.43 seconds
Started	Aug 17 06:32:00 PM PDT 24
Finished	Aug 17 06:32:05 PM PDT 24
Peak memory	218148 kb
Host	smart-94893e1d-6f8a-428e-af45-57cf6665123a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795650919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta g_prog_failure.3795650919
Directory	/workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_smoke.3113904815
Short name	T82
Test name
Test status
Simulation time	117348046 ps
CPU time	4.07 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	217524 kb
Host	smart-34909530-97be-4c0b-864e-b93bfe5acaff
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113904815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke .3113904815
Directory	/workspace/10.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3802298991
Short name	T5
Test name
Test status
Simulation time	1322082633 ps
CPU time	61.27 seconds
Started	Aug 17 06:32:11 PM PDT 24
Finished	Aug 17 06:33:13 PM PDT 24
Peak memory	267192 kb
Host	smart-eb9131b3-4af1-4dfb-b8fa-e61723d6ae6e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802298991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt ag_state_failure.3802298991
Directory	/workspace/10.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2302146554
Short name	T677
Test name
Test status
Simulation time	2852864444 ps
CPU time	11.86 seconds
Started	Aug 17 06:32:09 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	224180 kb
Host	smart-40eeacf0-981b-4f0b-91b2-e14c52353656
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302146554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl _jtag_state_post_trans.2302146554
Directory	/workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/10.lc_ctrl_prog_failure.3470553359
Short name	T464
Test name
Test status
Simulation time	813463635 ps
CPU time	3.96 seconds
Started	Aug 17 06:32:12 PM PDT 24
Finished	Aug 17 06:32:16 PM PDT 24
Peak memory	222836 kb
Host	smart-5633367c-7093-42c5-9d03-4fa3f9be4c07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470553359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3470553359
Directory	/workspace/10.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_mubi.4183625493
Short name	T756
Test name
Test status
Simulation time	304856697 ps
CPU time	13.99 seconds
Started	Aug 17 06:32:10 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	226056 kb
Host	smart-03b8e3bb-723e-40d1-830e-e762520e6c16
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183625493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.4183625493
Directory	/workspace/10.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_digest.2980346103
Short name	T599
Test name
Test status
Simulation time	1013533608 ps
CPU time	7.65 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:32:25 PM PDT 24
Peak memory	225924 kb
Host	smart-1e9660dd-38f7-4fe7-9aca-28e9141e7c04
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980346103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d igest.2980346103
Directory	/workspace/10.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/10.lc_ctrl_sec_token_mux.1867340727
Short name	T621
Test name
Test status
Simulation time	1434152362 ps
CPU time	8.94 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:28 PM PDT 24
Peak memory	226024 kb
Host	smart-c9fd0ed9-dcf5-4d6f-92cb-d56b73c2dfa8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867340727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux. 1867340727
Directory	/workspace/10.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/10.lc_ctrl_security_escalation.4036225650
Short name	T51
Test name
Test status
Simulation time	182088010 ps
CPU time	6.57 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:28 PM PDT 24
Peak memory	225012 kb
Host	smart-bd092f4b-fea9-48bd-a6c4-5f2ec1874d0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036225650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.4036225650
Directory	/workspace/10.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/10.lc_ctrl_smoke.1638553087
Short name	T63
Test name
Test status
Simulation time	165928141 ps
CPU time	3.56 seconds
Started	Aug 17 06:32:09 PM PDT 24
Finished	Aug 17 06:32:13 PM PDT 24
Peak memory	217608 kb
Host	smart-5bae1732-e938-450b-aa7b-49e520dcbb38
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638553087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1638553087
Directory	/workspace/10.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.lc_ctrl_state_failure.781994304
Short name	T782
Test name
Test status
Simulation time	354334454 ps
CPU time	29.32 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:49 PM PDT 24
Peak memory	250876 kb
Host	smart-bdf872e0-e27d-473b-835b-2264af1e27c1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=781994304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.781994304
Directory	/workspace/10.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/10.lc_ctrl_stress_all.4268601779
Short name	T285
Test name
Test status
Simulation time	13605543445 ps
CPU time	76.86 seconds
Started	Aug 17 06:32:14 PM PDT 24
Finished	Aug 17 06:33:31 PM PDT 24
Peak memory	276816 kb
Host	smart-7719cc1e-5073-45a2-b336-4e6ff1fe14e0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268601779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all.4268601779
Directory	/workspace/10.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1347102684
Short name	T651
Test name
Test status
Simulation time	14552098 ps
CPU time	0.93 seconds
Started	Aug 17 06:32:13 PM PDT 24
Finished	Aug 17 06:32:14 PM PDT 24
Peak memory	212884 kb
Host	smart-34c8fefe-10cb-49eb-92ab-8ac1721a5ae1
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347102684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c trl_volatile_unlock_smoke.1347102684
Directory	/workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_alert_test.2632372521
Short name	T783
Test name
Test status
Simulation time	35143543 ps
CPU time	1.05 seconds
Started	Aug 17 06:32:16 PM PDT 24
Finished	Aug 17 06:32:17 PM PDT 24
Peak memory	208888 kb
Host	smart-f02f2cb7-23d9-4ea3-bdd3-ee1997300bdc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632372521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2632372521
Directory	/workspace/11.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.lc_ctrl_errors.2870245027
Short name	T746
Test name
Test status
Simulation time	3689010790 ps
CPU time	17.65 seconds
Started	Aug 17 06:32:01 PM PDT 24
Finished	Aug 17 06:32:19 PM PDT 24
Peak memory	218980 kb
Host	smart-93bd76d2-4315-4621-b042-ce1471924a04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2870245027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2870245027
Directory	/workspace/11.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_access.3477714915
Short name	T36
Test name
Test status
Simulation time	195842558 ps
CPU time	5.84 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:27 PM PDT 24
Peak memory	217000 kb
Host	smart-0a97bc59-2786-43c5-bb77-16590483a8ce
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477714915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3477714915
Directory	/workspace/11.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_errors.3786069201
Short name	T248
Test name
Test status
Simulation time	1657087804 ps
CPU time	49.65 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:33:09 PM PDT 24
Peak memory	218212 kb
Host	smart-08cf2c53-047a-4bbe-b1e3-a876c6938aeb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786069201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e rrors.3786069201
Directory	/workspace/11.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.4069151050
Short name	T345
Test name
Test status
Simulation time	817808737 ps
CPU time	3.39 seconds
Started	Aug 17 06:32:09 PM PDT 24
Finished	Aug 17 06:32:12 PM PDT 24
Peak memory	218212 kb
Host	smart-501ff206-7b6f-42c2-893f-3cbee2ea6b70
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069151050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta g_prog_failure.4069151050
Directory	/workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_smoke.3816649589
Short name	T354
Test name
Test status
Simulation time	996454868 ps
CPU time	8.07 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	217580 kb
Host	smart-c3d4df42-3d0d-4351-a229-3887ab724376
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816649589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke .3816649589
Directory	/workspace/11.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3919325528
Short name	T729
Test name
Test status
Simulation time	8638614043 ps
CPU time	79.11 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:33:41 PM PDT 24
Peak memory	267244 kb
Host	smart-cdcda11e-d201-4c35-aad2-34de2ae6ba63
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919325528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt ag_state_failure.3919325528
Directory	/workspace/11.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1366477466
Short name	T206
Test name
Test status
Simulation time	1863428591 ps
CPU time	12.74 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:35 PM PDT 24
Peak memory	223364 kb
Host	smart-d2e76e67-110f-4461-9364-3ec8f814d531
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366477466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl _jtag_state_post_trans.1366477466
Directory	/workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_prog_failure.1196077089
Short name	T665
Test name
Test status
Simulation time	18871337 ps
CPU time	1.69 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:23 PM PDT 24
Peak memory	221688 kb
Host	smart-f7222a49-706c-468d-a31a-7179653972c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1196077089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1196077089
Directory	/workspace/11.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_mubi.3986388583
Short name	T548
Test name
Test status
Simulation time	336868264 ps
CPU time	14.63 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:32:32 PM PDT 24
Peak memory	225940 kb
Host	smart-c45d8347-96cd-422f-8948-bd8df064b21f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986388583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.3986388583
Directory	/workspace/11.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_digest.4238031484
Short name	T630
Test name
Test status
Simulation time	420004035 ps
CPU time	7.17 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:27 PM PDT 24
Peak memory	225968 kb
Host	smart-6146ae01-f4fe-452e-856d-2b925c924b51
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238031484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d igest.4238031484
Directory	/workspace/11.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/11.lc_ctrl_sec_token_mux.782236020
Short name	T727
Test name
Test status
Simulation time	326678473 ps
CPU time	11.83 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:35 PM PDT 24
Peak memory	218220 kb
Host	smart-71d18ffa-1d3b-4257-a957-0ff2cc1f44d4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782236020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.782236020
Directory	/workspace/11.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/11.lc_ctrl_security_escalation.1182178219
Short name	T445
Test name
Test status
Simulation time	847422358 ps
CPU time	9.26 seconds
Started	Aug 17 06:32:12 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	224740 kb
Host	smart-601a6705-40e0-40da-b2ee-0ee65bf224e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1182178219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1182178219
Directory	/workspace/11.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/11.lc_ctrl_smoke.2664430828
Short name	T66
Test name
Test status
Simulation time	322006928 ps
CPU time	1.73 seconds
Started	Aug 17 06:32:15 PM PDT 24
Finished	Aug 17 06:32:17 PM PDT 24
Peak memory	213856 kb
Host	smart-ed14aa76-adaa-4342-8945-73324113dce9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2664430828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2664430828
Directory	/workspace/11.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_failure.2129309668
Short name	T823
Test name
Test status
Simulation time	1218752116 ps
CPU time	25.83 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:49 PM PDT 24
Peak memory	246352 kb
Host	smart-823a0a28-456a-4b66-8166-248646978e04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2129309668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2129309668
Directory	/workspace/11.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/11.lc_ctrl_state_post_trans.1320181163
Short name	T849
Test name
Test status
Simulation time	167297150 ps
CPU time	8.64 seconds
Started	Aug 17 06:32:09 PM PDT 24
Finished	Aug 17 06:32:18 PM PDT 24
Peak memory	250920 kb
Host	smart-c5807ad2-99d2-477c-817f-d6c937bf8fdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320181163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1320181163
Directory	/workspace/11.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all.3175883668
Short name	T814
Test name
Test status
Simulation time	14142053069 ps
CPU time	92.84 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:33:50 PM PDT 24
Peak memory	268496 kb
Host	smart-f55382f8-d1e7-41e6-9463-4c0e3969aca0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175883668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all.3175883668
Directory	/workspace/11.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2685398300
Short name	T137
Test name
Test status
Simulation time	9519797654 ps
CPU time	73.27 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:33:33 PM PDT 24
Peak memory	250620 kb
Host	smart-bb4d4467-ee86-4040-98ed-79698d456491
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2685398300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.2685398300
Directory	/workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1204067141
Short name	T417
Test name
Test status
Simulation time	14321331 ps
CPU time	1.04 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:20 PM PDT 24
Peak memory	211808 kb
Host	smart-d071a26f-2fc7-496c-817b-fe98d5584c9e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204067141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c trl_volatile_unlock_smoke.1204067141
Directory	/workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_alert_test.601957901
Short name	T416
Test name
Test status
Simulation time	24353644 ps
CPU time	1.24 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:23 PM PDT 24
Peak memory	209024 kb
Host	smart-db0a6903-9158-43df-ba17-814ac251eedb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601957901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.601957901
Directory	/workspace/12.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.lc_ctrl_errors.821967515
Short name	T755
Test name
Test status
Simulation time	244702020 ps
CPU time	10.07 seconds
Started	Aug 17 06:32:36 PM PDT 24
Finished	Aug 17 06:32:46 PM PDT 24
Peak memory	218240 kb
Host	smart-09b2c387-e64e-4a0e-a891-1e8072248f93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=821967515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.821967515
Directory	/workspace/12.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_access.4079716010
Short name	T715
Test name
Test status
Simulation time	269063462 ps
CPU time	4.31 seconds
Started	Aug 17 06:32:39 PM PDT 24
Finished	Aug 17 06:32:43 PM PDT 24
Peak memory	217172 kb
Host	smart-7a76a3d0-e397-43ba-af3e-bf4d169665d1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079716010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.4079716010
Directory	/workspace/12.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2124371639
Short name	T397
Test name
Test status
Simulation time	827755559 ps
CPU time	4.08 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:25 PM PDT 24
Peak memory	218228 kb
Host	smart-40eb6f94-39db-400f-a9c0-36051bda1f44
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124371639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta g_prog_failure.2124371639
Directory	/workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_smoke.1871672162
Short name	T259
Test name
Test status
Simulation time	1373353906 ps
CPU time	4.5 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	217564 kb
Host	smart-4696b203-51a4-4bef-8c85-aa2501583e9d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871672162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke .1871672162
Directory	/workspace/12.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_failure.53370578
Short name	T430
Test name
Test status
Simulation time	3474578619 ps
CPU time	70.25 seconds
Started	Aug 17 06:32:32 PM PDT 24
Finished	Aug 17 06:33:42 PM PDT 24
Peak memory	283488 kb
Host	smart-e82d7ca5-9567-4605-8d27-4fb1fa715fcb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53370578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag _state_failure.53370578
Directory	/workspace/12.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1610413511
Short name	T860
Test name
Test status
Simulation time	2540418335 ps
CPU time	13.49 seconds
Started	Aug 17 06:32:25 PM PDT 24
Finished	Aug 17 06:32:43 PM PDT 24
Peak memory	250856 kb
Host	smart-9c38e6c0-19d2-43d3-a09d-14d03d059dda
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610413511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl _jtag_state_post_trans.1610413511
Directory	/workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_prog_failure.1431591595
Short name	T614
Test name
Test status
Simulation time	76737837 ps
CPU time	3.96 seconds
Started	Aug 17 06:32:12 PM PDT 24
Finished	Aug 17 06:32:16 PM PDT 24
Peak memory	218276 kb
Host	smart-19070861-42d6-4893-b718-d4c9d8f93706
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431591595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1431591595
Directory	/workspace/12.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_mubi.1581048042
Short name	T698
Test name
Test status
Simulation time	864788994 ps
CPU time	11.84 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:33 PM PDT 24
Peak memory	225648 kb
Host	smart-551dc24d-b0d0-4731-ac3e-4b1111d36dfd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581048042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1581048042
Directory	/workspace/12.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_digest.856579619
Short name	T544
Test name
Test status
Simulation time	197824580 ps
CPU time	9.01 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:31 PM PDT 24
Peak memory	225376 kb
Host	smart-44950e67-b312-4ace-a21c-0e0f76f2fa8c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856579619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di gest.856579619
Directory	/workspace/12.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/12.lc_ctrl_sec_token_mux.3935316617
Short name	T602
Test name
Test status
Simulation time	868307040 ps
CPU time	8.76 seconds
Started	Aug 17 06:32:34 PM PDT 24
Finished	Aug 17 06:32:42 PM PDT 24
Peak memory	218276 kb
Host	smart-4f237942-6780-48d3-a430-3610c624602d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935316617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux. 3935316617
Directory	/workspace/12.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/12.lc_ctrl_security_escalation.178928271
Short name	T827
Test name
Test status
Simulation time	1447370604 ps
CPU time	13.79 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:32:31 PM PDT 24
Peak memory	225132 kb
Host	smart-ef7eeab8-e29d-4229-a975-1673d272c030
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=178928271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.178928271
Directory	/workspace/12.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/12.lc_ctrl_smoke.2847727525
Short name	T819
Test name
Test status
Simulation time	172531790 ps
CPU time	2.1 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	217732 kb
Host	smart-35c9bc96-2504-4dc7-84dc-6d38ace54e61
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847727525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2847727525
Directory	/workspace/12.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_failure.2611680692
Short name	T88
Test name
Test status
Simulation time	172488264 ps
CPU time	24.93 seconds
Started	Aug 17 06:32:14 PM PDT 24
Finished	Aug 17 06:32:39 PM PDT 24
Peak memory	250916 kb
Host	smart-c764afde-a933-4fbd-83e3-8518b1e3fbaf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2611680692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2611680692
Directory	/workspace/12.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/12.lc_ctrl_state_post_trans.3558001989
Short name	T419
Test name
Test status
Simulation time	306449856 ps
CPU time	6.16 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:29 PM PDT 24
Peak memory	246932 kb
Host	smart-d1b9b9e9-dbc2-4c6e-b9bb-721afdea38bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3558001989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3558001989
Directory	/workspace/12.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/12.lc_ctrl_stress_all.719542905
Short name	T480
Test name
Test status
Simulation time	9267307972 ps
CPU time	203.63 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:35:44 PM PDT 24
Peak memory	264000 kb
Host	smart-51b7d3db-727f-4a91-aead-9b752099d6c8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719542905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all.719542905
Directory	/workspace/12.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4177176618
Short name	T379
Test name
Test status
Simulation time	31890258 ps
CPU time	0.88 seconds
Started	Aug 17 06:32:11 PM PDT 24
Finished	Aug 17 06:32:12 PM PDT 24
Peak memory	211992 kb
Host	smart-c56cf8a3-9345-447c-86fb-94c9847c99b6
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177176618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c trl_volatile_unlock_smoke.4177176618
Directory	/workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_alert_test.3120424146
Short name	T142
Test name
Test status
Simulation time	18121841 ps
CPU time	0.91 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	208760 kb
Host	smart-e3e9f21b-fd60-4d7e-b842-ed8a291f5478
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120424146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3120424146
Directory	/workspace/13.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.lc_ctrl_errors.1886633
Short name	T616
Test name
Test status
Simulation time	401859045 ps
CPU time	16.56 seconds
Started	Aug 17 06:32:38 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	218244 kb
Host	smart-6832ea6d-2701-463a-b294-25bc4fb6ccb8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1886633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1886633
Directory	/workspace/13.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_access.1218161384
Short name	T568
Test name
Test status
Simulation time	3936083090 ps
CPU time	10.38 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:32:28 PM PDT 24
Peak memory	217604 kb
Host	smart-a6fa7805-9012-428c-8340-9f39e771e68a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218161384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1218161384
Directory	/workspace/13.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_errors.384592795
Short name	T585
Test name
Test status
Simulation time	1077702204 ps
CPU time	20.98 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:41 PM PDT 24
Peak memory	218184 kb
Host	smart-eec6e627-8455-4927-ba37-d532c92ed902
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384592795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er rors.384592795
Directory	/workspace/13.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1615844004
Short name	T732
Test name
Test status
Simulation time	4264787744 ps
CPU time	8.4 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:28 PM PDT 24
Peak memory	218280 kb
Host	smart-a09c4131-d00d-438e-82a9-70a1b2de86bd
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615844004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta g_prog_failure.1615844004
Directory	/workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_smoke.1279851709
Short name	T268
Test name
Test status
Simulation time	2265694898 ps
CPU time	6.43 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:29 PM PDT 24
Peak memory	217784 kb
Host	smart-acd44512-d5ad-40ad-8d76-3f085cf31be4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279851709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke .1279851709
Directory	/workspace/13.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_failure.545878360
Short name	T619
Test name
Test status
Simulation time	5759090093 ps
CPU time	69.87 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:33:29 PM PDT 24
Peak memory	276864 kb
Host	smart-e35af291-1b4d-4063-a23f-4515886a78ba
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545878360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta g_state_failure.545878360
Directory	/workspace/13.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.215594333
Short name	T622
Test name
Test status
Simulation time	579239346 ps
CPU time	18.69 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:38 PM PDT 24
Peak memory	251004 kb
Host	smart-eb1209e2-9092-4088-939f-9e4d11743d1d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215594333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_ jtag_state_post_trans.215594333
Directory	/workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_prog_failure.3881099078
Short name	T842
Test name
Test status
Simulation time	53627375 ps
CPU time	2.36 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	222436 kb
Host	smart-e2764c1f-2143-4483-9eb3-27614c69c0f0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881099078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3881099078
Directory	/workspace/13.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_mubi.2222829753
Short name	T200
Test name
Test status
Simulation time	874525681 ps
CPU time	8.62 seconds
Started	Aug 17 06:32:14 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	218276 kb
Host	smart-ffa2be96-0691-4e22-82ac-3ccac6e0d83a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222829753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2222829753
Directory	/workspace/13.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_digest.1619230400
Short name	T830
Test name
Test status
Simulation time	1129547848 ps
CPU time	11.84 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:31 PM PDT 24
Peak memory	226020 kb
Host	smart-958b4e05-48c2-4353-bd94-90f878bc0b57
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619230400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d igest.1619230400
Directory	/workspace/13.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/13.lc_ctrl_sec_token_mux.4160671800
Short name	T532
Test name
Test status
Simulation time	253068827 ps
CPU time	6.83 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:28 PM PDT 24
Peak memory	218340 kb
Host	smart-a7747772-fb2d-4007-ad38-2028a639fd51
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160671800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux. 4160671800
Directory	/workspace/13.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/13.lc_ctrl_security_escalation.2477758601
Short name	T808
Test name
Test status
Simulation time	492586672 ps
CPU time	8.95 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:30 PM PDT 24
Peak memory	225996 kb
Host	smart-32dd742e-c0df-4839-a266-27e27597d003
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2477758601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2477758601
Directory	/workspace/13.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/13.lc_ctrl_smoke.1416625901
Short name	T60
Test name
Test status
Simulation time	202868543 ps
CPU time	3.06 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:23 PM PDT 24
Peak memory	217596 kb
Host	smart-e85b793f-ded8-40f1-8ce9-4e731b0c6e30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1416625901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1416625901
Directory	/workspace/13.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_failure.127561320
Short name	T356
Test name
Test status
Simulation time	1058576379 ps
CPU time	33.91 seconds
Started	Aug 17 06:32:13 PM PDT 24
Finished	Aug 17 06:32:47 PM PDT 24
Peak memory	249448 kb
Host	smart-5ebe8829-3a92-469a-8802-044ed21f4917
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=127561320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.127561320
Directory	/workspace/13.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/13.lc_ctrl_state_post_trans.3903684458
Short name	T366
Test name
Test status
Simulation time	151222451 ps
CPU time	6.61 seconds
Started	Aug 17 06:32:13 PM PDT 24
Finished	Aug 17 06:32:20 PM PDT 24
Peak memory	246752 kb
Host	smart-ca728f4d-a7ff-401b-b4f1-76f2fcc6e869
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3903684458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3903684458
Directory	/workspace/13.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3295159591
Short name	T94
Test name
Test status
Simulation time	2346042393 ps
CPU time	77.58 seconds
Started	Aug 17 06:32:26 PM PDT 24
Finished	Aug 17 06:33:43 PM PDT 24
Peak memory	242872 kb
Host	smart-a936e4af-ae0a-4c3d-be9e-4231023ec51b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3295159591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.3295159591
Directory	/workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.434491749
Short name	T636
Test name
Test status
Simulation time	29904028 ps
CPU time	0.8 seconds
Started	Aug 17 06:32:27 PM PDT 24
Finished	Aug 17 06:32:28 PM PDT 24
Peak memory	211944 kb
Host	smart-172032df-adda-4dff-8c81-ec0d62a8e64a
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434491749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct rl_volatile_unlock_smoke.434491749
Directory	/workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_alert_test.3943369018
Short name	T813
Test name
Test status
Simulation time	24957291 ps
CPU time	0.84 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	208692 kb
Host	smart-77cca51e-fd22-4c19-860e-944192fa318f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943369018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3943369018
Directory	/workspace/14.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/14.lc_ctrl_errors.2946312575
Short name	T40
Test name
Test status
Simulation time	210208265 ps
CPU time	9.19 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	226076 kb
Host	smart-ffb7a8a1-0995-474e-8582-235d8f6deadc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2946312575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2946312575
Directory	/workspace/14.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_access.1804252171
Short name	T476
Test name
Test status
Simulation time	53234901 ps
CPU time	2.04 seconds
Started	Aug 17 06:32:27 PM PDT 24
Finished	Aug 17 06:32:29 PM PDT 24
Peak memory	217076 kb
Host	smart-5ac754d4-6e99-4aa7-8d61-e8f96613bd6f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804252171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1804252171
Directory	/workspace/14.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_errors.2320629863
Short name	T277
Test name
Test status
Simulation time	3696387548 ps
CPU time	28.35 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:32:45 PM PDT 24
Peak memory	218868 kb
Host	smart-1cdb4f6d-0db9-45b0-ad7e-7af5501dd5ac
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320629863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e rrors.2320629863
Directory	/workspace/14.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3060324448
Short name	T26
Test name
Test status
Simulation time	2547395832 ps
CPU time	7.04 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:27 PM PDT 24
Peak memory	224468 kb
Host	smart-bab2392e-fd50-4ec2-89d1-00053d586731
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060324448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta g_prog_failure.3060324448
Directory	/workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_smoke.351475074
Short name	T743
Test name
Test status
Simulation time	257507102 ps
CPU time	4.31 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	217568 kb
Host	smart-ab58c3a6-9dde-4d0c-8fd9-4fb3c56c6710
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351475074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke. 351475074
Directory	/workspace/14.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3745646306
Short name	T298
Test name
Test status
Simulation time	12144844547 ps
CPU time	58.31 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	283452 kb
Host	smart-3a3a2aa1-444f-4ba2-b2f5-1b9fa49b6d73
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745646306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt ag_state_failure.3745646306
Directory	/workspace/14.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2763970317
Short name	T448
Test name
Test status
Simulation time	443032040 ps
CPU time	13.97 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:32:31 PM PDT 24
Peak memory	250748 kb
Host	smart-ef6462fc-3000-43de-9474-b522ba5eb64f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763970317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl _jtag_state_post_trans.2763970317
Directory	/workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_prog_failure.3628795360
Short name	T280
Test name
Test status
Simulation time	210978475 ps
CPU time	2.71 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	218268 kb
Host	smart-3867faab-8328-4015-8a78-b75c17adc6a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628795360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3628795360
Directory	/workspace/14.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_mubi.2370393366
Short name	T734
Test name
Test status
Simulation time	6165475984 ps
CPU time	11.8 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:32:30 PM PDT 24
Peak memory	226132 kb
Host	smart-98be3332-29bb-42d1-a90d-2967c7c66944
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370393366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2370393366
Directory	/workspace/14.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_digest.886680430
Short name	T201
Test name
Test status
Simulation time	319873447 ps
CPU time	9.17 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:32:27 PM PDT 24
Peak memory	226004 kb
Host	smart-49852784-7d2e-47e3-832d-b058749d9fca
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886680430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di gest.886680430
Directory	/workspace/14.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/14.lc_ctrl_sec_token_mux.4028784793
Short name	T679
Test name
Test status
Simulation time	1177085687 ps
CPU time	10.89 seconds
Started	Aug 17 06:32:39 PM PDT 24
Finished	Aug 17 06:32:50 PM PDT 24
Peak memory	218212 kb
Host	smart-8a29fdee-a308-4a05-99a7-69b61e13c58d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028784793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux. 4028784793
Directory	/workspace/14.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/14.lc_ctrl_security_escalation.1347150091
Short name	T428
Test name
Test status
Simulation time	855294081 ps
CPU time	9.25 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	226036 kb
Host	smart-4c3dd2e2-22a1-4380-8ed0-17476ae3cff5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1347150091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1347150091
Directory	/workspace/14.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/14.lc_ctrl_smoke.2945496884
Short name	T766
Test name
Test status
Simulation time	17362336 ps
CPU time	1.4 seconds
Started	Aug 17 06:32:13 PM PDT 24
Finished	Aug 17 06:32:14 PM PDT 24
Peak memory	217604 kb
Host	smart-560d3415-70de-49d2-9eb2-24a6cf84e18d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2945496884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2945496884
Directory	/workspace/14.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_failure.3582329782
Short name	T456
Test name
Test status
Simulation time	358484029 ps
CPU time	36.7 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:57 PM PDT 24
Peak memory	250896 kb
Host	smart-fe2e5ec9-799f-4367-a1ed-56fe118cc58b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582329782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3582329782
Directory	/workspace/14.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/14.lc_ctrl_state_post_trans.2538939745
Short name	T839
Test name
Test status
Simulation time	147240817 ps
CPU time	8.34 seconds
Started	Aug 17 06:32:26 PM PDT 24
Finished	Aug 17 06:32:34 PM PDT 24
Peak memory	250920 kb
Host	smart-00e16011-65a4-4928-b9cd-5f9c74adbb68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538939745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2538939745
Directory	/workspace/14.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/14.lc_ctrl_stress_all.3093077957
Short name	T759
Test name
Test status
Simulation time	6536338591 ps
CPU time	138.38 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:34:38 PM PDT 24
Peak memory	267312 kb
Host	smart-94775023-7d4a-4b2a-8eb1-4d3232d9b3de
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093077957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all.3093077957
Directory	/workspace/14.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3502067630
Short name	T691
Test name
Test status
Simulation time	14943560 ps
CPU time	0.96 seconds
Started	Aug 17 06:32:39 PM PDT 24
Finished	Aug 17 06:32:40 PM PDT 24
Peak memory	211952 kb
Host	smart-83849431-2579-445f-ad6a-812e70fcec22
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502067630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c trl_volatile_unlock_smoke.3502067630
Directory	/workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_alert_test.798018210
Short name	T252
Test name
Test status
Simulation time	15840566 ps
CPU time	1.07 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	209008 kb
Host	smart-3f5c9b73-1f07-45b7-bd47-8b0c09b00ead
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798018210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.798018210
Directory	/workspace/15.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.lc_ctrl_errors.2407512713
Short name	T209
Test name
Test status
Simulation time	260102525 ps
CPU time	9.85 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:29 PM PDT 24
Peak memory	218276 kb
Host	smart-020369dd-43bf-4495-8f57-5ecbe51d6db4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2407512713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2407512713
Directory	/workspace/15.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_access.2380891005
Short name	T375
Test name
Test status
Simulation time	912401284 ps
CPU time	11.82 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:35 PM PDT 24
Peak memory	217308 kb
Host	smart-b07e8013-0302-4ca6-8b69-c4668b132e3a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380891005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2380891005
Directory	/workspace/15.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_errors.421192438
Short name	T223
Test name
Test status
Simulation time	4458468620 ps
CPU time	36.16 seconds
Started	Aug 17 06:32:12 PM PDT 24
Finished	Aug 17 06:32:49 PM PDT 24
Peak memory	216968 kb
Host	smart-d6e7108c-d39b-439f-8a79-c6c8e0a6509d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421192438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er rors.421192438
Directory	/workspace/15.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1160064208
Short name	T391
Test name
Test status
Simulation time	377893489 ps
CPU time	4.39 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	218216 kb
Host	smart-55444891-078e-4897-8ab0-9414be8bb18a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160064208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta g_prog_failure.1160064208
Directory	/workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_smoke.6226197
Short name	T406
Test name
Test status
Simulation time	476797551 ps
CPU time	11.78 seconds
Started	Aug 17 06:32:14 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	217580 kb
Host	smart-1a3606ce-236f-4493-9f58-2fd5253d560e
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6226197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.6226197
Directory	/workspace/15.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2083334889
Short name	T357
Test name
Test status
Simulation time	2743495467 ps
CPU time	51.02 seconds
Started	Aug 17 06:32:13 PM PDT 24
Finished	Aug 17 06:33:04 PM PDT 24
Peak memory	267236 kb
Host	smart-9ee461fc-bb01-4348-a6b0-a04b5e5e1d1c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083334889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt ag_state_failure.2083334889
Directory	/workspace/15.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_prog_failure.3409058268
Short name	T491
Test name
Test status
Simulation time	91036655 ps
CPU time	3.03 seconds
Started	Aug 17 06:32:56 PM PDT 24
Finished	Aug 17 06:32:59 PM PDT 24
Peak memory	218264 kb
Host	smart-63388645-d370-45fd-a587-c9ef173c055b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409058268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3409058268
Directory	/workspace/15.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_mubi.332288558
Short name	T620
Test name
Test status
Simulation time	5818660182 ps
CPU time	21.02 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:41 PM PDT 24
Peak memory	220028 kb
Host	smart-b62a4183-5dde-48d4-9e3d-c1e101b7c605
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332288558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.332288558
Directory	/workspace/15.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_digest.1754385485
Short name	T394
Test name
Test status
Simulation time	876941263 ps
CPU time	8.17 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:31 PM PDT 24
Peak memory	225992 kb
Host	smart-5e676649-e1b5-45aa-a589-d2c8a4351f18
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754385485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d igest.1754385485
Directory	/workspace/15.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/15.lc_ctrl_sec_token_mux.1179245398
Short name	T263
Test name
Test status
Simulation time	1561394860 ps
CPU time	13.98 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:34 PM PDT 24
Peak memory	218216 kb
Host	smart-60d19683-8f7c-42be-948a-2f65d37e4d08
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179245398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux. 1179245398
Directory	/workspace/15.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/15.lc_ctrl_smoke.3877566269
Short name	T595
Test name
Test status
Simulation time	15329737 ps
CPU time	1.36 seconds
Started	Aug 17 06:32:24 PM PDT 24
Finished	Aug 17 06:32:25 PM PDT 24
Peak memory	213600 kb
Host	smart-ad1f79cf-c55e-4044-8f9a-db8613f5b24a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3877566269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3877566269
Directory	/workspace/15.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_failure.4187142152
Short name	T384
Test name
Test status
Simulation time	1052475252 ps
CPU time	37.27 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:57 PM PDT 24
Peak memory	250896 kb
Host	smart-c8bd8ac3-43b7-4a01-b6a7-1096bb00768d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187142152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.4187142152
Directory	/workspace/15.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/15.lc_ctrl_state_post_trans.4089393953
Short name	T697
Test name
Test status
Simulation time	82026530 ps
CPU time	3.08 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:27 PM PDT 24
Peak memory	222520 kb
Host	smart-3fda5f92-b16f-4eb8-bf5a-bd5627fb5825
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4089393953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.4089393953
Directory	/workspace/15.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/15.lc_ctrl_stress_all.3499287216
Short name	T724
Test name
Test status
Simulation time	44718321307 ps
CPU time	339.8 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:38:03 PM PDT 24
Peak memory	267060 kb
Host	smart-b02a58d7-1e44-436d-990e-0d1707ba2d43
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499287216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all.3499287216
Directory	/workspace/15.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1910499939
Short name	T442
Test name
Test status
Simulation time	35976580 ps
CPU time	0.83 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	211876 kb
Host	smart-430ddda6-fe92-4aea-aca9-88d9dc6d9f53
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910499939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c trl_volatile_unlock_smoke.1910499939
Directory	/workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_alert_test.1729594234
Short name	T648
Test name
Test status
Simulation time	80981802 ps
CPU time	1.17 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	208876 kb
Host	smart-2d073b9d-346a-4001-956c-a013258a26e8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729594234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1729594234
Directory	/workspace/16.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.lc_ctrl_errors.702054597
Short name	T373
Test name
Test status
Simulation time	432635736 ps
CPU time	13.37 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:35 PM PDT 24
Peak memory	218176 kb
Host	smart-0c1330a3-f84b-4550-86d0-2263a3b89f13
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=702054597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.702054597
Directory	/workspace/16.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_access.2648297802
Short name	T461
Test name
Test status
Simulation time	636998154 ps
CPU time	16.17 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:32:35 PM PDT 24
Peak memory	217160 kb
Host	smart-b17f51ae-4966-42c7-90f6-70d861da50c1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648297802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2648297802
Directory	/workspace/16.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_errors.1833766952
Short name	T865
Test name
Test status
Simulation time	2709596449 ps
CPU time	23.64 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:46 PM PDT 24
Peak memory	226052 kb
Host	smart-ba0c1561-e7ec-4e1a-889a-878f0c6f1fe8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833766952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e rrors.1833766952
Directory	/workspace/16.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1509152952
Short name	T768
Test name
Test status
Simulation time	520752376 ps
CPU time	8.58 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:31 PM PDT 24
Peak memory	224276 kb
Host	smart-d5179153-a465-400c-8329-01d9042f4c8b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509152952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta g_prog_failure.1509152952
Directory	/workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_smoke.3786758261
Short name	T725
Test name
Test status
Simulation time	229552741 ps
CPU time	4.52 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	217420 kb
Host	smart-6777db17-d317-4222-ba03-049ed214ffeb
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786758261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke .3786758261
Directory	/workspace/16.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_failure.628424983
Short name	T669
Test name
Test status
Simulation time	1748503474 ps
CPU time	71.88 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:33:32 PM PDT 24
Peak memory	276552 kb
Host	smart-2c4735ae-a172-4f8c-b048-bb5f2389e6b5
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628424983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta g_state_failure.628424983
Directory	/workspace/16.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2310125126
Short name	T805
Test name
Test status
Simulation time	392069693 ps
CPU time	16.89 seconds
Started	Aug 17 06:32:39 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	250832 kb
Host	smart-29418d60-180d-4822-9d39-0dc488e35f74
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310125126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl _jtag_state_post_trans.2310125126
Directory	/workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_prog_failure.1484199628
Short name	T271
Test name
Test status
Simulation time	201466337 ps
CPU time	2.92 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	222488 kb
Host	smart-ef00de36-2858-4bd3-9d65-9552897815b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1484199628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1484199628
Directory	/workspace/16.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_mubi.1269586217
Short name	T485
Test name
Test status
Simulation time	454713510 ps
CPU time	9.82 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:29 PM PDT 24
Peak memory	226064 kb
Host	smart-5d8a75f6-3f8d-41a3-8c11-405ec4b2e32d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269586217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1269586217
Directory	/workspace/16.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_digest.896671729
Short name	T834
Test name
Test status
Simulation time	442356573 ps
CPU time	7.01 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:29 PM PDT 24
Peak memory	218192 kb
Host	smart-66a4d350-c258-417d-8a42-338f4286df05
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896671729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_di gest.896671729
Directory	/workspace/16.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/16.lc_ctrl_sec_token_mux.957627969
Short name	T339
Test name
Test status
Simulation time	607153862 ps
CPU time	11.98 seconds
Started	Aug 17 06:32:26 PM PDT 24
Finished	Aug 17 06:32:38 PM PDT 24
Peak memory	218192 kb
Host	smart-6f303970-c8a4-4d0a-9cda-1083a3ba9c6e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957627969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.957627969
Directory	/workspace/16.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/16.lc_ctrl_security_escalation.1895210997
Short name	T158
Test name
Test status
Simulation time	465578986 ps
CPU time	11.87 seconds
Started	Aug 17 06:32:36 PM PDT 24
Finished	Aug 17 06:32:47 PM PDT 24
Peak memory	226116 kb
Host	smart-5edd28a2-be00-4042-b588-822d812d351c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1895210997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1895210997
Directory	/workspace/16.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/16.lc_ctrl_smoke.838545460
Short name	T299
Test name
Test status
Simulation time	102216240 ps
CPU time	7.16 seconds
Started	Aug 17 06:32:47 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	217624 kb
Host	smart-6a2fb185-8d8c-492c-8e8c-6300f0003dd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=838545460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.838545460
Directory	/workspace/16.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_failure.3970455195
Short name	T767
Test name
Test status
Simulation time	740156067 ps
CPU time	29.64 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:52 PM PDT 24
Peak memory	250888 kb
Host	smart-07dbc3e7-2ae5-4498-89ba-4c095abed799
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970455195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3970455195
Directory	/workspace/16.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/16.lc_ctrl_state_post_trans.1129972178
Short name	T310
Test name
Test status
Simulation time	45658788 ps
CPU time	5.63 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	246852 kb
Host	smart-b98a579f-d9e1-4b22-b3c9-66d99a5b4450
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1129972178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1129972178
Directory	/workspace/16.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/16.lc_ctrl_stress_all.726718505
Short name	T764
Test name
Test status
Simulation time	177017599921 ps
CPU time	325.98 seconds
Started	Aug 17 06:32:24 PM PDT 24
Finished	Aug 17 06:37:55 PM PDT 24
Peak memory	251888 kb
Host	smart-85e27cd8-71fd-4579-85cf-2a897a9933e3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726718505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all.726718505
Directory	/workspace/16.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3828432816
Short name	T437
Test name
Test status
Simulation time	21958307 ps
CPU time	0.87 seconds
Started	Aug 17 06:32:25 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	211824 kb
Host	smart-baa44e45-aa7b-468f-9526-400b86263049
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828432816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c trl_volatile_unlock_smoke.3828432816
Directory	/workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_alert_test.3157414440
Short name	T574
Test name
Test status
Simulation time	31382647 ps
CPU time	1.18 seconds
Started	Aug 17 06:32:53 PM PDT 24
Finished	Aug 17 06:32:54 PM PDT 24
Peak memory	208916 kb
Host	smart-f39206ba-f461-471e-a06f-330788653d24
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157414440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3157414440
Directory	/workspace/17.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.lc_ctrl_errors.699535827
Short name	T258
Test name
Test status
Simulation time	1153570721 ps
CPU time	11.87 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:32 PM PDT 24
Peak memory	216964 kb
Host	smart-92a504b3-e153-4b87-86be-2c16ae05580c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699535827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.699535827
Directory	/workspace/17.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_access.1374181202
Short name	T127
Test name
Test status
Simulation time	273844880 ps
CPU time	2.52 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:23 PM PDT 24
Peak memory	217588 kb
Host	smart-0d08f59c-662c-4af7-936b-f6e9a2589c90
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374181202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1374181202
Directory	/workspace/17.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_errors.2373304969
Short name	T826
Test name
Test status
Simulation time	1361603377 ps
CPU time	25.33 seconds
Started	Aug 17 06:32:34 PM PDT 24
Finished	Aug 17 06:33:00 PM PDT 24
Peak memory	218172 kb
Host	smart-a22a1d7f-9d73-4982-9221-241e70611a24
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373304969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e rrors.2373304969
Directory	/workspace/17.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1634437263
Short name	T613
Test name
Test status
Simulation time	404867441 ps
CPU time	2.87 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	222056 kb
Host	smart-b5d4b700-9725-4898-92d5-afd6e6a5af75
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634437263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta g_prog_failure.1634437263
Directory	/workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_smoke.3829601742
Short name	T29
Test name
Test status
Simulation time	536718734 ps
CPU time	7.88 seconds
Started	Aug 17 06:32:14 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	217548 kb
Host	smart-55d189cf-3751-44d7-a055-ec6a8419c3a0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829601742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke .3829601742
Directory	/workspace/17.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1919768089
Short name	T867
Test name
Test status
Simulation time	1042018145 ps
CPU time	33.27 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	267224 kb
Host	smart-a655896a-c8be-426d-a848-9c1bd32f1f89
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919768089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt ag_state_failure.1919768089
Directory	/workspace/17.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.3270900697
Short name	T267
Test name
Test status
Simulation time	306624443 ps
CPU time	14.99 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:38 PM PDT 24
Peak memory	250832 kb
Host	smart-a8db5257-e993-416c-b241-7c39ff9c9bc3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270900697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl _jtag_state_post_trans.3270900697
Directory	/workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_prog_failure.1006819374
Short name	T370
Test name
Test status
Simulation time	30412416 ps
CPU time	2.02 seconds
Started	Aug 17 06:32:24 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	218268 kb
Host	smart-0c277286-a161-4714-b1f5-f9ecdccbeef4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1006819374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1006819374
Directory	/workspace/17.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_mubi.1330733397
Short name	T322
Test name
Test status
Simulation time	256298173 ps
CPU time	10.54 seconds
Started	Aug 17 06:32:28 PM PDT 24
Finished	Aug 17 06:32:39 PM PDT 24
Peak memory	225992 kb
Host	smart-fd65f934-3e68-4d97-be15-04e695a8ce63
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330733397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1330733397
Directory	/workspace/17.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_digest.2441817311
Short name	T870
Test name
Test status
Simulation time	1557138302 ps
CPU time	21.75 seconds
Started	Aug 17 06:32:36 PM PDT 24
Finished	Aug 17 06:32:58 PM PDT 24
Peak memory	226000 kb
Host	smart-40223f78-c00a-415f-9837-64407331de55
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441817311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d igest.2441817311
Directory	/workspace/17.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/17.lc_ctrl_sec_token_mux.3967053615
Short name	T320
Test name
Test status
Simulation time	736351522 ps
CPU time	8.51 seconds
Started	Aug 17 06:32:29 PM PDT 24
Finished	Aug 17 06:32:38 PM PDT 24
Peak memory	226024 kb
Host	smart-033dfacb-1af5-42d2-b52d-8a79afe559f9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967053615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux. 3967053615
Directory	/workspace/17.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/17.lc_ctrl_security_escalation.2722370471
Short name	T516
Test name
Test status
Simulation time	1755159426 ps
CPU time	16.76 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:36 PM PDT 24
Peak memory	226068 kb
Host	smart-d2a4f7c7-a245-4970-b18a-ea84ac3ddcb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2722370471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2722370471
Directory	/workspace/17.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/17.lc_ctrl_smoke.3884077169
Short name	T295
Test name
Test status
Simulation time	523101208 ps
CPU time	2.55 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	214776 kb
Host	smart-67b6b57b-23ae-45a9-b674-012f13a63d34
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884077169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3884077169
Directory	/workspace/17.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_failure.3210186485
Short name	T600
Test name
Test status
Simulation time	302473151 ps
CPU time	28.06 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:49 PM PDT 24
Peak memory	251212 kb
Host	smart-643033ef-8fd7-41ec-af6d-f819ca7e3ce0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210186485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3210186485
Directory	/workspace/17.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/17.lc_ctrl_state_post_trans.459714564
Short name	T524
Test name
Test status
Simulation time	65507848 ps
CPU time	6.64 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	244752 kb
Host	smart-4571001a-3e21-4a51-aadd-b6797ee4dcbc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459714564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.459714564
Directory	/workspace/17.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/17.lc_ctrl_stress_all.2235600830
Short name	T629
Test name
Test status
Simulation time	2012604041 ps
CPU time	18.58 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:38 PM PDT 24
Peak memory	219040 kb
Host	smart-27008309-7c13-489a-9273-79985427c761
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235600830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all.2235600830
Directory	/workspace/17.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3023834552
Short name	T132
Test name
Test status
Simulation time	16517979713 ps
CPU time	58.24 seconds
Started	Aug 17 06:32:24 PM PDT 24
Finished	Aug 17 06:33:22 PM PDT 24
Peak memory	251080 kb
Host	smart-2f8f4bc3-e43b-4209-8c15-73a7d6ee313c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3023834552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.3023834552
Directory	/workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1047786076
Short name	T404
Test name
Test status
Simulation time	44242484 ps
CPU time	0.83 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:32:18 PM PDT 24
Peak memory	211872 kb
Host	smart-893eece3-fb42-4dcb-9679-718c7d9932f0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047786076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c trl_volatile_unlock_smoke.1047786076
Directory	/workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_alert_test.650165273
Short name	T306
Test name
Test status
Simulation time	66608091 ps
CPU time	0.88 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:20 PM PDT 24
Peak memory	208876 kb
Host	smart-769ae9a8-43ba-4968-ab94-c4d69390a919
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650165273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.650165273
Directory	/workspace/18.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.lc_ctrl_errors.3882895266
Short name	T824
Test name
Test status
Simulation time	603326411 ps
CPU time	10.18 seconds
Started	Aug 17 06:32:38 PM PDT 24
Finished	Aug 17 06:32:48 PM PDT 24
Peak memory	218268 kb
Host	smart-a07130e4-0524-4cb7-9ab2-c72af2001b0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3882895266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3882895266
Directory	/workspace/18.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_access.2614674962
Short name	T452
Test name
Test status
Simulation time	2250995921 ps
CPU time	25.55 seconds
Started	Aug 17 06:32:43 PM PDT 24
Finished	Aug 17 06:33:09 PM PDT 24
Peak memory	217404 kb
Host	smart-027fb322-a1d9-44cc-a019-3c320840bb11
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614674962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2614674962
Directory	/workspace/18.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_errors.3696085851
Short name	T690
Test name
Test status
Simulation time	28013397686 ps
CPU time	44.51 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:33:06 PM PDT 24
Peak memory	218912 kb
Host	smart-2ae8e6a5-2f2d-432a-a5b1-7f81b7bb7c80
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696085851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e rrors.3696085851
Directory	/workspace/18.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.4013561807
Short name	T443
Test name
Test status
Simulation time	336040887 ps
CPU time	11.24 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:33 PM PDT 24
Peak memory	218220 kb
Host	smart-59bec332-d337-43b9-aa31-98784c7fe400
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013561807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta g_prog_failure.4013561807
Directory	/workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_smoke.2006092416
Short name	T670
Test name
Test status
Simulation time	425968007 ps
CPU time	2.24 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:23 PM PDT 24
Peak memory	217568 kb
Host	smart-d9ae7dee-f7e2-4590-8187-26380ed5d751
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006092416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke .2006092416
Directory	/workspace/18.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_failure.570885099
Short name	T712
Test name
Test status
Simulation time	1213745255 ps
CPU time	53.16 seconds
Started	Aug 17 06:32:57 PM PDT 24
Finished	Aug 17 06:33:50 PM PDT 24
Peak memory	267344 kb
Host	smart-e547f836-47f9-4447-a85e-0e746c80b42f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570885099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta g_state_failure.570885099
Directory	/workspace/18.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2835573093
Short name	T399
Test name
Test status
Simulation time	519908172 ps
CPU time	14.32 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:34 PM PDT 24
Peak memory	250796 kb
Host	smart-741cc217-e5c5-42a0-989c-04dd1c035194
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835573093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl _jtag_state_post_trans.2835573093
Directory	/workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_prog_failure.253249559
Short name	T539
Test name
Test status
Simulation time	30571617 ps
CPU time	2.06 seconds
Started	Aug 17 06:32:57 PM PDT 24
Finished	Aug 17 06:32:59 PM PDT 24
Peak memory	218224 kb
Host	smart-ef7258f9-0cf5-4e81-9e6c-828ae90867d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=253249559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.253249559
Directory	/workspace/18.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_mubi.2610034168
Short name	T649
Test name
Test status
Simulation time	1913465917 ps
CPU time	16.27 seconds
Started	Aug 17 06:32:33 PM PDT 24
Finished	Aug 17 06:32:49 PM PDT 24
Peak memory	219024 kb
Host	smart-7440c9b2-e0fa-4ecc-b94c-7f406afe6499
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610034168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2610034168
Directory	/workspace/18.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_digest.2371699017
Short name	T21
Test name
Test status
Simulation time	256197541 ps
CPU time	10.72 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:34 PM PDT 24
Peak memory	226004 kb
Host	smart-7695201b-d340-4b37-b495-e177926892af
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371699017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d igest.2371699017
Directory	/workspace/18.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/18.lc_ctrl_sec_token_mux.209633784
Short name	T683
Test name
Test status
Simulation time	3176332005 ps
CPU time	5.84 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	218256 kb
Host	smart-44ac9cf1-9db4-458d-b56b-042f6045b5e2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209633784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.209633784
Directory	/workspace/18.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/18.lc_ctrl_security_escalation.3301908198
Short name	T832
Test name
Test status
Simulation time	338314199 ps
CPU time	13.08 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:34 PM PDT 24
Peak memory	225468 kb
Host	smart-444e57a0-09c8-442d-9389-6a7f27f28f91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3301908198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3301908198
Directory	/workspace/18.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/18.lc_ctrl_smoke.4043974461
Short name	T791
Test name
Test status
Simulation time	21416261 ps
CPU time	1.63 seconds
Started	Aug 17 06:32:50 PM PDT 24
Finished	Aug 17 06:32:52 PM PDT 24
Peak memory	213944 kb
Host	smart-770f52b2-74ed-41bc-b3d8-ad58eb7a0c03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4043974461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.4043974461
Directory	/workspace/18.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_failure.1067180035
Short name	T757
Test name
Test status
Simulation time	1160907550 ps
CPU time	32.37 seconds
Started	Aug 17 06:32:28 PM PDT 24
Finished	Aug 17 06:33:00 PM PDT 24
Peak memory	250820 kb
Host	smart-5598ac11-ac77-46ac-9374-7e2742f00947
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067180035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1067180035
Directory	/workspace/18.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/18.lc_ctrl_state_post_trans.180581167
Short name	T721
Test name
Test status
Simulation time	238158455 ps
CPU time	5.58 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	246620 kb
Host	smart-8a4f088b-08c1-419b-8baf-d9fc6ab392fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=180581167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.180581167
Directory	/workspace/18.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/18.lc_ctrl_stress_all.2662172418
Short name	T522
Test name
Test status
Simulation time	12415754518 ps
CPU time	98.43 seconds
Started	Aug 17 06:32:27 PM PDT 24
Finished	Aug 17 06:34:05 PM PDT 24
Peak memory	250984 kb
Host	smart-8e50e105-ffc5-4685-86f9-ddbf07941b92
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662172418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all.2662172418
Directory	/workspace/18.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1083379568
Short name	T770
Test name
Test status
Simulation time	898155620 ps
CPU time	52.8 seconds
Started	Aug 17 06:32:39 PM PDT 24
Finished	Aug 17 06:33:32 PM PDT 24
Peak memory	252508 kb
Host	smart-d95cd913-f3fe-42a7-88b8-bd5fe027b0d8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1083379568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1083379568
Directory	/workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1267425415
Short name	T740
Test name
Test status
Simulation time	48605073 ps
CPU time	0.89 seconds
Started	Aug 17 06:32:24 PM PDT 24
Finished	Aug 17 06:32:25 PM PDT 24
Peak memory	211828 kb
Host	smart-83db0b72-a849-4903-a9ad-bc7130f403af
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267425415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c trl_volatile_unlock_smoke.1267425415
Directory	/workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_alert_test.3386949826
Short name	T640
Test name
Test status
Simulation time	16759448 ps
CPU time	1.01 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:23 PM PDT 24
Peak memory	208960 kb
Host	smart-42f8bfc7-452d-4bb0-8ac9-4bc53623635f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386949826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3386949826
Directory	/workspace/19.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.lc_ctrl_errors.1628228998
Short name	T210
Test name
Test status
Simulation time	1400403486 ps
CPU time	10.85 seconds
Started	Aug 17 06:32:32 PM PDT 24
Finished	Aug 17 06:32:43 PM PDT 24
Peak memory	218448 kb
Host	smart-c27aa234-f672-4728-a77b-b488899a0df4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1628228998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1628228998
Directory	/workspace/19.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_access.3998357714
Short name	T857
Test name
Test status
Simulation time	178450906 ps
CPU time	5.22 seconds
Started	Aug 17 06:32:26 PM PDT 24
Finished	Aug 17 06:32:32 PM PDT 24
Peak memory	217108 kb
Host	smart-bbd23670-c890-443a-824b-67fdc02ddcaa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998357714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3998357714
Directory	/workspace/19.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_errors.3966408727
Short name	T412
Test name
Test status
Simulation time	4967489584 ps
CPU time	33.33 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	218812 kb
Host	smart-239c1991-bac6-47ff-b9f3-c649a4b4a959
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966408727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e rrors.3966408727
Directory	/workspace/19.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1486046284
Short name	T569
Test name
Test status
Simulation time	1170379983 ps
CPU time	6.18 seconds
Started	Aug 17 06:32:40 PM PDT 24
Finished	Aug 17 06:32:46 PM PDT 24
Peak memory	218216 kb
Host	smart-3c93d73e-36d6-49d0-8405-7cec7409f845
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486046284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta g_prog_failure.1486046284
Directory	/workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_smoke.2076516013
Short name	T77
Test name
Test status
Simulation time	97350533 ps
CPU time	2.18 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:23 PM PDT 24
Peak memory	217420 kb
Host	smart-88fe74e9-c711-46a2-9622-7f1dcaf42504
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076516013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke .2076516013
Directory	/workspace/19.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3426699907
Short name	T611
Test name
Test status
Simulation time	2540649961 ps
CPU time	84.81 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:33:44 PM PDT 24
Peak memory	279980 kb
Host	smart-db2c4215-48f5-46ae-ba56-328ff53971a4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426699907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt ag_state_failure.3426699907
Directory	/workspace/19.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3613623432
Short name	T340
Test name
Test status
Simulation time	684660985 ps
CPU time	16.5 seconds
Started	Aug 17 06:32:24 PM PDT 24
Finished	Aug 17 06:32:41 PM PDT 24
Peak memory	250836 kb
Host	smart-823d4b25-6a90-4341-9c77-2dcdd2d3a1ce
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613623432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl _jtag_state_post_trans.3613623432
Directory	/workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_prog_failure.2862386353
Short name	T454
Test name
Test status
Simulation time	29667090 ps
CPU time	1.72 seconds
Started	Aug 17 06:32:33 PM PDT 24
Finished	Aug 17 06:32:35 PM PDT 24
Peak memory	218200 kb
Host	smart-33f3ef41-8266-4191-81a2-b342052fcd19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862386353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2862386353
Directory	/workspace/19.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_mubi.3071458491
Short name	T408
Test name
Test status
Simulation time	224953790 ps
CPU time	9.5 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:32 PM PDT 24
Peak memory	226052 kb
Host	smart-9c03d7a4-6316-4862-b976-92d856ddb1b2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071458491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3071458491
Directory	/workspace/19.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_digest.1294708181
Short name	T643
Test name
Test status
Simulation time	1080563153 ps
CPU time	7.55 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:28 PM PDT 24
Peak memory	225980 kb
Host	smart-3cddfeeb-3047-4e3c-a14c-4e222040a621
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294708181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d igest.1294708181
Directory	/workspace/19.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/19.lc_ctrl_sec_token_mux.1815979249
Short name	T581
Test name
Test status
Simulation time	481378065 ps
CPU time	5.69 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	218172 kb
Host	smart-c6f31323-82e7-473e-9f9f-c0665c7ef66b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815979249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux. 1815979249
Directory	/workspace/19.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/19.lc_ctrl_security_escalation.2852232453
Short name	T195
Test name
Test status
Simulation time	421617050 ps
CPU time	9.58 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:31 PM PDT 24
Peak memory	225288 kb
Host	smart-bc6f49d4-ab5b-4e23-b80a-4ed28c1d54e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2852232453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2852232453
Directory	/workspace/19.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/19.lc_ctrl_smoke.2205696231
Short name	T65
Test name
Test status
Simulation time	17999678 ps
CPU time	1.47 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:23 PM PDT 24
Peak memory	213804 kb
Host	smart-70a53553-4c36-491e-9230-068f7a54d4dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205696231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.2205696231
Directory	/workspace/19.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_failure.3431186008
Short name	T795
Test name
Test status
Simulation time	3762810491 ps
CPU time	35.13 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	250936 kb
Host	smart-60f743df-1c8d-48c8-a154-2d41757b6822
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431186008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3431186008
Directory	/workspace/19.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/19.lc_ctrl_state_post_trans.1654097760
Short name	T692
Test name
Test status
Simulation time	344095415 ps
CPU time	9.4 seconds
Started	Aug 17 06:32:27 PM PDT 24
Finished	Aug 17 06:32:37 PM PDT 24
Peak memory	251004 kb
Host	smart-41e7299b-0198-4cc1-927f-cd8d557d9e63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654097760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1654097760
Directory	/workspace/19.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/19.lc_ctrl_stress_all.3358354363
Short name	T545
Test name
Test status
Simulation time	4511857659 ps
CPU time	98.92 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:34:01 PM PDT 24
Peak memory	252284 kb
Host	smart-f9689d76-4930-4f60-ab86-cfd66bdf8321
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358354363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all.3358354363
Directory	/workspace/19.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2164199152
Short name	T765
Test name
Test status
Simulation time	1186149090 ps
CPU time	11.66 seconds
Started	Aug 17 06:32:37 PM PDT 24
Finished	Aug 17 06:32:48 PM PDT 24
Peak memory	250720 kb
Host	smart-e3912bc2-2eb9-437b-9758-b021aae39a6e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2164199152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2164199152
Directory	/workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1432653944
Short name	T415
Test name
Test status
Simulation time	27579647 ps
CPU time	0.88 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	217632 kb
Host	smart-a903aa02-f0d2-476a-92e1-01864057cf50
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432653944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c trl_volatile_unlock_smoke.1432653944
Directory	/workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_alert_test.1732682439
Short name	T751
Test name
Test status
Simulation time	74936171 ps
CPU time	0.99 seconds
Started	Aug 17 06:31:29 PM PDT 24
Finished	Aug 17 06:31:30 PM PDT 24
Peak memory	208868 kb
Host	smart-10ded671-4114-44cb-beff-68db7543f20e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732682439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1732682439
Directory	/workspace/2.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.lc_ctrl_claim_transition_if.633608405
Short name	T510
Test name
Test status
Simulation time	13878427 ps
CPU time	0.97 seconds
Started	Aug 17 06:31:55 PM PDT 24
Finished	Aug 17 06:31:56 PM PDT 24
Peak memory	208752 kb
Host	smart-42c9a5bd-9bd0-487d-8b8a-fe1323eabb15
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=633608405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.633608405
Directory	/workspace/2.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/2.lc_ctrl_errors.2017547259
Short name	T330
Test name
Test status
Simulation time	1657867973 ps
CPU time	9.81 seconds
Started	Aug 17 06:31:37 PM PDT 24
Finished	Aug 17 06:31:47 PM PDT 24
Peak memory	218184 kb
Host	smart-dc2be60a-9e5c-47a9-8f9c-8f1c2c5ea97b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2017547259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2017547259
Directory	/workspace/2.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_access.206456368
Short name	T164
Test name
Test status
Simulation time	776111867 ps
CPU time	7.64 seconds
Started	Aug 17 06:32:08 PM PDT 24
Finished	Aug 17 06:32:16 PM PDT 24
Peak memory	217236 kb
Host	smart-f66e2dce-6bd3-4767-ae4c-2d48cbe71c88
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206456368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.206456368
Directory	/workspace/2.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_errors.942502379
Short name	T429
Test name
Test status
Simulation time	4225014878 ps
CPU time	64.7 seconds
Started	Aug 17 06:31:33 PM PDT 24
Finished	Aug 17 06:32:38 PM PDT 24
Peak memory	218860 kb
Host	smart-262132fe-9a43-49da-8d98-9c4628c2868d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942502379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err ors.942502379
Directory	/workspace/2.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_priority.2518773769
Short name	T496
Test name
Test status
Simulation time	181006831 ps
CPU time	2.85 seconds
Started	Aug 17 06:31:56 PM PDT 24
Finished	Aug 17 06:31:59 PM PDT 24
Peak memory	217452 kb
Host	smart-bc91a169-d09f-47d3-8e48-78e67ce8dcc4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518773769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2 518773769
Directory	/workspace/2.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1605742724
Short name	T837
Test name
Test status
Simulation time	2548784646 ps
CPU time	9.64 seconds
Started	Aug 17 06:32:03 PM PDT 24
Finished	Aug 17 06:32:12 PM PDT 24
Peak memory	218252 kb
Host	smart-60238c7e-25b5-4b1b-87a1-9f6010641e78
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605742724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag _prog_failure.1605742724
Directory	/workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2355056863
Short name	T507
Test name
Test status
Simulation time	4068441274 ps
CPU time	14.37 seconds
Started	Aug 17 06:32:02 PM PDT 24
Finished	Aug 17 06:32:16 PM PDT 24
Peak memory	217596 kb
Host	smart-f37e3aa9-0987-4d20-9c47-e411cbc89e06
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355056863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_regwen_during_op.2355056863
Directory	/workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_smoke.2074131639
Short name	T278
Test name
Test status
Simulation time	87427694 ps
CPU time	1.32 seconds
Started	Aug 17 06:31:39 PM PDT 24
Finished	Aug 17 06:31:40 PM PDT 24
Peak memory	217532 kb
Host	smart-64424780-efd6-40fb-a5ce-df6f964e93e9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074131639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke. 2074131639
Directory	/workspace/2.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3851131577
Short name	T742
Test name
Test status
Simulation time	2913605909 ps
CPU time	57.59 seconds
Started	Aug 17 06:31:32 PM PDT 24
Finished	Aug 17 06:32:30 PM PDT 24
Peak memory	276196 kb
Host	smart-8f2efa8f-394b-432d-b7a3-26ab52362ac6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851131577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta g_state_failure.3851131577
Directory	/workspace/2.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2240566221
Short name	T141
Test name
Test status
Simulation time	719751960 ps
CPU time	7.14 seconds
Started	Aug 17 06:31:24 PM PDT 24
Finished	Aug 17 06:31:33 PM PDT 24
Peak memory	226256 kb
Host	smart-f90ac437-c4d4-4549-bb0f-f5915fc766dc
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240566221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_state_post_trans.2240566221
Directory	/workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_prog_failure.403926783
Short name	T509
Test name
Test status
Simulation time	33273165 ps
CPU time	2.25 seconds
Started	Aug 17 06:32:03 PM PDT 24
Finished	Aug 17 06:32:05 PM PDT 24
Peak memory	222072 kb
Host	smart-0b120afa-2747-4879-97fb-fd864bb2bac4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=403926783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.403926783
Directory	/workspace/2.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_regwen_during_op.3696830922
Short name	T717
Test name
Test status
Simulation time	822424318 ps
CPU time	13.37 seconds
Started	Aug 17 06:31:27 PM PDT 24
Finished	Aug 17 06:31:41 PM PDT 24
Peak memory	214556 kb
Host	smart-c40ca345-2135-4898-8e22-30c72fde63df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696830922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3696830922
Directory	/workspace/2.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_cm.781458231
Short name	T56
Test name
Test status
Simulation time	123366375 ps
CPU time	21.81 seconds
Started	Aug 17 06:32:12 PM PDT 24
Finished	Aug 17 06:32:34 PM PDT 24
Peak memory	282388 kb
Host	smart-b7ac82d9-ad32-4703-87c8-c5eb332afd14
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781458231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.781458231
Directory	/workspace/2.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_mubi.1083457692
Short name	T335
Test name
Test status
Simulation time	1524431187 ps
CPU time	14.33 seconds
Started	Aug 17 06:31:39 PM PDT 24
Finished	Aug 17 06:31:54 PM PDT 24
Peak memory	219976 kb
Host	smart-c31b03cf-9e9a-4034-a906-b86468ddd05d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083457692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1083457692
Directory	/workspace/2.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_digest.3814119968
Short name	T346
Test name
Test status
Simulation time	6011410500 ps
CPU time	11.37 seconds
Started	Aug 17 06:31:24 PM PDT 24
Finished	Aug 17 06:31:37 PM PDT 24
Peak memory	226060 kb
Host	smart-e0c2b6f6-6c5e-4f5e-9b29-12ed04bf0b7f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814119968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di gest.3814119968
Directory	/workspace/2.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/2.lc_ctrl_sec_token_mux.2299547351
Short name	T686
Test name
Test status
Simulation time	267276599 ps
CPU time	9.94 seconds
Started	Aug 17 06:31:40 PM PDT 24
Finished	Aug 17 06:31:50 PM PDT 24
Peak memory	225944 kb
Host	smart-4b664d33-1bfa-45ff-b80f-aed0df38b7ed
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299547351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2 299547351
Directory	/workspace/2.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/2.lc_ctrl_security_escalation.3269034468
Short name	T49
Test name
Test status
Simulation time	772175079 ps
CPU time	13.93 seconds
Started	Aug 17 06:31:33 PM PDT 24
Finished	Aug 17 06:31:47 PM PDT 24
Peak memory	226088 kb
Host	smart-735d690d-da6a-4896-bc82-99790db764ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269034468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3269034468
Directory	/workspace/2.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/2.lc_ctrl_smoke.3849329732
Short name	T67
Test name
Test status
Simulation time	79334571 ps
CPU time	2.07 seconds
Started	Aug 17 06:31:57 PM PDT 24
Finished	Aug 17 06:31:59 PM PDT 24
Peak memory	214388 kb
Host	smart-a7ff9904-f9b2-4231-8e96-fd67db89f9ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3849329732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3849329732
Directory	/workspace/2.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_failure.293908068
Short name	T843
Test name
Test status
Simulation time	195371953 ps
CPU time	17.15 seconds
Started	Aug 17 06:31:26 PM PDT 24
Finished	Aug 17 06:31:44 PM PDT 24
Peak memory	245020 kb
Host	smart-176be4e9-4d61-4eeb-bd00-494222591f6b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=293908068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.293908068
Directory	/workspace/2.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/2.lc_ctrl_state_post_trans.337674252
Short name	T737
Test name
Test status
Simulation time	67047208 ps
CPU time	10.14 seconds
Started	Aug 17 06:31:29 PM PDT 24
Finished	Aug 17 06:31:40 PM PDT 24
Peak memory	250816 kb
Host	smart-f73de5e5-1021-4fe9-88ec-5471f6e6ca31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=337674252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.337674252
Directory	/workspace/2.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/2.lc_ctrl_stress_all.1513553696
Short name	T492
Test name
Test status
Simulation time	1745548705 ps
CPU time	31.51 seconds
Started	Aug 17 06:31:38 PM PDT 24
Finished	Aug 17 06:32:10 PM PDT 24
Peak memory	225956 kb
Host	smart-e3b6fbdc-d45c-42ec-919c-42e6461876e1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513553696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all.1513553696
Directory	/workspace/2.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.lc_ctrl_alert_test.2988082812
Short name	T289
Test name
Test status
Simulation time	81838128 ps
CPU time	1.08 seconds
Started	Aug 17 06:32:53 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	208924 kb
Host	smart-2a590b26-ef66-4dd7-a8f5-db7f765ac4a6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988082812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2988082812
Directory	/workspace/20.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.lc_ctrl_errors.1590542268
Short name	T462
Test name
Test status
Simulation time	745510660 ps
CPU time	16.52 seconds
Started	Aug 17 06:32:50 PM PDT 24
Finished	Aug 17 06:33:07 PM PDT 24
Peak memory	218276 kb
Host	smart-edef1d79-33b4-4e5e-adc3-3d8721f68d58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1590542268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1590542268
Directory	/workspace/20.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/20.lc_ctrl_jtag_access.9758724
Short name	T625
Test name
Test status
Simulation time	496209690 ps
CPU time	4.12 seconds
Started	Aug 17 06:32:33 PM PDT 24
Finished	Aug 17 06:32:38 PM PDT 24
Peak memory	217100 kb
Host	smart-42f19834-91e0-4bd5-ab9f-ed11bbe065ad
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9758724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.9758724
Directory	/workspace/20.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/20.lc_ctrl_prog_failure.1050276464
Short name	T806
Test name
Test status
Simulation time	56489692 ps
CPU time	2.94 seconds
Started	Aug 17 06:32:38 PM PDT 24
Finished	Aug 17 06:32:41 PM PDT 24
Peak memory	218188 kb
Host	smart-b829816f-a52e-41e8-a72a-1747a9fdaea8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050276464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1050276464
Directory	/workspace/20.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_mubi.2822060839
Short name	T488
Test name
Test status
Simulation time	1157921913 ps
CPU time	16.93 seconds
Started	Aug 17 06:32:37 PM PDT 24
Finished	Aug 17 06:32:54 PM PDT 24
Peak memory	218920 kb
Host	smart-40224a15-018a-4102-8174-19d82951b40e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822060839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2822060839
Directory	/workspace/20.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_digest.1196147779
Short name	T730
Test name
Test status
Simulation time	257503439 ps
CPU time	7.94 seconds
Started	Aug 17 06:32:24 PM PDT 24
Finished	Aug 17 06:32:32 PM PDT 24
Peak memory	225956 kb
Host	smart-9c153327-4109-48a4-9aea-773555a718e3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196147779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d igest.1196147779
Directory	/workspace/20.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/20.lc_ctrl_sec_token_mux.2287755678
Short name	T235
Test name
Test status
Simulation time	1441644054 ps
CPU time	13.38 seconds
Started	Aug 17 06:32:52 PM PDT 24
Finished	Aug 17 06:33:05 PM PDT 24
Peak memory	218164 kb
Host	smart-77697be4-5657-4ded-ab0b-ca807ab52d3c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287755678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux. 2287755678
Directory	/workspace/20.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/20.lc_ctrl_security_escalation.3841220112
Short name	T194
Test name
Test status
Simulation time	1137418496 ps
CPU time	8.98 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:32 PM PDT 24
Peak memory	226060 kb
Host	smart-d0dbd112-1def-44e4-8693-7659e60f85e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841220112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3841220112
Directory	/workspace/20.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/20.lc_ctrl_smoke.3139604365
Short name	T328
Test name
Test status
Simulation time	92738050 ps
CPU time	6.8 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:27 PM PDT 24
Peak memory	217580 kb
Host	smart-8ad3eda9-7a37-4910-946f-8a8875497dba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139604365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3139604365
Directory	/workspace/20.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_failure.1965788734
Short name	T739
Test name
Test status
Simulation time	821873541 ps
CPU time	22.48 seconds
Started	Aug 17 06:32:33 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	250892 kb
Host	smart-3698e8c0-101a-410a-b73f-5add47fbe3a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1965788734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1965788734
Directory	/workspace/20.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/20.lc_ctrl_state_post_trans.2176295603
Short name	T859
Test name
Test status
Simulation time	465277424 ps
CPU time	8.19 seconds
Started	Aug 17 06:32:52 PM PDT 24
Finished	Aug 17 06:33:00 PM PDT 24
Peak memory	250764 kb
Host	smart-897c42f3-a0c6-46c2-b263-4f6ac6566edd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2176295603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2176295603
Directory	/workspace/20.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/20.lc_ctrl_stress_all.3809318117
Short name	T402
Test name
Test status
Simulation time	9574390038 ps
CPU time	54.32 seconds
Started	Aug 17 06:32:27 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	250596 kb
Host	smart-05e8e518-afcc-4590-8d42-7eae963e3791
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809318117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all.3809318117
Directory	/workspace/20.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.3430070601
Short name	T525
Test name
Test status
Simulation time	2191209384 ps
CPU time	80.1 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:33:42 PM PDT 24
Peak memory	251044 kb
Host	smart-675ccfa9-acd8-476e-91ce-385118755364
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3430070601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.3430070601
Directory	/workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1324035033
Short name	T680
Test name
Test status
Simulation time	31163834 ps
CPU time	0.93 seconds
Started	Aug 17 06:32:40 PM PDT 24
Finished	Aug 17 06:32:41 PM PDT 24
Peak memory	211812 kb
Host	smart-3500d00f-9aad-4457-a055-d030b7dde6c1
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324035033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c trl_volatile_unlock_smoke.1324035033
Directory	/workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_alert_test.873570386
Short name	T265
Test name
Test status
Simulation time	21395745 ps
CPU time	1.18 seconds
Started	Aug 17 06:32:34 PM PDT 24
Finished	Aug 17 06:32:37 PM PDT 24
Peak memory	208928 kb
Host	smart-acd27cd4-6da4-41cc-a2dc-fa47a165ce97
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873570386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.873570386
Directory	/workspace/21.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.lc_ctrl_errors.2681868281
Short name	T45
Test name
Test status
Simulation time	879889370 ps
CPU time	10.82 seconds
Started	Aug 17 06:32:25 PM PDT 24
Finished	Aug 17 06:32:35 PM PDT 24
Peak memory	218236 kb
Host	smart-dd641740-d741-4f6c-9fab-b2c9963790ad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2681868281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2681868281
Directory	/workspace/21.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/21.lc_ctrl_jtag_access.2001860555
Short name	T546
Test name
Test status
Simulation time	317607126 ps
CPU time	2.57 seconds
Started	Aug 17 06:32:14 PM PDT 24
Finished	Aug 17 06:32:16 PM PDT 24
Peak memory	216956 kb
Host	smart-91e0f17e-e4d5-48b5-9650-ebb4fb3b86e3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001860555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2001860555
Directory	/workspace/21.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/21.lc_ctrl_prog_failure.598136864
Short name	T672
Test name
Test status
Simulation time	48860818 ps
CPU time	3.22 seconds
Started	Aug 17 06:32:26 PM PDT 24
Finished	Aug 17 06:32:30 PM PDT 24
Peak memory	218232 kb
Host	smart-8e670751-3791-426a-b1e6-ba089a43d4ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=598136864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.598136864
Directory	/workspace/21.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_mubi.1775137120
Short name	T256
Test name
Test status
Simulation time	2098434287 ps
CPU time	14.27 seconds
Started	Aug 17 06:32:39 PM PDT 24
Finished	Aug 17 06:32:54 PM PDT 24
Peak memory	226068 kb
Host	smart-a1862f98-6887-4973-84e8-625fc9c2e55b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775137120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1775137120
Directory	/workspace/21.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_digest.3848093581
Short name	T467
Test name
Test status
Simulation time	1328463215 ps
CPU time	8.98 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:32 PM PDT 24
Peak memory	226176 kb
Host	smart-561e58c4-e512-434e-bbca-d23fbdb4e989
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848093581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d igest.3848093581
Directory	/workspace/21.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/21.lc_ctrl_sec_token_mux.4195462341
Short name	T829
Test name
Test status
Simulation time	315556571 ps
CPU time	11.55 seconds
Started	Aug 17 06:32:40 PM PDT 24
Finished	Aug 17 06:32:51 PM PDT 24
Peak memory	218188 kb
Host	smart-c72214ec-fb6e-4588-852b-35f87fc47ba4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195462341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux. 4195462341
Directory	/workspace/21.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/21.lc_ctrl_security_escalation.995192624
Short name	T866
Test name
Test status
Simulation time	550359969 ps
CPU time	8.79 seconds
Started	Aug 17 06:32:55 PM PDT 24
Finished	Aug 17 06:33:04 PM PDT 24
Peak memory	225396 kb
Host	smart-a5ffb379-fe06-42b4-9cba-1f3faa39d0b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=995192624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.995192624
Directory	/workspace/21.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/21.lc_ctrl_smoke.298948297
Short name	T302
Test name
Test status
Simulation time	127871039 ps
CPU time	1.59 seconds
Started	Aug 17 06:32:48 PM PDT 24
Finished	Aug 17 06:32:49 PM PDT 24
Peak memory	213920 kb
Host	smart-d57556e1-eb42-4233-a11c-f8fca5dc238e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=298948297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.298948297
Directory	/workspace/21.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_failure.3968380434
Short name	T199
Test name
Test status
Simulation time	201781998 ps
CPU time	16.74 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:53 PM PDT 24
Peak memory	250924 kb
Host	smart-df35746c-0649-4bf6-8591-724c42614270
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968380434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3968380434
Directory	/workspace/21.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/21.lc_ctrl_state_post_trans.1603457549
Short name	T489
Test name
Test status
Simulation time	461046494 ps
CPU time	8.09 seconds
Started	Aug 17 06:32:40 PM PDT 24
Finished	Aug 17 06:32:48 PM PDT 24
Peak memory	250864 kb
Host	smart-2f76cba8-2585-4f6d-aeec-8c60c0d29f97
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1603457549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1603457549
Directory	/workspace/21.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/21.lc_ctrl_stress_all.1013555025
Short name	T389
Test name
Test status
Simulation time	4781711747 ps
CPU time	128.53 seconds
Started	Aug 17 06:32:27 PM PDT 24
Finished	Aug 17 06:34:36 PM PDT 24
Peak memory	250632 kb
Host	smart-62f3ac6c-3d19-4f2a-a8fa-19f08660332f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013555025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all.1013555025
Directory	/workspace/21.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1940403158
Short name	T241
Test name
Test status
Simulation time	43954279 ps
CPU time	0.92 seconds
Started	Aug 17 06:32:27 PM PDT 24
Finished	Aug 17 06:32:28 PM PDT 24
Peak memory	211892 kb
Host	smart-67935adc-1c09-4f58-8beb-d17d444175ad
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940403158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c trl_volatile_unlock_smoke.1940403158
Directory	/workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_alert_test.4265376470
Short name	T75
Test name
Test status
Simulation time	23262627 ps
CPU time	1.25 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	208984 kb
Host	smart-b0c4d46a-e013-4701-8e0b-f84434efe2c6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265376470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.4265376470
Directory	/workspace/22.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.lc_ctrl_errors.1782524532
Short name	T508
Test name
Test status
Simulation time	534673123 ps
CPU time	11.79 seconds
Started	Aug 17 06:32:42 PM PDT 24
Finished	Aug 17 06:32:53 PM PDT 24
Peak memory	218224 kb
Host	smart-ea6cb3af-35ab-4265-8d84-f96de0d61a59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782524532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1782524532
Directory	/workspace/22.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/22.lc_ctrl_jtag_access.2540499770
Short name	T35
Test name
Test status
Simulation time	216547307 ps
CPU time	2.06 seconds
Started	Aug 17 06:32:49 PM PDT 24
Finished	Aug 17 06:32:51 PM PDT 24
Peak memory	216960 kb
Host	smart-2beda2b6-d096-4042-beee-69bd604d613f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540499770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2540499770
Directory	/workspace/22.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/22.lc_ctrl_prog_failure.3330479167
Short name	T542
Test name
Test status
Simulation time	63347727 ps
CPU time	1.55 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	218184 kb
Host	smart-ffb9ed9d-69a8-4b1e-aaee-0d0f791951d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330479167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3330479167
Directory	/workspace/22.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_mubi.2345868897
Short name	T242
Test name
Test status
Simulation time	870754219 ps
CPU time	14.28 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:35 PM PDT 24
Peak memory	226104 kb
Host	smart-c09564b5-349d-43c5-a4d5-90d782ec301c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345868897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2345868897
Directory	/workspace/22.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_digest.2972210796
Short name	T873
Test name
Test status
Simulation time	516655902 ps
CPU time	9.95 seconds
Started	Aug 17 06:33:00 PM PDT 24
Finished	Aug 17 06:33:10 PM PDT 24
Peak memory	226016 kb
Host	smart-722c12e6-ef1a-4249-a819-071b1058fe93
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972210796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d igest.2972210796
Directory	/workspace/22.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/22.lc_ctrl_sec_token_mux.991101396
Short name	T846
Test name
Test status
Simulation time	587451635 ps
CPU time	7.17 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:30 PM PDT 24
Peak memory	218192 kb
Host	smart-652d3492-7132-4228-9af1-14c4e62aca59
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991101396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.991101396
Directory	/workspace/22.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/22.lc_ctrl_security_escalation.1763666823
Short name	T584
Test name
Test status
Simulation time	1151266586 ps
CPU time	12.24 seconds
Started	Aug 17 06:32:26 PM PDT 24
Finished	Aug 17 06:32:40 PM PDT 24
Peak memory	218268 kb
Host	smart-91c24b7c-5b12-4e4e-a18f-47b99e6bb5eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1763666823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1763666823
Directory	/workspace/22.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/22.lc_ctrl_smoke.4231006675
Short name	T234
Test name
Test status
Simulation time	49345554 ps
CPU time	2.15 seconds
Started	Aug 17 06:32:54 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	213864 kb
Host	smart-974974db-c7fb-4141-8cc9-b768a2e50d84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4231006675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.4231006675
Directory	/workspace/22.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_failure.2574210881
Short name	T14
Test name
Test status
Simulation time	316379507 ps
CPU time	22.8 seconds
Started	Aug 17 06:32:54 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	250900 kb
Host	smart-d13171b4-c499-4796-ac9a-7393c4855625
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574210881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2574210881
Directory	/workspace/22.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/22.lc_ctrl_state_post_trans.3158763951
Short name	T451
Test name
Test status
Simulation time	110448948 ps
CPU time	10.2 seconds
Started	Aug 17 06:32:52 PM PDT 24
Finished	Aug 17 06:33:02 PM PDT 24
Peak memory	250908 kb
Host	smart-00ffe704-a77c-4aab-a228-ffddf4bf7115
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158763951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3158763951
Directory	/workspace/22.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3770434175
Short name	T671
Test name
Test status
Simulation time	122583998 ps
CPU time	0.98 seconds
Started	Aug 17 06:32:40 PM PDT 24
Finished	Aug 17 06:32:41 PM PDT 24
Peak memory	217676 kb
Host	smart-3682f45f-cf88-4f22-b25b-95d3fbbb2292
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770434175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c trl_volatile_unlock_smoke.3770434175
Directory	/workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_alert_test.1447871508
Short name	T69
Test name
Test status
Simulation time	21023219 ps
CPU time	1.15 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	208876 kb
Host	smart-040d83bd-c9ec-49c0-b3f7-c448e807f9c8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447871508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1447871508
Directory	/workspace/23.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.lc_ctrl_errors.2669069790
Short name	T575
Test name
Test status
Simulation time	1649177356 ps
CPU time	19.52 seconds
Started	Aug 17 06:32:35 PM PDT 24
Finished	Aug 17 06:32:54 PM PDT 24
Peak memory	218292 kb
Host	smart-982379e4-8a2e-4388-bebb-cb16e388605f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2669069790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2669069790
Directory	/workspace/23.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/23.lc_ctrl_jtag_access.2991617140
Short name	T246
Test name
Test status
Simulation time	73601740 ps
CPU time	1.6 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	216996 kb
Host	smart-26ce3bb1-e204-4627-9662-50262398d755
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991617140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2991617140
Directory	/workspace/23.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/23.lc_ctrl_prog_failure.1786159075
Short name	T779
Test name
Test status
Simulation time	180976985 ps
CPU time	2.17 seconds
Started	Aug 17 06:32:32 PM PDT 24
Finished	Aug 17 06:32:34 PM PDT 24
Peak memory	218280 kb
Host	smart-0ebffbcf-c643-47b7-922c-1363c3ac023e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1786159075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1786159075
Directory	/workspace/23.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_mubi.1339733873
Short name	T810
Test name
Test status
Simulation time	537682627 ps
CPU time	18.41 seconds
Started	Aug 17 06:32:46 PM PDT 24
Finished	Aug 17 06:33:05 PM PDT 24
Peak memory	226064 kb
Host	smart-2ab6ec81-1b17-469d-97cc-46f4ab590a43
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339733873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1339733873
Directory	/workspace/23.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_digest.1761878747
Short name	T383
Test name
Test status
Simulation time	2741707838 ps
CPU time	17.38 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:37 PM PDT 24
Peak memory	226048 kb
Host	smart-72137658-f0ef-43d8-8250-a9e7dc6f981d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761878747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d igest.1761878747
Directory	/workspace/23.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/23.lc_ctrl_sec_token_mux.1331802749
Short name	T316
Test name
Test status
Simulation time	903487968 ps
CPU time	8.49 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:29 PM PDT 24
Peak memory	225996 kb
Host	smart-ee141ccc-9a4b-4851-b358-5ee71839b5fb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331802749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux. 1331802749
Directory	/workspace/23.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/23.lc_ctrl_security_escalation.4047003153
Short name	T530
Test name
Test status
Simulation time	829099501 ps
CPU time	9.08 seconds
Started	Aug 17 06:32:32 PM PDT 24
Finished	Aug 17 06:32:45 PM PDT 24
Peak memory	225588 kb
Host	smart-b55a0eea-abba-419e-a1bb-c78e145d5c26
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4047003153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.4047003153
Directory	/workspace/23.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/23.lc_ctrl_smoke.2368041454
Short name	T374
Test name
Test status
Simulation time	23738910 ps
CPU time	1.64 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	217648 kb
Host	smart-2747a462-08ad-4031-9526-799392dc9431
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2368041454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2368041454
Directory	/workspace/23.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_failure.1179025600
Short name	T385
Test name
Test status
Simulation time	140721466 ps
CPU time	19.41 seconds
Started	Aug 17 06:32:25 PM PDT 24
Finished	Aug 17 06:32:44 PM PDT 24
Peak memory	250868 kb
Host	smart-ce78bc02-09cd-4a40-8211-67e9d1a8ac79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1179025600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1179025600
Directory	/workspace/23.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/23.lc_ctrl_state_post_trans.2926751741
Short name	T511
Test name
Test status
Simulation time	211792937 ps
CPU time	9.56 seconds
Started	Aug 17 06:32:57 PM PDT 24
Finished	Aug 17 06:33:07 PM PDT 24
Peak memory	243772 kb
Host	smart-84d5a1dc-5659-429e-9e50-c0a1daeb9c8d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2926751741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2926751741
Directory	/workspace/23.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/23.lc_ctrl_stress_all.1856070651
Short name	T81
Test name
Test status
Simulation time	4457193882 ps
CPU time	171.22 seconds
Started	Aug 17 06:32:25 PM PDT 24
Finished	Aug 17 06:35:16 PM PDT 24
Peak memory	272636 kb
Host	smart-f2f33fd9-7a7c-4644-806c-fb4346a41b85
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856070651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all.1856070651
Directory	/workspace/23.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1227932658
Short name	T185
Test name
Test status
Simulation time	1395291419 ps
CPU time	54.42 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	270884 kb
Host	smart-3b398049-1aa3-427e-9baa-24f0c5ba6504
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1227932658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.1227932658
Directory	/workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3622330972
Short name	T785
Test name
Test status
Simulation time	11627874 ps
CPU time	0.88 seconds
Started	Aug 17 06:32:45 PM PDT 24
Finished	Aug 17 06:32:46 PM PDT 24
Peak memory	211872 kb
Host	smart-8939e007-8c16-4d0c-9932-df0bfee43a4c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622330972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c trl_volatile_unlock_smoke.3622330972
Directory	/workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_alert_test.665446443
Short name	T689
Test name
Test status
Simulation time	17734864 ps
CPU time	1.14 seconds
Started	Aug 17 06:32:25 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	208944 kb
Host	smart-c08114b2-ab4a-4113-b081-6f14ba2b35b7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665446443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.665446443
Directory	/workspace/24.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.lc_ctrl_errors.3263725886
Short name	T353
Test name
Test status
Simulation time	523604736 ps
CPU time	8.89 seconds
Started	Aug 17 06:32:35 PM PDT 24
Finished	Aug 17 06:32:44 PM PDT 24
Peak memory	226048 kb
Host	smart-cd215c03-31de-48da-b76c-8590afd393de
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263725886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3263725886
Directory	/workspace/24.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/24.lc_ctrl_jtag_access.1485434907
Short name	T592
Test name
Test status
Simulation time	370830519 ps
CPU time	6.31 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:29 PM PDT 24
Peak memory	217096 kb
Host	smart-0ed916f7-fe34-4032-976a-2574be8be0db
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485434907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1485434907
Directory	/workspace/24.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/24.lc_ctrl_prog_failure.3229404731
Short name	T862
Test name
Test status
Simulation time	39016315 ps
CPU time	1.94 seconds
Started	Aug 17 06:32:24 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	222080 kb
Host	smart-a2d53d62-95e8-4e27-8a14-7eb5fa78f517
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229404731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3229404731
Directory	/workspace/24.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_mubi.2881198382
Short name	T761
Test name
Test status
Simulation time	2234615142 ps
CPU time	15.8 seconds
Started	Aug 17 06:32:24 PM PDT 24
Finished	Aug 17 06:32:40 PM PDT 24
Peak memory	226048 kb
Host	smart-a4562c12-bc23-4652-9da9-1c6d591a90d2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881198382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2881198382
Directory	/workspace/24.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_digest.3724424089
Short name	T286
Test name
Test status
Simulation time	329300133 ps
CPU time	10.38 seconds
Started	Aug 17 06:32:30 PM PDT 24
Finished	Aug 17 06:32:40 PM PDT 24
Peak memory	225932 kb
Host	smart-c903b579-6201-49e8-aa29-b486f8d0f5be
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724424089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d igest.3724424089
Directory	/workspace/24.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/24.lc_ctrl_sec_token_mux.509482109
Short name	T631
Test name
Test status
Simulation time	1651876415 ps
CPU time	10.42 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:33 PM PDT 24
Peak memory	225968 kb
Host	smart-fe71e5c9-8756-40ea-acad-1f52c7b6d908
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509482109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.509482109
Directory	/workspace/24.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/24.lc_ctrl_security_escalation.457132525
Short name	T760
Test name
Test status
Simulation time	235569655 ps
CPU time	8.98 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:32 PM PDT 24
Peak memory	218320 kb
Host	smart-4485fd1d-044a-4bcc-9188-b5de2a68c324
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=457132525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.457132525
Directory	/workspace/24.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/24.lc_ctrl_smoke.3718484575
Short name	T637
Test name
Test status
Simulation time	221637265 ps
CPU time	2.03 seconds
Started	Aug 17 06:32:50 PM PDT 24
Finished	Aug 17 06:32:53 PM PDT 24
Peak memory	217644 kb
Host	smart-c13c5626-2fb8-4ab5-8bbb-f73949fb979e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718484575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3718484575
Directory	/workspace/24.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_failure.671206243
Short name	T424
Test name
Test status
Simulation time	351590468 ps
CPU time	23.01 seconds
Started	Aug 17 06:32:37 PM PDT 24
Finished	Aug 17 06:33:00 PM PDT 24
Peak memory	250900 kb
Host	smart-8e1fd28e-d6fb-45da-b1da-ce5e7b8f5590
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=671206243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.671206243
Directory	/workspace/24.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/24.lc_ctrl_state_post_trans.3813393100
Short name	T771
Test name
Test status
Simulation time	241191291 ps
CPU time	7.47 seconds
Started	Aug 17 06:32:27 PM PDT 24
Finished	Aug 17 06:32:35 PM PDT 24
Peak memory	250888 kb
Host	smart-c09480c2-3b50-464e-b8e0-858b00c7d30b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3813393100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3813393100
Directory	/workspace/24.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/24.lc_ctrl_stress_all.58925729
Short name	T364
Test name
Test status
Simulation time	1315706920 ps
CPU time	57.67 seconds
Started	Aug 17 06:32:54 PM PDT 24
Finished	Aug 17 06:33:51 PM PDT 24
Peak memory	268900 kb
Host	smart-4bca041e-aa78-4dbf-add5-085e2d70b402
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58925729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.lc_ctrl_stress_all.58925729
Directory	/workspace/24.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.707051456
Short name	T700
Test name
Test status
Simulation time	36823951 ps
CPU time	0.93 seconds
Started	Aug 17 06:32:37 PM PDT 24
Finished	Aug 17 06:32:38 PM PDT 24
Peak memory	211916 kb
Host	smart-dbc3f044-882a-4803-9caa-6d032e052d3c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707051456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct rl_volatile_unlock_smoke.707051456
Directory	/workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_alert_test.99002742
Short name	T505
Test name
Test status
Simulation time	13566734 ps
CPU time	0.81 seconds
Started	Aug 17 06:32:45 PM PDT 24
Finished	Aug 17 06:32:46 PM PDT 24
Peak memory	208656 kb
Host	smart-bf877c3c-ff2f-456b-b560-17aa04f9c885
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99002742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.99002742
Directory	/workspace/25.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.lc_ctrl_errors.842994742
Short name	T261
Test name
Test status
Simulation time	1206018916 ps
CPU time	13.65 seconds
Started	Aug 17 06:32:31 PM PDT 24
Finished	Aug 17 06:32:44 PM PDT 24
Peak memory	218260 kb
Host	smart-bacf98b2-aead-4431-ac95-66fe7cdd4e0b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=842994742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.842994742
Directory	/workspace/25.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/25.lc_ctrl_jtag_access.1349369906
Short name	T728
Test name
Test status
Simulation time	35410184 ps
CPU time	1.14 seconds
Started	Aug 17 06:32:47 PM PDT 24
Finished	Aug 17 06:32:49 PM PDT 24
Peak memory	216928 kb
Host	smart-143ce952-ef78-4c60-9450-477e4a0f90d4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349369906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1349369906
Directory	/workspace/25.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/25.lc_ctrl_prog_failure.3257045351
Short name	T230
Test name
Test status
Simulation time	69743538 ps
CPU time	2.81 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	222604 kb
Host	smart-c115b1b4-375e-46ac-89c9-d4b6662cb0ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257045351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3257045351
Directory	/workspace/25.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_mubi.3747374104
Short name	T296
Test name
Test status
Simulation time	393208974 ps
CPU time	15.1 seconds
Started	Aug 17 06:32:46 PM PDT 24
Finished	Aug 17 06:33:01 PM PDT 24
Peak memory	226072 kb
Host	smart-b262a1a8-2b13-4110-acb1-c0236307e214
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747374104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3747374104
Directory	/workspace/25.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_digest.492891583
Short name	T567
Test name
Test status
Simulation time	334611203 ps
CPU time	10.18 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:38 PM PDT 24
Peak memory	226004 kb
Host	smart-0b8059a2-46a2-48c7-8458-f75790643933
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492891583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di gest.492891583
Directory	/workspace/25.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/25.lc_ctrl_sec_token_mux.3470956837
Short name	T250
Test name
Test status
Simulation time	248171743 ps
CPU time	10 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:33 PM PDT 24
Peak memory	226008 kb
Host	smart-ac48317e-0acb-45aa-b566-ff7e697ef88e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470956837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux. 3470956837
Directory	/workspace/25.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/25.lc_ctrl_security_escalation.177758934
Short name	T847
Test name
Test status
Simulation time	410666622 ps
CPU time	11.6 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:33 PM PDT 24
Peak memory	218352 kb
Host	smart-761273ed-ba94-406e-8052-de8df886fc41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177758934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.177758934
Directory	/workspace/25.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/25.lc_ctrl_smoke.4283802916
Short name	T305
Test name
Test status
Simulation time	23135022 ps
CPU time	1.12 seconds
Started	Aug 17 06:32:29 PM PDT 24
Finished	Aug 17 06:32:30 PM PDT 24
Peak memory	217532 kb
Host	smart-b1911654-30b7-4ce3-8e0b-23d6b963e97e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283802916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.4283802916
Directory	/workspace/25.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_failure.772113855
Short name	T232
Test name
Test status
Simulation time	793794501 ps
CPU time	20.19 seconds
Started	Aug 17 06:32:42 PM PDT 24
Finished	Aug 17 06:33:02 PM PDT 24
Peak memory	250900 kb
Host	smart-5f63a255-3dc2-453f-a8cc-cf74f11f385d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772113855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.772113855
Directory	/workspace/25.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/25.lc_ctrl_state_post_trans.2665539006
Short name	T460
Test name
Test status
Simulation time	60893896 ps
CPU time	6.84 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:30 PM PDT 24
Peak memory	250416 kb
Host	smart-beaeb290-743b-4412-9b7a-479063b9c487
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2665539006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2665539006
Directory	/workspace/25.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/25.lc_ctrl_stress_all.3419635478
Short name	T612
Test name
Test status
Simulation time	2682500884 ps
CPU time	18.57 seconds
Started	Aug 17 06:32:32 PM PDT 24
Finished	Aug 17 06:32:51 PM PDT 24
Peak memory	226804 kb
Host	smart-1396a42e-2023-4187-a10f-21482305c4b3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419635478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all.3419635478
Directory	/workspace/25.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.422938246
Short name	T133
Test name
Test status
Simulation time	1666608620 ps
CPU time	67.14 seconds
Started	Aug 17 06:32:31 PM PDT 24
Finished	Aug 17 06:33:38 PM PDT 24
Peak memory	251012 kb
Host	smart-a43ce624-fd8f-4235-9eba-9f33e5e696b9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=422938246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.422938246
Directory	/workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2902852340
Short name	T368
Test name
Test status
Simulation time	63333459 ps
CPU time	0.81 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	211788 kb
Host	smart-a27ede7b-136d-4270-8843-8ce4d5fdfab6
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902852340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c trl_volatile_unlock_smoke.2902852340
Directory	/workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/26.lc_ctrl_errors.2680022109
Short name	T861
Test name
Test status
Simulation time	548230691 ps
CPU time	21.44 seconds
Started	Aug 17 06:32:53 PM PDT 24
Finished	Aug 17 06:33:15 PM PDT 24
Peak memory	218296 kb
Host	smart-d8f614c5-465f-41fd-b792-0e20e4343c9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2680022109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2680022109
Directory	/workspace/26.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/26.lc_ctrl_jtag_access.1666742420
Short name	T854
Test name
Test status
Simulation time	2592977538 ps
CPU time	9.2 seconds
Started	Aug 17 06:32:22 PM PDT 24
Finished	Aug 17 06:32:31 PM PDT 24
Peak memory	217628 kb
Host	smart-deacf838-50d2-428e-8501-bb9d037e6497
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666742420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1666742420
Directory	/workspace/26.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/26.lc_ctrl_prog_failure.2480621998
Short name	T608
Test name
Test status
Simulation time	89745465 ps
CPU time	4.22 seconds
Started	Aug 17 06:32:36 PM PDT 24
Finished	Aug 17 06:32:40 PM PDT 24
Peak memory	218256 kb
Host	smart-c3659a53-834f-4db9-a859-caacf314de81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480621998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.2480621998
Directory	/workspace/26.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_mubi.1400217815
Short name	T293
Test name
Test status
Simulation time	3351096349 ps
CPU time	10.5 seconds
Started	Aug 17 06:32:59 PM PDT 24
Finished	Aug 17 06:33:10 PM PDT 24
Peak memory	226128 kb
Host	smart-a2c3b62c-6964-4cac-a7e6-b52b58cc25b3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400217815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1400217815
Directory	/workspace/26.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_digest.2636465072
Short name	T674
Test name
Test status
Simulation time	1643990634 ps
CPU time	10.75 seconds
Started	Aug 17 06:32:44 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	225992 kb
Host	smart-8723173a-4e7b-4ff0-b6db-1fe5245a120e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636465072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d igest.2636465072
Directory	/workspace/26.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/26.lc_ctrl_sec_token_mux.3385902298
Short name	T440
Test name
Test status
Simulation time	1335111186 ps
CPU time	7.47 seconds
Started	Aug 17 06:32:37 PM PDT 24
Finished	Aug 17 06:32:45 PM PDT 24
Peak memory	225868 kb
Host	smart-1f1b1cc5-6fa0-434e-95b1-d13469b8f24a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385902298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux. 3385902298
Directory	/workspace/26.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/26.lc_ctrl_security_escalation.2661665846
Short name	T197
Test name
Test status
Simulation time	4846194996 ps
CPU time	7.52 seconds
Started	Aug 17 06:32:47 PM PDT 24
Finished	Aug 17 06:32:54 PM PDT 24
Peak memory	225660 kb
Host	smart-8a8a3cc3-e5f4-41f1-9a19-0e4d6348d475
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661665846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2661665846
Directory	/workspace/26.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_failure.426082497
Short name	T589
Test name
Test status
Simulation time	1296206191 ps
CPU time	28.91 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:32:47 PM PDT 24
Peak memory	250720 kb
Host	smart-59562c29-ae5e-45c6-aef7-6dbe4b0f18c3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426082497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.426082497
Directory	/workspace/26.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/26.lc_ctrl_state_post_trans.1507784271
Short name	T407
Test name
Test status
Simulation time	365941959 ps
CPU time	3.48 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	222684 kb
Host	smart-4e736cf9-50eb-440d-b411-47e2f7c9e843
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1507784271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1507784271
Directory	/workspace/26.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/26.lc_ctrl_stress_all.3261354534
Short name	T149
Test name
Test status
Simulation time	5680623885 ps
CPU time	129.3 seconds
Started	Aug 17 06:32:39 PM PDT 24
Finished	Aug 17 06:34:49 PM PDT 24
Peak memory	267304 kb
Host	smart-bfae0d86-5b17-4673-8b29-ab2ddb212338
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261354534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all.3261354534
Directory	/workspace/26.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.3022725037
Short name	T571
Test name
Test status
Simulation time	2979352034 ps
CPU time	111.34 seconds
Started	Aug 17 06:32:39 PM PDT 24
Finished	Aug 17 06:34:30 PM PDT 24
Peak memory	272660 kb
Host	smart-e6cc5f85-8e36-4261-8af9-e52d81393ede
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3022725037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.3022725037
Directory	/workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1271960349
Short name	T191
Test name
Test status
Simulation time	21959859 ps
CPU time	1 seconds
Started	Aug 17 06:32:30 PM PDT 24
Finished	Aug 17 06:32:32 PM PDT 24
Peak memory	212864 kb
Host	smart-8a28dda5-dd5e-4352-9216-c5546f1700dd
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271960349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c trl_volatile_unlock_smoke.1271960349
Directory	/workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_alert_test.3786297383
Short name	T718
Test name
Test status
Simulation time	30475403 ps
CPU time	0.86 seconds
Started	Aug 17 06:32:58 PM PDT 24
Finished	Aug 17 06:32:59 PM PDT 24
Peak memory	209236 kb
Host	smart-74352779-fec9-4be8-aa89-975c00c73203
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786297383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3786297383
Directory	/workspace/27.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.lc_ctrl_errors.512885682
Short name	T272
Test name
Test status
Simulation time	1084330035 ps
CPU time	14.47 seconds
Started	Aug 17 06:32:41 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	218220 kb
Host	smart-7438a54d-5556-49d7-b3e2-d2918378579f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512885682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.512885682
Directory	/workspace/27.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/27.lc_ctrl_jtag_access.2220728093
Short name	T557
Test name
Test status
Simulation time	367392005 ps
CPU time	4.82 seconds
Started	Aug 17 06:32:35 PM PDT 24
Finished	Aug 17 06:32:40 PM PDT 24
Peak memory	217088 kb
Host	smart-d73a6c06-02c5-4f1b-800d-f02a2c09347e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220728093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2220728093
Directory	/workspace/27.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/27.lc_ctrl_prog_failure.2793187491
Short name	T433
Test name
Test status
Simulation time	77251902 ps
CPU time	4.03 seconds
Started	Aug 17 06:32:57 PM PDT 24
Finished	Aug 17 06:33:01 PM PDT 24
Peak memory	218268 kb
Host	smart-28bb5dc9-f495-42c4-9a8f-17706841deba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793187491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2793187491
Directory	/workspace/27.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_mubi.2286075082
Short name	T745
Test name
Test status
Simulation time	522461385 ps
CPU time	19.02 seconds
Started	Aug 17 06:32:36 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	218924 kb
Host	smart-0f309342-8696-4048-8086-5027cf75bce6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286075082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2286075082
Directory	/workspace/27.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_digest.3718430100
Short name	T449
Test name
Test status
Simulation time	281405342 ps
CPU time	9.43 seconds
Started	Aug 17 06:32:45 PM PDT 24
Finished	Aug 17 06:32:54 PM PDT 24
Peak memory	225904 kb
Host	smart-67d0a198-1d47-4c28-9f33-0537e25ac31f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718430100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d igest.3718430100
Directory	/workspace/27.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/27.lc_ctrl_sec_token_mux.917652980
Short name	T531
Test name
Test status
Simulation time	2131137301 ps
CPU time	10.14 seconds
Started	Aug 17 06:32:39 PM PDT 24
Finished	Aug 17 06:32:49 PM PDT 24
Peak memory	226020 kb
Host	smart-630a0373-43e3-491f-a5d5-1ea9280df9cf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917652980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.917652980
Directory	/workspace/27.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/27.lc_ctrl_security_escalation.3366111334
Short name	T470
Test name
Test status
Simulation time	581476619 ps
CPU time	7.9 seconds
Started	Aug 17 06:32:38 PM PDT 24
Finished	Aug 17 06:32:46 PM PDT 24
Peak memory	226076 kb
Host	smart-8833a5ad-3174-4855-9f32-065ad8b5c522
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3366111334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3366111334
Directory	/workspace/27.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/27.lc_ctrl_smoke.893835000
Short name	T678
Test name
Test status
Simulation time	71549778 ps
CPU time	1.67 seconds
Started	Aug 17 06:32:54 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	213808 kb
Host	smart-cc0ae61e-126a-4a2b-8df0-5954ec53f789
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=893835000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.893835000
Directory	/workspace/27.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_failure.2831003117
Short name	T292
Test name
Test status
Simulation time	519174639 ps
CPU time	26.64 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:47 PM PDT 24
Peak memory	250880 kb
Host	smart-bc4156bb-b3f8-441c-a429-2f66a2d32a94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831003117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2831003117
Directory	/workspace/27.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/27.lc_ctrl_state_post_trans.868587446
Short name	T667
Test name
Test status
Simulation time	820992238 ps
CPU time	6.82 seconds
Started	Aug 17 06:32:50 PM PDT 24
Finished	Aug 17 06:32:57 PM PDT 24
Peak memory	250724 kb
Host	smart-d601a4f5-bc90-4279-bfbb-31e300eb8ef9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868587446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.868587446
Directory	/workspace/27.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/27.lc_ctrl_stress_all.3389199624
Short name	T308
Test name
Test status
Simulation time	2370413432 ps
CPU time	63.56 seconds
Started	Aug 17 06:32:44 PM PDT 24
Finished	Aug 17 06:33:48 PM PDT 24
Peak memory	251052 kb
Host	smart-d4b466a7-7f9e-435e-9fc5-9a652ccfb86b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389199624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all.3389199624
Directory	/workspace/27.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2975668585
Short name	T618
Test name
Test status
Simulation time	30993796 ps
CPU time	0.71 seconds
Started	Aug 17 06:32:27 PM PDT 24
Finished	Aug 17 06:32:28 PM PDT 24
Peak memory	207020 kb
Host	smart-568ab7f6-915a-4e70-ba91-51a9532331cf
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975668585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c trl_volatile_unlock_smoke.2975668585
Directory	/workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_alert_test.1351542926
Short name	T868
Test name
Test status
Simulation time	17944032 ps
CPU time	0.9 seconds
Started	Aug 17 06:32:53 PM PDT 24
Finished	Aug 17 06:32:54 PM PDT 24
Peak memory	208788 kb
Host	smart-484fb7b0-84cf-422a-ba6a-e8212febb6a0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351542926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1351542926
Directory	/workspace/28.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.lc_ctrl_errors.571525895
Short name	T752
Test name
Test status
Simulation time	1610838545 ps
CPU time	10.79 seconds
Started	Aug 17 06:32:40 PM PDT 24
Finished	Aug 17 06:32:51 PM PDT 24
Peak memory	226068 kb
Host	smart-dbecc0d5-6efd-42ac-9be8-0c16c6f70fb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=571525895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.571525895
Directory	/workspace/28.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/28.lc_ctrl_jtag_access.1697184792
Short name	T807
Test name
Test status
Simulation time	424399615 ps
CPU time	10.96 seconds
Started	Aug 17 06:32:58 PM PDT 24
Finished	Aug 17 06:33:09 PM PDT 24
Peak memory	217500 kb
Host	smart-fcb8d3e9-7e05-4924-bcbb-0d9c3beb3c3e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697184792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1697184792
Directory	/workspace/28.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/28.lc_ctrl_prog_failure.2596640882
Short name	T380
Test name
Test status
Simulation time	47861259 ps
CPU time	2.81 seconds
Started	Aug 17 06:32:40 PM PDT 24
Finished	Aug 17 06:32:43 PM PDT 24
Peak memory	222316 kb
Host	smart-8640c9cb-24e2-4dec-b05d-c17c2b9cec7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596640882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2596640882
Directory	/workspace/28.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_mubi.3127252300
Short name	T458
Test name
Test status
Simulation time	686011436 ps
CPU time	17.51 seconds
Started	Aug 17 06:32:45 PM PDT 24
Finished	Aug 17 06:33:03 PM PDT 24
Peak memory	218344 kb
Host	smart-ad144597-23ad-4ccd-9079-838740b27906
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127252300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3127252300
Directory	/workspace/28.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_digest.2519614087
Short name	T564
Test name
Test status
Simulation time	484319423 ps
CPU time	16.54 seconds
Started	Aug 17 06:32:44 PM PDT 24
Finished	Aug 17 06:33:01 PM PDT 24
Peak memory	225980 kb
Host	smart-a557807e-283d-4600-8be1-8cb56faec3bd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519614087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d igest.2519614087
Directory	/workspace/28.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/28.lc_ctrl_sec_token_mux.1096925512
Short name	T22
Test name
Test status
Simulation time	367127512 ps
CPU time	14.07 seconds
Started	Aug 17 06:32:41 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	225572 kb
Host	smart-bf9f412f-aec8-4798-a6e1-ce43b2193c73
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096925512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux. 1096925512
Directory	/workspace/28.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/28.lc_ctrl_security_escalation.4278682183
Short name	T788
Test name
Test status
Simulation time	1260977507 ps
CPU time	10.96 seconds
Started	Aug 17 06:33:03 PM PDT 24
Finished	Aug 17 06:33:14 PM PDT 24
Peak memory	225624 kb
Host	smart-285f74f5-6230-4a23-b616-07208ebfd556
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278682183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.4278682183
Directory	/workspace/28.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/28.lc_ctrl_smoke.877694170
Short name	T64
Test name
Test status
Simulation time	82609420 ps
CPU time	1.55 seconds
Started	Aug 17 06:32:54 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	213668 kb
Host	smart-4b593cd5-97a5-49f4-b577-76af1c3384bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877694170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.877694170
Directory	/workspace/28.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_failure.3643095300
Short name	T494
Test name
Test status
Simulation time	603912291 ps
CPU time	24.72 seconds
Started	Aug 17 06:32:23 PM PDT 24
Finished	Aug 17 06:32:48 PM PDT 24
Peak memory	250900 kb
Host	smart-eb0eb23a-a383-4042-b363-f41c72c3b8fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3643095300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3643095300
Directory	/workspace/28.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/28.lc_ctrl_state_post_trans.1332020454
Short name	T213
Test name
Test status
Simulation time	254588831 ps
CPU time	2.94 seconds
Started	Aug 17 06:32:29 PM PDT 24
Finished	Aug 17 06:32:32 PM PDT 24
Peak memory	218200 kb
Host	smart-6d96dcab-f027-47af-85c2-4697d70930c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332020454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1332020454
Directory	/workspace/28.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all.972586767
Short name	T547
Test name
Test status
Simulation time	1023152715 ps
CPU time	22.66 seconds
Started	Aug 17 06:32:33 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	226056 kb
Host	smart-29f39501-8abb-4de3-8a36-f177713112c9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972586767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all.972586767
Directory	/workspace/28.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2590479589
Short name	T775
Test name
Test status
Simulation time	49213993551 ps
CPU time	78.93 seconds
Started	Aug 17 06:32:52 PM PDT 24
Finished	Aug 17 06:34:11 PM PDT 24
Peak memory	251052 kb
Host	smart-3fb6393f-6b08-4772-818b-9c1f1665c82f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2590479589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.2590479589
Directory	/workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.4165588585
Short name	T423
Test name
Test status
Simulation time	21969671 ps
CPU time	0.89 seconds
Started	Aug 17 06:32:56 PM PDT 24
Finished	Aug 17 06:32:57 PM PDT 24
Peak memory	211924 kb
Host	smart-ba70ee9c-88c6-411d-8e8e-6a6270070fa9
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165588585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c trl_volatile_unlock_smoke.4165588585
Directory	/workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_alert_test.3267143557
Short name	T471
Test name
Test status
Simulation time	52099141 ps
CPU time	1.01 seconds
Started	Aug 17 06:32:53 PM PDT 24
Finished	Aug 17 06:32:54 PM PDT 24
Peak memory	209072 kb
Host	smart-7b45fe07-83a8-44e4-a80b-5298b4e89e6d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267143557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3267143557
Directory	/workspace/29.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.lc_ctrl_errors.2046993151
Short name	T20
Test name
Test status
Simulation time	372117571 ps
CPU time	17.06 seconds
Started	Aug 17 06:32:47 PM PDT 24
Finished	Aug 17 06:33:04 PM PDT 24
Peak memory	226092 kb
Host	smart-e3a09bbf-48fd-48f7-83d0-6e2a2af4ef6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046993151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2046993151
Directory	/workspace/29.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/29.lc_ctrl_jtag_access.4044367428
Short name	T848
Test name
Test status
Simulation time	497906486 ps
CPU time	6.77 seconds
Started	Aug 17 06:32:48 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	217024 kb
Host	smart-3761eb1b-8c75-44e0-af3b-783bc11267b4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044367428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.4044367428
Directory	/workspace/29.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/29.lc_ctrl_prog_failure.1563697467
Short name	T863
Test name
Test status
Simulation time	223167082 ps
CPU time	2.43 seconds
Started	Aug 17 06:32:51 PM PDT 24
Finished	Aug 17 06:32:54 PM PDT 24
Peak memory	218268 kb
Host	smart-80ab1c32-6fa6-4878-870c-56b7f0711cc5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1563697467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1563697467
Directory	/workspace/29.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_mubi.185825492
Short name	T731
Test name
Test status
Simulation time	293652878 ps
CPU time	13.74 seconds
Started	Aug 17 06:32:48 PM PDT 24
Finished	Aug 17 06:33:02 PM PDT 24
Peak memory	218352 kb
Host	smart-6261939c-1dd0-4375-b752-f4d56d19e87a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185825492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.185825492
Directory	/workspace/29.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_digest.3579805999
Short name	T294
Test name
Test status
Simulation time	1057114885 ps
CPU time	12.15 seconds
Started	Aug 17 06:32:39 PM PDT 24
Finished	Aug 17 06:32:51 PM PDT 24
Peak memory	226000 kb
Host	smart-8880d1df-bc6b-44b7-8c26-d0d12dc833df
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579805999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d igest.3579805999
Directory	/workspace/29.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/29.lc_ctrl_sec_token_mux.2444051648
Short name	T140
Test name
Test status
Simulation time	850510799 ps
CPU time	10.92 seconds
Started	Aug 17 06:32:50 PM PDT 24
Finished	Aug 17 06:33:01 PM PDT 24
Peak memory	218232 kb
Host	smart-d6c8062e-8d8d-4e32-9dc0-0dffdebb5d0c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444051648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux. 2444051648
Directory	/workspace/29.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/29.lc_ctrl_security_escalation.2247749565
Short name	T154
Test name
Test status
Simulation time	260887747 ps
CPU time	9.3 seconds
Started	Aug 17 06:32:46 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	226064 kb
Host	smart-9446c336-0109-4aae-8c15-8c25bf310593
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2247749565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2247749565
Directory	/workspace/29.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/29.lc_ctrl_smoke.1816637227
Short name	T610
Test name
Test status
Simulation time	22300127 ps
CPU time	1.18 seconds
Started	Aug 17 06:33:01 PM PDT 24
Finished	Aug 17 06:33:02 PM PDT 24
Peak memory	217656 kb
Host	smart-d66f3d08-14b3-4661-9976-5800712807fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1816637227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1816637227
Directory	/workspace/29.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_failure.2084092129
Short name	T534
Test name
Test status
Simulation time	324698384 ps
CPU time	29.98 seconds
Started	Aug 17 06:32:51 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	250876 kb
Host	smart-90c12e48-90ce-4c33-9f99-8a69aa79074e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2084092129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2084092129
Directory	/workspace/29.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/29.lc_ctrl_state_post_trans.1858775740
Short name	T414
Test name
Test status
Simulation time	862635817 ps
CPU time	7.66 seconds
Started	Aug 17 06:32:30 PM PDT 24
Finished	Aug 17 06:32:38 PM PDT 24
Peak memory	247060 kb
Host	smart-a8f9a296-822b-4f1e-a4aa-3c1c56432f91
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858775740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1858775740
Directory	/workspace/29.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/29.lc_ctrl_stress_all.1991117245
Short name	T778
Test name
Test status
Simulation time	3151243397 ps
CPU time	83.36 seconds
Started	Aug 17 06:32:55 PM PDT 24
Finished	Aug 17 06:34:18 PM PDT 24
Peak memory	250928 kb
Host	smart-8ddf8d69-cfc2-4bc6-bcc2-a54b64d799f0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991117245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all.1991117245
Directory	/workspace/29.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3539947568
Short name	T833
Test name
Test status
Simulation time	20088476 ps
CPU time	0.98 seconds
Started	Aug 17 06:32:55 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	211864 kb
Host	smart-97b48216-ae99-4ab6-8d8d-75ef232b5d58
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539947568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c trl_volatile_unlock_smoke.3539947568
Directory	/workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_alert_test.230886959
Short name	T497
Test name
Test status
Simulation time	40578906 ps
CPU time	1.01 seconds
Started	Aug 17 06:31:53 PM PDT 24
Finished	Aug 17 06:31:54 PM PDT 24
Peak memory	208848 kb
Host	smart-0e3f9ecf-cd5f-4ea8-80dd-4416b238a6a2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230886959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.230886959
Directory	/workspace/3.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.lc_ctrl_claim_transition_if.3741017505
Short name	T483
Test name
Test status
Simulation time	10977145 ps
CPU time	0.8 seconds
Started	Aug 17 06:31:54 PM PDT 24
Finished	Aug 17 06:31:55 PM PDT 24
Peak memory	208564 kb
Host	smart-a7398a4f-a9bd-4555-afe6-bcb4c66918a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3741017505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3741017505
Directory	/workspace/3.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/3.lc_ctrl_errors.731699337
Short name	T18
Test name
Test status
Simulation time	359870496 ps
CPU time	16.59 seconds
Started	Aug 17 06:31:37 PM PDT 24
Finished	Aug 17 06:31:54 PM PDT 24
Peak memory	218276 kb
Host	smart-0c19509e-7fc2-486e-a0dd-231b65979c62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=731699337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.731699337
Directory	/workspace/3.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_access.1861735186
Short name	T39
Test name
Test status
Simulation time	3661639885 ps
CPU time	9.29 seconds
Started	Aug 17 06:31:49 PM PDT 24
Finished	Aug 17 06:31:58 PM PDT 24
Peak memory	217660 kb
Host	smart-c18bc96d-6777-4478-bcef-17afc59e8f28
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861735186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1861735186
Directory	/workspace/3.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_errors.1940865004
Short name	T243
Test name
Test status
Simulation time	4266644813 ps
CPU time	53.47 seconds
Started	Aug 17 06:31:25 PM PDT 24
Finished	Aug 17 06:32:20 PM PDT 24
Peak memory	219876 kb
Host	smart-ef2a125d-86b9-4ec1-a975-270e7ee50ff0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940865004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er rors.1940865004
Directory	/workspace/3.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_priority.1835334824
Short name	T763
Test name
Test status
Simulation time	397049721 ps
CPU time	9.85 seconds
Started	Aug 17 06:32:12 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	217572 kb
Host	smart-e5c84818-423e-488d-ab07-41c2f06fde65
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835334824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1 835334824
Directory	/workspace/3.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1868348387
Short name	T139
Test name
Test status
Simulation time	100829707 ps
CPU time	3.89 seconds
Started	Aug 17 06:32:13 PM PDT 24
Finished	Aug 17 06:32:17 PM PDT 24
Peak memory	221916 kb
Host	smart-0e7a62cd-fc58-4382-a151-e61de2e841be
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868348387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag _prog_failure.1868348387
Directory	/workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3651710289
Short name	T733
Test name
Test status
Simulation time	4302636291 ps
CPU time	23.77 seconds
Started	Aug 17 06:31:49 PM PDT 24
Finished	Aug 17 06:32:13 PM PDT 24
Peak memory	217612 kb
Host	smart-30e91116-9ef2-4d13-802d-3fd7c159c384
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651710289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_regwen_during_op.3651710289
Directory	/workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_smoke.1181694055
Short name	T212
Test name
Test status
Simulation time	1526419603 ps
CPU time	8.07 seconds
Started	Aug 17 06:31:34 PM PDT 24
Finished	Aug 17 06:31:42 PM PDT 24
Peak memory	217524 kb
Host	smart-0b402d31-e160-4fa2-87ab-eb710425ae2c
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181694055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke. 1181694055
Directory	/workspace/3.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2704505431
Short name	T799
Test name
Test status
Simulation time	1920373586 ps
CPU time	64.95 seconds
Started	Aug 17 06:32:08 PM PDT 24
Finished	Aug 17 06:33:13 PM PDT 24
Peak memory	275408 kb
Host	smart-c9ab18a8-439f-411b-81d7-06f8e56359e6
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704505431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta g_state_failure.2704505431
Directory	/workspace/3.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3578809409
Short name	T685
Test name
Test status
Simulation time	315158153 ps
CPU time	13.25 seconds
Started	Aug 17 06:31:44 PM PDT 24
Finished	Aug 17 06:31:58 PM PDT 24
Peak memory	246512 kb
Host	smart-e0da5fe4-53cf-4869-901a-29edce2fe636
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578809409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_state_post_trans.3578809409
Directory	/workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_prog_failure.1326016293
Short name	T519
Test name
Test status
Simulation time	52833881 ps
CPU time	2.82 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	222316 kb
Host	smart-73795aaa-07b1-4b54-85c2-689fd72010c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1326016293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1326016293
Directory	/workspace/3.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_regwen_during_op.3374052826
Short name	T439
Test name
Test status
Simulation time	457973423 ps
CPU time	15.51 seconds
Started	Aug 17 06:31:58 PM PDT 24
Finished	Aug 17 06:32:14 PM PDT 24
Peak memory	214572 kb
Host	smart-bcf3de77-bffb-498b-8db0-b68be26a5f63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3374052826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3374052826
Directory	/workspace/3.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_cm.4291383394
Short name	T55
Test name
Test status
Simulation time	212647042 ps
CPU time	36.1 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	282284 kb
Host	smart-fe569455-9e01-4bdf-a006-d8ee2b6856d4
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291383394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.4291383394
Directory	/workspace/3.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_mubi.563883697
Short name	T224
Test name
Test status
Simulation time	1071226898 ps
CPU time	11.68 seconds
Started	Aug 17 06:31:48 PM PDT 24
Finished	Aug 17 06:31:59 PM PDT 24
Peak memory	218924 kb
Host	smart-dd2ce3b9-4dbc-46f0-87c4-22b82e4d2e2f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563883697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.563883697
Directory	/workspace/3.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_digest.2045640843
Short name	T776
Test name
Test status
Simulation time	1015735035 ps
CPU time	8.15 seconds
Started	Aug 17 06:31:55 PM PDT 24
Finished	Aug 17 06:32:04 PM PDT 24
Peak memory	225872 kb
Host	smart-538d7d65-dab5-440a-acfb-4be18619d1d7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045640843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di gest.2045640843
Directory	/workspace/3.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/3.lc_ctrl_sec_token_mux.702657862
Short name	T381
Test name
Test status
Simulation time	1827243307 ps
CPU time	9.47 seconds
Started	Aug 17 06:31:51 PM PDT 24
Finished	Aug 17 06:32:00 PM PDT 24
Peak memory	218232 kb
Host	smart-2bbea69f-5d8b-4336-b243-f007a929b89b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702657862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.702657862
Directory	/workspace/3.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/3.lc_ctrl_security_escalation.1835093094
Short name	T623
Test name
Test status
Simulation time	624935041 ps
CPU time	12.25 seconds
Started	Aug 17 06:31:29 PM PDT 24
Finished	Aug 17 06:31:42 PM PDT 24
Peak memory	218288 kb
Host	smart-e4679309-d253-41b3-96b5-eb1a04180318
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835093094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.1835093094
Directory	/workspace/3.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/3.lc_ctrl_smoke.2203751112
Short name	T628
Test name
Test status
Simulation time	306308820 ps
CPU time	3.08 seconds
Started	Aug 17 06:31:30 PM PDT 24
Finished	Aug 17 06:31:38 PM PDT 24
Peak memory	217632 kb
Host	smart-ba3907cd-1841-41e8-a96e-d72419cd5eb6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2203751112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2203751112
Directory	/workspace/3.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_failure.730761467
Short name	T590
Test name
Test status
Simulation time	231113875 ps
CPU time	24.17 seconds
Started	Aug 17 06:31:59 PM PDT 24
Finished	Aug 17 06:32:23 PM PDT 24
Peak memory	246492 kb
Host	smart-cbfa3a38-19ff-4490-b05f-ef889e462422
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=730761467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.730761467
Directory	/workspace/3.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/3.lc_ctrl_state_post_trans.3036470782
Short name	T240
Test name
Test status
Simulation time	98847787 ps
CPU time	6.64 seconds
Started	Aug 17 06:32:08 PM PDT 24
Finished	Aug 17 06:32:15 PM PDT 24
Peak memory	244312 kb
Host	smart-76a5679c-e333-409b-8ed5-cdb1555665e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036470782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3036470782
Directory	/workspace/3.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/3.lc_ctrl_stress_all.3336230904
Short name	T543
Test name
Test status
Simulation time	9450956297 ps
CPU time	188.73 seconds
Started	Aug 17 06:31:55 PM PDT 24
Finished	Aug 17 06:35:04 PM PDT 24
Peak memory	250880 kb
Host	smart-d1109c7a-bd7a-4863-a527-9eabeeca04f3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336230904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all.3336230904
Directory	/workspace/3.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.140359272
Short name	T825
Test name
Test status
Simulation time	71624638 ps
CPU time	1.21 seconds
Started	Aug 17 06:31:51 PM PDT 24
Finished	Aug 17 06:31:53 PM PDT 24
Peak memory	212936 kb
Host	smart-47b794c6-7449-4cc4-a21d-da3819e10c54
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140359272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr l_volatile_unlock_smoke.140359272
Directory	/workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_alert_test.892680917
Short name	T515
Test name
Test status
Simulation time	50308428 ps
CPU time	0.88 seconds
Started	Aug 17 06:32:52 PM PDT 24
Finished	Aug 17 06:32:53 PM PDT 24
Peak memory	208664 kb
Host	smart-9d9a53d1-fa41-43c4-81a1-c2e0d3a9239a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892680917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.892680917
Directory	/workspace/30.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.lc_ctrl_errors.1238385910
Short name	T231
Test name
Test status
Simulation time	703066726 ps
CPU time	7.73 seconds
Started	Aug 17 06:32:47 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	218176 kb
Host	smart-813430b2-3095-42bc-a825-577017516dcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1238385910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1238385910
Directory	/workspace/30.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/30.lc_ctrl_jtag_access.1774708884
Short name	T376
Test name
Test status
Simulation time	2880783916 ps
CPU time	17.17 seconds
Started	Aug 17 06:32:46 PM PDT 24
Finished	Aug 17 06:33:03 PM PDT 24
Peak memory	217556 kb
Host	smart-f229f28f-ff2e-4475-87a7-eddbba8860c3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774708884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1774708884
Directory	/workspace/30.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/30.lc_ctrl_prog_failure.2228237430
Short name	T736
Test name
Test status
Simulation time	210905837 ps
CPU time	3.3 seconds
Started	Aug 17 06:32:50 PM PDT 24
Finished	Aug 17 06:32:54 PM PDT 24
Peak memory	218228 kb
Host	smart-426c0fd0-00ae-4141-aebb-e4ae9068530d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2228237430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2228237430
Directory	/workspace/30.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_mubi.3109144120
Short name	T62
Test name
Test status
Simulation time	2707542513 ps
CPU time	15.13 seconds
Started	Aug 17 06:32:46 PM PDT 24
Finished	Aug 17 06:33:02 PM PDT 24
Peak memory	218840 kb
Host	smart-efe8c88d-bdb1-4c78-9de9-944cb2a47384
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109144120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3109144120
Directory	/workspace/30.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_digest.3154484722
Short name	T803
Test name
Test status
Simulation time	1718560974 ps
CPU time	12.61 seconds
Started	Aug 17 06:33:04 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	226004 kb
Host	smart-a59b3bee-9f5a-438f-9d33-a57eb66485e3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154484722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d igest.3154484722
Directory	/workspace/30.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/30.lc_ctrl_sec_token_mux.1161512915
Short name	T838
Test name
Test status
Simulation time	1089597677 ps
CPU time	7.26 seconds
Started	Aug 17 06:32:54 PM PDT 24
Finished	Aug 17 06:33:01 PM PDT 24
Peak memory	225996 kb
Host	smart-52b45d0b-843f-4a71-8b02-a8631db98928
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161512915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux. 1161512915
Directory	/workspace/30.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/30.lc_ctrl_security_escalation.1171853102
Short name	T517
Test name
Test status
Simulation time	262362984 ps
CPU time	12.34 seconds
Started	Aug 17 06:32:45 PM PDT 24
Finished	Aug 17 06:32:57 PM PDT 24
Peak memory	218288 kb
Host	smart-f9767c90-ed4e-4dd7-9a04-80064fe5dc2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171853102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1171853102
Directory	/workspace/30.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/30.lc_ctrl_smoke.2551630175
Short name	T313
Test name
Test status
Simulation time	59072530 ps
CPU time	1.38 seconds
Started	Aug 17 06:32:51 PM PDT 24
Finished	Aug 17 06:32:53 PM PDT 24
Peak memory	213624 kb
Host	smart-c56918e2-0e14-428b-98f2-d76f8e794fc9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551630175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2551630175
Directory	/workspace/30.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_failure.1885167850
Short name	T31
Test name
Test status
Simulation time	968586446 ps
CPU time	33.84 seconds
Started	Aug 17 06:32:50 PM PDT 24
Finished	Aug 17 06:33:24 PM PDT 24
Peak memory	250860 kb
Host	smart-b104bd98-4c66-44da-a6f1-7a0355465333
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1885167850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.1885167850
Directory	/workspace/30.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/30.lc_ctrl_state_post_trans.2000389369
Short name	T726
Test name
Test status
Simulation time	72701505 ps
CPU time	8.45 seconds
Started	Aug 17 06:33:04 PM PDT 24
Finished	Aug 17 06:33:13 PM PDT 24
Peak memory	242684 kb
Host	smart-99ad112e-8548-40f0-8dc7-57a4004d1131
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000389369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2000389369
Directory	/workspace/30.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/30.lc_ctrl_stress_all.944493200
Short name	T239
Test name
Test status
Simulation time	6541300989 ps
CPU time	217.41 seconds
Started	Aug 17 06:32:52 PM PDT 24
Finished	Aug 17 06:36:30 PM PDT 24
Peak memory	283664 kb
Host	smart-aac94c99-ac58-4415-93b1-bae42d45a95c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944493200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all.944493200
Directory	/workspace/30.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3711555491
Short name	T609
Test name
Test status
Simulation time	14648747215 ps
CPU time	107.39 seconds
Started	Aug 17 06:32:50 PM PDT 24
Finished	Aug 17 06:34:38 PM PDT 24
Peak memory	275512 kb
Host	smart-9daf7535-17c2-41a0-8cb2-f4257a9b3d51
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3711555491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.3711555491
Directory	/workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1433326385
Short name	T211
Test name
Test status
Simulation time	14629584 ps
CPU time	1.1 seconds
Started	Aug 17 06:32:49 PM PDT 24
Finished	Aug 17 06:32:51 PM PDT 24
Peak memory	211836 kb
Host	smart-2de4daa1-6c98-4772-b8ba-3738a3c89eb3
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433326385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c trl_volatile_unlock_smoke.1433326385
Directory	/workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_alert_test.1213961965
Short name	T73
Test name
Test status
Simulation time	28188455 ps
CPU time	0.88 seconds
Started	Aug 17 06:32:53 PM PDT 24
Finished	Aug 17 06:32:54 PM PDT 24
Peak memory	208792 kb
Host	smart-30788d4e-b274-430a-9675-a176c42b0bb1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213961965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1213961965
Directory	/workspace/31.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.lc_ctrl_errors.2479585629
Short name	T393
Test name
Test status
Simulation time	581090705 ps
CPU time	12.59 seconds
Started	Aug 17 06:33:03 PM PDT 24
Finished	Aug 17 06:33:15 PM PDT 24
Peak memory	218216 kb
Host	smart-831e4f4a-2b42-42e5-8f01-093b758bb08b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479585629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2479585629
Directory	/workspace/31.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/31.lc_ctrl_jtag_access.292053859
Short name	T703
Test name
Test status
Simulation time	334936870 ps
CPU time	9.62 seconds
Started	Aug 17 06:32:41 PM PDT 24
Finished	Aug 17 06:32:51 PM PDT 24
Peak memory	217396 kb
Host	smart-f2027094-2614-46d3-b603-c4011b7f6344
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292053859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.292053859
Directory	/workspace/31.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/31.lc_ctrl_prog_failure.220285604
Short name	T594
Test name
Test status
Simulation time	1048213949 ps
CPU time	2.32 seconds
Started	Aug 17 06:32:44 PM PDT 24
Finished	Aug 17 06:32:46 PM PDT 24
Peak memory	222276 kb
Host	smart-596f65d6-83c5-405f-bf5e-1f5f7e6e7976
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=220285604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.220285604
Directory	/workspace/31.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_mubi.555988545
Short name	T705
Test name
Test status
Simulation time	4700589409 ps
CPU time	19.14 seconds
Started	Aug 17 06:32:53 PM PDT 24
Finished	Aug 17 06:33:12 PM PDT 24
Peak memory	226128 kb
Host	smart-70f59127-fcb5-447f-ba9b-f6df42e32236
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555988545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.555988545
Directory	/workspace/31.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_digest.3804486353
Short name	T358
Test name
Test status
Simulation time	947705935 ps
CPU time	10.08 seconds
Started	Aug 17 06:33:00 PM PDT 24
Finished	Aug 17 06:33:10 PM PDT 24
Peak memory	226000 kb
Host	smart-fc1d3745-715c-4785-90ef-7e14b2a0dcb5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804486353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d igest.3804486353
Directory	/workspace/31.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/31.lc_ctrl_sec_token_mux.1997787220
Short name	T560
Test name
Test status
Simulation time	1057805169 ps
CPU time	8.5 seconds
Started	Aug 17 06:32:44 PM PDT 24
Finished	Aug 17 06:32:53 PM PDT 24
Peak memory	218228 kb
Host	smart-ed617ba6-566e-4460-9e2e-bdb416ded8cd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997787220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux. 1997787220
Directory	/workspace/31.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/31.lc_ctrl_smoke.1856828005
Short name	T218
Test name
Test status
Simulation time	65141433 ps
CPU time	1.14 seconds
Started	Aug 17 06:32:51 PM PDT 24
Finished	Aug 17 06:32:53 PM PDT 24
Peak memory	217584 kb
Host	smart-378bcd5d-76d2-4ea6-981a-c32130a4eb4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856828005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1856828005
Directory	/workspace/31.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_failure.2267820298
Short name	T586
Test name
Test status
Simulation time	329313659 ps
CPU time	26.66 seconds
Started	Aug 17 06:32:47 PM PDT 24
Finished	Aug 17 06:33:13 PM PDT 24
Peak memory	250896 kb
Host	smart-b6f73829-74c6-4432-a75b-3ec8f0486fcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2267820298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2267820298
Directory	/workspace/31.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/31.lc_ctrl_state_post_trans.2673200120
Short name	T83
Test name
Test status
Simulation time	204890974 ps
CPU time	3.39 seconds
Started	Aug 17 06:32:53 PM PDT 24
Finished	Aug 17 06:32:57 PM PDT 24
Peak memory	218264 kb
Host	smart-8ac9b752-ff6f-4686-8c10-2f1634b1bf4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2673200120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2673200120
Directory	/workspace/31.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/31.lc_ctrl_stress_all.732031739
Short name	T74
Test name
Test status
Simulation time	12156436084 ps
CPU time	94.45 seconds
Started	Aug 17 06:32:53 PM PDT 24
Finished	Aug 17 06:34:27 PM PDT 24
Peak memory	250744 kb
Host	smart-b01dfe91-30b7-4716-b6d5-80e2a6ef21b9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732031739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all.732031739
Directory	/workspace/31.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2277965722
Short name	T772
Test name
Test status
Simulation time	54577610 ps
CPU time	0.96 seconds
Started	Aug 17 06:32:55 PM PDT 24
Finished	Aug 17 06:32:57 PM PDT 24
Peak memory	211880 kb
Host	smart-cc773b36-9c10-46a2-a4fc-ece6639556b8
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277965722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c trl_volatile_unlock_smoke.2277965722
Directory	/workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_alert_test.190039615
Short name	T596
Test name
Test status
Simulation time	76188143 ps
CPU time	0.92 seconds
Started	Aug 17 06:32:37 PM PDT 24
Finished	Aug 17 06:32:38 PM PDT 24
Peak memory	208924 kb
Host	smart-853bdd9e-6f49-4f1c-a541-636dfc49ee16
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190039615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.190039615
Directory	/workspace/32.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.lc_ctrl_errors.4129703006
Short name	T372
Test name
Test status
Simulation time	298178141 ps
CPU time	11.26 seconds
Started	Aug 17 06:33:09 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	218240 kb
Host	smart-f1f2037d-b89a-4e48-924a-5bcdb45649b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4129703006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.4129703006
Directory	/workspace/32.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/32.lc_ctrl_jtag_access.4133451947
Short name	T28
Test name
Test status
Simulation time	293404780 ps
CPU time	2.52 seconds
Started	Aug 17 06:33:00 PM PDT 24
Finished	Aug 17 06:33:02 PM PDT 24
Peak memory	216960 kb
Host	smart-dc165aba-97a9-4847-8077-4b6495ea34ae
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133451947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.4133451947
Directory	/workspace/32.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/32.lc_ctrl_prog_failure.2338937859
Short name	T332
Test name
Test status
Simulation time	87591077 ps
CPU time	1.93 seconds
Started	Aug 17 06:32:52 PM PDT 24
Finished	Aug 17 06:32:54 PM PDT 24
Peak memory	222108 kb
Host	smart-da336ab5-3e99-4428-adc7-08756e6c0232
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2338937859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2338937859
Directory	/workspace/32.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_mubi.3914126163
Short name	T852
Test name
Test status
Simulation time	350534343 ps
CPU time	10.55 seconds
Started	Aug 17 06:33:02 PM PDT 24
Finished	Aug 17 06:33:13 PM PDT 24
Peak memory	226036 kb
Host	smart-dcf025e5-7d1a-4fed-9478-2ca4a5132d02
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914126163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3914126163
Directory	/workspace/32.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_digest.3161282578
Short name	T245
Test name
Test status
Simulation time	481369092 ps
CPU time	12.68 seconds
Started	Aug 17 06:32:49 PM PDT 24
Finished	Aug 17 06:33:02 PM PDT 24
Peak memory	225988 kb
Host	smart-46642f37-4d12-4d9d-b135-66e24853b63f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161282578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d igest.3161282578
Directory	/workspace/32.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/32.lc_ctrl_sec_token_mux.2582166269
Short name	T257
Test name
Test status
Simulation time	1515989611 ps
CPU time	7.53 seconds
Started	Aug 17 06:32:47 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	226092 kb
Host	smart-3547c5eb-97f9-4560-8745-7fe46049227f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582166269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux. 2582166269
Directory	/workspace/32.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/32.lc_ctrl_security_escalation.3196543931
Short name	T352
Test name
Test status
Simulation time	252596985 ps
CPU time	9.71 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:20 PM PDT 24
Peak memory	218388 kb
Host	smart-c3453506-5220-4a72-82b1-54723cf35cb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196543931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3196543931
Directory	/workspace/32.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/32.lc_ctrl_smoke.3809526802
Short name	T578
Test name
Test status
Simulation time	207632124 ps
CPU time	3.24 seconds
Started	Aug 17 06:32:53 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	217612 kb
Host	smart-8d296983-0d1d-453a-98b3-c2b4594e0aa4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3809526802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3809526802
Directory	/workspace/32.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_failure.4137111284
Short name	T702
Test name
Test status
Simulation time	2285053000 ps
CPU time	22.95 seconds
Started	Aug 17 06:33:01 PM PDT 24
Finished	Aug 17 06:33:24 PM PDT 24
Peak memory	251028 kb
Host	smart-813ff427-f235-4575-adc8-14e982b48dba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4137111284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.4137111284
Directory	/workspace/32.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/32.lc_ctrl_state_post_trans.2785202491
Short name	T198
Test name
Test status
Simulation time	49718519 ps
CPU time	3.16 seconds
Started	Aug 17 06:32:58 PM PDT 24
Finished	Aug 17 06:33:01 PM PDT 24
Peak memory	218236 kb
Host	smart-4710ccb8-db85-441c-b5da-16ad3486050d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785202491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2785202491
Directory	/workspace/32.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/32.lc_ctrl_stress_all.567122895
Short name	T617
Test name
Test status
Simulation time	48900896959 ps
CPU time	319.9 seconds
Started	Aug 17 06:32:52 PM PDT 24
Finished	Aug 17 06:38:12 PM PDT 24
Peak memory	258880 kb
Host	smart-159adca6-59bb-4ef0-bf9e-eae5a1ceb342
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567122895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all.567122895
Directory	/workspace/32.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3394005268
Short name	T558
Test name
Test status
Simulation time	12370193 ps
CPU time	0.82 seconds
Started	Aug 17 06:32:56 PM PDT 24
Finished	Aug 17 06:32:57 PM PDT 24
Peak memory	211876 kb
Host	smart-dac70d9a-e655-4fad-a39f-6d360515dfbf
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394005268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c trl_volatile_unlock_smoke.3394005268
Directory	/workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_alert_test.521890301
Short name	T556
Test name
Test status
Simulation time	35467822 ps
CPU time	0.9 seconds
Started	Aug 17 06:33:04 PM PDT 24
Finished	Aug 17 06:33:05 PM PDT 24
Peak memory	208852 kb
Host	smart-7a9768ca-c638-448b-9087-0d6a34909243
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521890301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.521890301
Directory	/workspace/33.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.lc_ctrl_errors.1216761106
Short name	T222
Test name
Test status
Simulation time	465711665 ps
CPU time	19.7 seconds
Started	Aug 17 06:33:05 PM PDT 24
Finished	Aug 17 06:33:25 PM PDT 24
Peak memory	218248 kb
Host	smart-dfaa11db-ab38-4d5d-b2a1-1b0e6a943e3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1216761106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1216761106
Directory	/workspace/33.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/33.lc_ctrl_jtag_access.2661320313
Short name	T708
Test name
Test status
Simulation time	44412604 ps
CPU time	1.34 seconds
Started	Aug 17 06:32:55 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	217164 kb
Host	smart-946bf106-a203-4a65-ade9-40e4621f0c0e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661320313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2661320313
Directory	/workspace/33.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/33.lc_ctrl_prog_failure.455676665
Short name	T529
Test name
Test status
Simulation time	62486664 ps
CPU time	2.78 seconds
Started	Aug 17 06:33:09 PM PDT 24
Finished	Aug 17 06:33:12 PM PDT 24
Peak memory	218252 kb
Host	smart-c960564a-084e-48c3-ada0-6681aaa26a2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455676665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.455676665
Directory	/workspace/33.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_mubi.4058080434
Short name	T822
Test name
Test status
Simulation time	207948753 ps
CPU time	11.3 seconds
Started	Aug 17 06:33:06 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	218288 kb
Host	smart-52732af2-62c0-43e8-90f2-4db7c6b4ebff
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058080434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.4058080434
Directory	/workspace/33.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_digest.1550206435
Short name	T786
Test name
Test status
Simulation time	709447222 ps
CPU time	11.33 seconds
Started	Aug 17 06:32:53 PM PDT 24
Finished	Aug 17 06:33:05 PM PDT 24
Peak memory	226008 kb
Host	smart-d52f9ddf-9eb0-4235-b688-1d15c50b1d06
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550206435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d igest.1550206435
Directory	/workspace/33.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/33.lc_ctrl_sec_token_mux.991833503
Short name	T392
Test name
Test status
Simulation time	307155943 ps
CPU time	11.12 seconds
Started	Aug 17 06:33:04 PM PDT 24
Finished	Aug 17 06:33:15 PM PDT 24
Peak memory	225972 kb
Host	smart-70b20b53-e69e-402a-a627-b7bdc142a148
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991833503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.991833503
Directory	/workspace/33.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/33.lc_ctrl_security_escalation.157433756
Short name	T528
Test name
Test status
Simulation time	873815735 ps
CPU time	9.86 seconds
Started	Aug 17 06:33:03 PM PDT 24
Finished	Aug 17 06:33:13 PM PDT 24
Peak memory	218516 kb
Host	smart-bf955d69-5fab-4d2d-8349-728d2e868186
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157433756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.157433756
Directory	/workspace/33.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/33.lc_ctrl_smoke.3254744143
Short name	T351
Test name
Test status
Simulation time	39119062 ps
CPU time	1.65 seconds
Started	Aug 17 06:32:46 PM PDT 24
Finished	Aug 17 06:32:48 PM PDT 24
Peak memory	213864 kb
Host	smart-aa54dfe8-db7b-4883-a61a-4423dab758ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3254744143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3254744143
Directory	/workspace/33.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_failure.561278915
Short name	T283
Test name
Test status
Simulation time	380540717 ps
CPU time	21.85 seconds
Started	Aug 17 06:33:03 PM PDT 24
Finished	Aug 17 06:33:25 PM PDT 24
Peak memory	250928 kb
Host	smart-96f80449-82a0-4213-b043-e4c457f737ef
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561278915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.561278915
Directory	/workspace/33.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/33.lc_ctrl_state_post_trans.4118716658
Short name	T681
Test name
Test status
Simulation time	196224125 ps
CPU time	11.08 seconds
Started	Aug 17 06:32:47 PM PDT 24
Finished	Aug 17 06:32:58 PM PDT 24
Peak memory	250912 kb
Host	smart-876c2c1e-81b0-4b9d-9423-6515165fa1a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4118716658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.4118716658
Directory	/workspace/33.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/33.lc_ctrl_stress_all.2884250509
Short name	T236
Test name
Test status
Simulation time	4433307813 ps
CPU time	43.43 seconds
Started	Aug 17 06:33:07 PM PDT 24
Finished	Aug 17 06:33:50 PM PDT 24
Peak memory	226060 kb
Host	smart-4c3dd2bb-86ca-444b-8a3c-3d3a4454a885
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884250509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all.2884250509
Directory	/workspace/33.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.3274874039
Short name	T535
Test name
Test status
Simulation time	7373713561 ps
CPU time	29.87 seconds
Started	Aug 17 06:32:55 PM PDT 24
Finished	Aug 17 06:33:25 PM PDT 24
Peak memory	248748 kb
Host	smart-45ddb1ba-912a-499e-84ec-077a7bdb9bdf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3274874039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.3274874039
Directory	/workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1708059670
Short name	T281
Test name
Test status
Simulation time	34665381 ps
CPU time	0.84 seconds
Started	Aug 17 06:33:01 PM PDT 24
Finished	Aug 17 06:33:02 PM PDT 24
Peak memory	211904 kb
Host	smart-a59e0ef0-27ce-41e0-92bc-6dcfbbf60d93
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708059670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c trl_volatile_unlock_smoke.1708059670
Directory	/workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_alert_test.540023118
Short name	T216
Test name
Test status
Simulation time	22012213 ps
CPU time	0.95 seconds
Started	Aug 17 06:33:06 PM PDT 24
Finished	Aug 17 06:33:07 PM PDT 24
Peak memory	208804 kb
Host	smart-186c3367-53ed-494f-ad05-8fd4a8abea06
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540023118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.540023118
Directory	/workspace/34.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.lc_ctrl_errors.3852747568
Short name	T644
Test name
Test status
Simulation time	1357453892 ps
CPU time	12.25 seconds
Started	Aug 17 06:33:03 PM PDT 24
Finished	Aug 17 06:33:15 PM PDT 24
Peak memory	218264 kb
Host	smart-bd02feba-9e9e-4530-843f-89a87c91cd42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3852747568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3852747568
Directory	/workspace/34.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/34.lc_ctrl_jtag_access.933030048
Short name	T409
Test name
Test status
Simulation time	645147250 ps
CPU time	3.92 seconds
Started	Aug 17 06:32:53 PM PDT 24
Finished	Aug 17 06:32:57 PM PDT 24
Peak memory	217632 kb
Host	smart-de85b899-3bbe-4276-9982-97b2b8206dc5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933030048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.933030048
Directory	/workspace/34.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/34.lc_ctrl_prog_failure.3209579232
Short name	T818
Test name
Test status
Simulation time	172382478 ps
CPU time	2.27 seconds
Started	Aug 17 06:33:04 PM PDT 24
Finished	Aug 17 06:33:07 PM PDT 24
Peak memory	218248 kb
Host	smart-f190f5d4-f3de-4501-9fce-42a5ff1e9367
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3209579232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3209579232
Directory	/workspace/34.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_mubi.2083044193
Short name	T160
Test name
Test status
Simulation time	596305374 ps
CPU time	16.8 seconds
Started	Aug 17 06:33:07 PM PDT 24
Finished	Aug 17 06:33:24 PM PDT 24
Peak memory	218336 kb
Host	smart-1d88c117-8c36-425d-91b5-322310d9d8d8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083044193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2083044193
Directory	/workspace/34.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_digest.2773811875
Short name	T668
Test name
Test status
Simulation time	449545387 ps
CPU time	16.53 seconds
Started	Aug 17 06:32:55 PM PDT 24
Finished	Aug 17 06:33:12 PM PDT 24
Peak memory	226020 kb
Host	smart-02801b8b-ff33-4da5-ab24-9e686dd5a98d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773811875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d igest.2773811875
Directory	/workspace/34.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/34.lc_ctrl_sec_token_mux.425675775
Short name	T540
Test name
Test status
Simulation time	2291910177 ps
CPU time	12.92 seconds
Started	Aug 17 06:33:06 PM PDT 24
Finished	Aug 17 06:33:18 PM PDT 24
Peak memory	218260 kb
Host	smart-88dc4d7a-d8ff-4e95-a66b-f943ff3bb015
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425675775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.425675775
Directory	/workspace/34.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/34.lc_ctrl_security_escalation.3148922396
Short name	T304
Test name
Test status
Simulation time	321835450 ps
CPU time	9.06 seconds
Started	Aug 17 06:33:17 PM PDT 24
Finished	Aug 17 06:33:26 PM PDT 24
Peak memory	218308 kb
Host	smart-5461021b-4f35-4759-a990-1894720bc06f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3148922396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3148922396
Directory	/workspace/34.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/34.lc_ctrl_smoke.4286579229
Short name	T329
Test name
Test status
Simulation time	52659620 ps
CPU time	2.69 seconds
Started	Aug 17 06:32:55 PM PDT 24
Finished	Aug 17 06:32:57 PM PDT 24
Peak memory	222720 kb
Host	smart-a8332e32-1ef5-45cc-bd84-e8cc44b35bad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286579229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4286579229
Directory	/workspace/34.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_failure.3452782
Short name	T706
Test name
Test status
Simulation time	1132381944 ps
CPU time	31.9 seconds
Started	Aug 17 06:33:03 PM PDT 24
Finished	Aug 17 06:33:35 PM PDT 24
Peak memory	251036 kb
Host	smart-4fb1d652-80a0-4ad8-a6f6-bf454d32ae84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3452782
Directory	/workspace/34.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/34.lc_ctrl_state_post_trans.1476725896
Short name	T3
Test name
Test status
Simulation time	323795623 ps
CPU time	6.47 seconds
Started	Aug 17 06:32:59 PM PDT 24
Finished	Aug 17 06:33:05 PM PDT 24
Peak memory	248388 kb
Host	smart-6f064da3-5047-43ec-a735-7c5409425633
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1476725896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1476725896
Directory	/workspace/34.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/34.lc_ctrl_stress_all.3197700756
Short name	T762
Test name
Test status
Simulation time	14024842769 ps
CPU time	554.96 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:42:25 PM PDT 24
Peak memory	251968 kb
Host	smart-0ee9adb0-60a0-4e65-8021-d3389c081788
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197700756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all.3197700756
Directory	/workspace/34.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1869747128
Short name	T136
Test name
Test status
Simulation time	21874168 ps
CPU time	0.92 seconds
Started	Aug 17 06:32:58 PM PDT 24
Finished	Aug 17 06:32:59 PM PDT 24
Peak memory	211876 kb
Host	smart-d978ebb4-0dcd-49fe-aafb-6be592dba75e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869747128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c trl_volatile_unlock_smoke.1869747128
Directory	/workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_alert_test.3015460855
Short name	T360
Test name
Test status
Simulation time	27174416 ps
CPU time	0.89 seconds
Started	Aug 17 06:33:03 PM PDT 24
Finished	Aug 17 06:33:04 PM PDT 24
Peak memory	208692 kb
Host	smart-c38e2470-7f4a-4542-a2f7-c79259cde394
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015460855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3015460855
Directory	/workspace/35.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.lc_ctrl_errors.1430041661
Short name	T288
Test name
Test status
Simulation time	244415790 ps
CPU time	10.16 seconds
Started	Aug 17 06:33:03 PM PDT 24
Finished	Aug 17 06:33:14 PM PDT 24
Peak memory	218252 kb
Host	smart-3d0f9e80-7ca9-45d0-9f18-6a9c4419597a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1430041661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1430041661
Directory	/workspace/35.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/35.lc_ctrl_jtag_access.2413506436
Short name	T597
Test name
Test status
Simulation time	1552567147 ps
CPU time	3.83 seconds
Started	Aug 17 06:33:06 PM PDT 24
Finished	Aug 17 06:33:10 PM PDT 24
Peak memory	216960 kb
Host	smart-002c1641-928e-48af-9d3d-41a9971ee61e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413506436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2413506436
Directory	/workspace/35.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/35.lc_ctrl_prog_failure.3526272150
Short name	T588
Test name
Test status
Simulation time	359202169 ps
CPU time	3.07 seconds
Started	Aug 17 06:33:14 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	218252 kb
Host	smart-7f651874-6614-4f96-8c5d-4cef27b28dad
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3526272150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3526272150
Directory	/workspace/35.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_mubi.1908841751
Short name	T500
Test name
Test status
Simulation time	1957661326 ps
CPU time	14.45 seconds
Started	Aug 17 06:33:01 PM PDT 24
Finished	Aug 17 06:33:16 PM PDT 24
Peak memory	226080 kb
Host	smart-6e66cf7b-603d-4301-adaa-fd7359f66af6
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908841751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1908841751
Directory	/workspace/35.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_digest.164417544
Short name	T552
Test name
Test status
Simulation time	1308338078 ps
CPU time	13.54 seconds
Started	Aug 17 06:32:52 PM PDT 24
Finished	Aug 17 06:33:06 PM PDT 24
Peak memory	226004 kb
Host	smart-2099374e-950c-4977-9649-f543ff9c5e75
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164417544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di gest.164417544
Directory	/workspace/35.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/35.lc_ctrl_sec_token_mux.4248600821
Short name	T338
Test name
Test status
Simulation time	1145174175 ps
CPU time	8.05 seconds
Started	Aug 17 06:33:00 PM PDT 24
Finished	Aug 17 06:33:08 PM PDT 24
Peak memory	218136 kb
Host	smart-a46724ea-647c-40a7-8e8a-71ccbbd2047d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248600821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux. 4248600821
Directory	/workspace/35.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/35.lc_ctrl_security_escalation.4251384129
Short name	T504
Test name
Test status
Simulation time	1808819361 ps
CPU time	8.89 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:19 PM PDT 24
Peak memory	218332 kb
Host	smart-ebf17f4a-4beb-488f-8cb2-0a2c3e171889
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4251384129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.4251384129
Directory	/workspace/35.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/35.lc_ctrl_smoke.1889097774
Short name	T615
Test name
Test status
Simulation time	81483702 ps
CPU time	2.55 seconds
Started	Aug 17 06:32:58 PM PDT 24
Finished	Aug 17 06:33:00 PM PDT 24
Peak memory	214352 kb
Host	smart-a163b255-5842-457a-885b-2606d28a06e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889097774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.1889097774
Directory	/workspace/35.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_failure.3240287543
Short name	T747
Test name
Test status
Simulation time	774871588 ps
CPU time	19.55 seconds
Started	Aug 17 06:33:06 PM PDT 24
Finished	Aug 17 06:33:26 PM PDT 24
Peak memory	250752 kb
Host	smart-fe6c02d8-b106-4b29-84c0-30acf4b6176b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3240287543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3240287543
Directory	/workspace/35.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/35.lc_ctrl_state_post_trans.689054457
Short name	T155
Test name
Test status
Simulation time	60829372 ps
CPU time	6.53 seconds
Started	Aug 17 06:33:06 PM PDT 24
Finished	Aug 17 06:33:13 PM PDT 24
Peak memory	247108 kb
Host	smart-1a2ec6b0-23d4-41e4-88c7-0260a413f305
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689054457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.689054457
Directory	/workspace/35.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/35.lc_ctrl_stress_all.3491425860
Short name	T720
Test name
Test status
Simulation time	49866045184 ps
CPU time	284.83 seconds
Started	Aug 17 06:33:17 PM PDT 24
Finished	Aug 17 06:38:02 PM PDT 24
Peak memory	278352 kb
Host	smart-3bfc63d7-54fa-4fea-b2c1-daa4b8dd9b64
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491425860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all.3491425860
Directory	/workspace/35.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.2938019757
Short name	T86
Test name
Test status
Simulation time	1881831980 ps
CPU time	45.5 seconds
Started	Aug 17 06:32:55 PM PDT 24
Finished	Aug 17 06:33:41 PM PDT 24
Peak memory	276408 kb
Host	smart-78778b2c-05df-4b70-9452-ede09107a0cb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2938019757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.2938019757
Directory	/workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.723844841
Short name	T624
Test name
Test status
Simulation time	63212766 ps
CPU time	1.01 seconds
Started	Aug 17 06:33:01 PM PDT 24
Finished	Aug 17 06:33:02 PM PDT 24
Peak memory	212868 kb
Host	smart-be23fc5b-6fba-428d-b2ad-ce0e7deb0b67
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723844841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct rl_volatile_unlock_smoke.723844841
Directory	/workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_alert_test.934752121
Short name	T555
Test name
Test status
Simulation time	22503737 ps
CPU time	0.93 seconds
Started	Aug 17 06:33:06 PM PDT 24
Finished	Aug 17 06:33:07 PM PDT 24
Peak memory	208840 kb
Host	smart-5b6f7858-939c-4218-bc01-c136bdaec280
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934752121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.934752121
Directory	/workspace/36.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.lc_ctrl_errors.2944303834
Short name	T203
Test name
Test status
Simulation time	2174907941 ps
CPU time	14.47 seconds
Started	Aug 17 06:33:11 PM PDT 24
Finished	Aug 17 06:33:25 PM PDT 24
Peak memory	226084 kb
Host	smart-007d37d2-3cd6-4913-94cb-8b0fe12e5d75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2944303834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2944303834
Directory	/workspace/36.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/36.lc_ctrl_jtag_access.3069191005
Short name	T468
Test name
Test status
Simulation time	405181498 ps
CPU time	5.97 seconds
Started	Aug 17 06:33:08 PM PDT 24
Finished	Aug 17 06:33:14 PM PDT 24
Peak memory	217308 kb
Host	smart-a0072446-42a7-4fa8-b832-855bd515507c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069191005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3069191005
Directory	/workspace/36.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/36.lc_ctrl_prog_failure.3662657154
Short name	T282
Test name
Test status
Simulation time	72297898 ps
CPU time	3.8 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:18 PM PDT 24
Peak memory	218292 kb
Host	smart-d700223a-5503-444e-be28-d9564854f63c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3662657154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3662657154
Directory	/workspace/36.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_mubi.208801854
Short name	T769
Test name
Test status
Simulation time	360974634 ps
CPU time	16.02 seconds
Started	Aug 17 06:33:07 PM PDT 24
Finished	Aug 17 06:33:24 PM PDT 24
Peak memory	218940 kb
Host	smart-ad215c80-1753-4684-9ef3-3181515ccc1e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208801854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.208801854
Directory	/workspace/36.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_digest.911157036
Short name	T583
Test name
Test status
Simulation time	352373415 ps
CPU time	13.79 seconds
Started	Aug 17 06:33:07 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	226028 kb
Host	smart-6c9bb9e0-e718-47d5-8929-c652cfac3cdc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911157036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di gest.911157036
Directory	/workspace/36.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/36.lc_ctrl_sec_token_mux.947968261
Short name	T856
Test name
Test status
Simulation time	196429943 ps
CPU time	8.25 seconds
Started	Aug 17 06:33:06 PM PDT 24
Finished	Aug 17 06:33:15 PM PDT 24
Peak memory	218216 kb
Host	smart-f37f3351-beb8-40c7-94e3-a9c201a0cabd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947968261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.947968261
Directory	/workspace/36.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/36.lc_ctrl_security_escalation.2427683553
Short name	T490
Test name
Test status
Simulation time	1141668443 ps
CPU time	13.59 seconds
Started	Aug 17 06:33:09 PM PDT 24
Finished	Aug 17 06:33:23 PM PDT 24
Peak memory	226096 kb
Host	smart-9d0d056a-9ce4-4a74-b1e5-c30bbb2c92fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2427683553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2427683553
Directory	/workspace/36.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/36.lc_ctrl_smoke.3025414881
Short name	T551
Test name
Test status
Simulation time	460838136 ps
CPU time	3.66 seconds
Started	Aug 17 06:33:07 PM PDT 24
Finished	Aug 17 06:33:11 PM PDT 24
Peak memory	217620 kb
Host	smart-4072e73a-6576-41d5-a166-a85411723635
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025414881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3025414881
Directory	/workspace/36.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_failure.1883767434
Short name	T348
Test name
Test status
Simulation time	762410782 ps
CPU time	23.46 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:39 PM PDT 24
Peak memory	250900 kb
Host	smart-a732f329-be2e-4adb-a58a-5b9dda5d19a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1883767434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1883767434
Directory	/workspace/36.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/36.lc_ctrl_state_post_trans.3387723733
Short name	T324
Test name
Test status
Simulation time	65020976 ps
CPU time	3.66 seconds
Started	Aug 17 06:33:11 PM PDT 24
Finished	Aug 17 06:33:15 PM PDT 24
Peak memory	226316 kb
Host	smart-1c6bdc50-d9e9-422c-b598-0b55451c9503
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3387723733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3387723733
Directory	/workspace/36.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/36.lc_ctrl_stress_all.1736256156
Short name	T493
Test name
Test status
Simulation time	5681357979 ps
CPU time	158.19 seconds
Started	Aug 17 06:32:56 PM PDT 24
Finished	Aug 17 06:35:34 PM PDT 24
Peak memory	332828 kb
Host	smart-6fb46ce6-121e-4ad9-9919-39a8db776fa3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736256156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all.1736256156
Directory	/workspace/36.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3048924474
Short name	T135
Test name
Test status
Simulation time	6674599435 ps
CPU time	66.58 seconds
Started	Aug 17 06:33:03 PM PDT 24
Finished	Aug 17 06:34:09 PM PDT 24
Peak memory	274204 kb
Host	smart-359df121-788b-4a28-98e9-494812fabd3d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3048924474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.3048924474
Directory	/workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2419750401
Short name	T422
Test name
Test status
Simulation time	12356204 ps
CPU time	1.08 seconds
Started	Aug 17 06:33:01 PM PDT 24
Finished	Aug 17 06:33:02 PM PDT 24
Peak memory	213052 kb
Host	smart-93a06888-efc2-4299-a189-c6e1ed86cff4
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419750401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c trl_volatile_unlock_smoke.2419750401
Directory	/workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_alert_test.2964010100
Short name	T70
Test name
Test status
Simulation time	17142716 ps
CPU time	0.95 seconds
Started	Aug 17 06:32:54 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	208832 kb
Host	smart-54c3b984-7d26-47df-a85a-f3f29ac8e8a9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964010100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2964010100
Directory	/workspace/37.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.lc_ctrl_errors.1163546190
Short name	T217
Test name
Test status
Simulation time	771563588 ps
CPU time	15.74 seconds
Started	Aug 17 06:32:58 PM PDT 24
Finished	Aug 17 06:33:14 PM PDT 24
Peak memory	218276 kb
Host	smart-79d78fe7-3e2d-4351-a066-128a726d029f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163546190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1163546190
Directory	/workspace/37.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/37.lc_ctrl_jtag_access.3807143181
Short name	T605
Test name
Test status
Simulation time	486570155 ps
CPU time	12.2 seconds
Started	Aug 17 06:33:04 PM PDT 24
Finished	Aug 17 06:33:16 PM PDT 24
Peak memory	217192 kb
Host	smart-2e06923c-5e94-43fa-92d5-4cccb78fac6e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807143181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3807143181
Directory	/workspace/37.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/37.lc_ctrl_prog_failure.466241175
Short name	T796
Test name
Test status
Simulation time	252781238 ps
CPU time	3.15 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:13 PM PDT 24
Peak memory	218260 kb
Host	smart-cb54cd87-3112-4e87-bb89-458e2ffb27f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=466241175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.466241175
Directory	/workspace/37.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_mubi.1850172721
Short name	T303
Test name
Test status
Simulation time	787276679 ps
CPU time	9.85 seconds
Started	Aug 17 06:33:17 PM PDT 24
Finished	Aug 17 06:33:27 PM PDT 24
Peak memory	219264 kb
Host	smart-58d49bda-f86a-42c6-a1bf-263e89059d8d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850172721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1850172721
Directory	/workspace/37.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_digest.3549531632
Short name	T682
Test name
Test status
Simulation time	284779687 ps
CPU time	8.74 seconds
Started	Aug 17 06:33:06 PM PDT 24
Finished	Aug 17 06:33:15 PM PDT 24
Peak memory	226004 kb
Host	smart-0a16c1e9-e3c0-43bb-9a2a-0281192b7c72
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549531632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d igest.3549531632
Directory	/workspace/37.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/37.lc_ctrl_sec_token_mux.909060205
Short name	T518
Test name
Test status
Simulation time	2527453429 ps
CPU time	6.28 seconds
Started	Aug 17 06:33:03 PM PDT 24
Finished	Aug 17 06:33:09 PM PDT 24
Peak memory	225292 kb
Host	smart-68f490d6-36c3-4fba-b7a5-5767f72333d1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909060205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.909060205
Directory	/workspace/37.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/37.lc_ctrl_security_escalation.1983540941
Short name	T844
Test name
Test status
Simulation time	170426732 ps
CPU time	8.05 seconds
Started	Aug 17 06:33:09 PM PDT 24
Finished	Aug 17 06:33:18 PM PDT 24
Peak memory	218340 kb
Host	smart-d4c394dd-4556-44e6-9938-7591929e89c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1983540941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1983540941
Directory	/workspace/37.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/37.lc_ctrl_smoke.1812924137
Short name	T598
Test name
Test status
Simulation time	32390200 ps
CPU time	2.67 seconds
Started	Aug 17 06:33:01 PM PDT 24
Finished	Aug 17 06:33:04 PM PDT 24
Peak memory	214308 kb
Host	smart-8eee04f0-7ff2-47e8-a41d-3bb04bd703e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1812924137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1812924137
Directory	/workspace/37.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_failure.1008159437
Short name	T498
Test name
Test status
Simulation time	170806114 ps
CPU time	17.66 seconds
Started	Aug 17 06:33:07 PM PDT 24
Finished	Aug 17 06:33:25 PM PDT 24
Peak memory	250892 kb
Host	smart-0cd177cf-1212-4ec3-975d-227cdff325d4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008159437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1008159437
Directory	/workspace/37.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/37.lc_ctrl_state_post_trans.3618760470
Short name	T297
Test name
Test status
Simulation time	67866802 ps
CPU time	3.08 seconds
Started	Aug 17 06:33:09 PM PDT 24
Finished	Aug 17 06:33:12 PM PDT 24
Peak memory	226308 kb
Host	smart-3a6cfa62-735d-4afa-ae17-e64a939f8b7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618760470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3618760470
Directory	/workspace/37.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/37.lc_ctrl_stress_all.4277711591
Short name	T48
Test name
Test status
Simulation time	5078918102 ps
CPU time	42.16 seconds
Started	Aug 17 06:33:01 PM PDT 24
Finished	Aug 17 06:33:43 PM PDT 24
Peak memory	250884 kb
Host	smart-e056f69a-4a71-403c-abe3-85e8511a8793
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277711591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all.4277711591
Directory	/workspace/37.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1574027678
Short name	T247
Test name
Test status
Simulation time	21522476 ps
CPU time	0.72 seconds
Started	Aug 17 06:33:17 PM PDT 24
Finished	Aug 17 06:33:18 PM PDT 24
Peak memory	208060 kb
Host	smart-4d3d10ea-0ebb-4d36-8960-de0a4bec2cf1
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574027678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c trl_volatile_unlock_smoke.1574027678
Directory	/workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_alert_test.484126606
Short name	T427
Test name
Test status
Simulation time	37985516 ps
CPU time	1.15 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:11 PM PDT 24
Peak memory	209008 kb
Host	smart-87a43da4-11c0-431d-a8fd-bcf5e4b2b013
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484126606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.484126606
Directory	/workspace/38.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.lc_ctrl_errors.88574328
Short name	T809
Test name
Test status
Simulation time	583771227 ps
CPU time	12.51 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:23 PM PDT 24
Peak memory	218220 kb
Host	smart-4432d06d-ae0f-4d0e-84e3-b2dd192feac8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=88574328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.88574328
Directory	/workspace/38.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/38.lc_ctrl_jtag_access.1891887067
Short name	T642
Test name
Test status
Simulation time	1546194543 ps
CPU time	10.65 seconds
Started	Aug 17 06:32:56 PM PDT 24
Finished	Aug 17 06:33:07 PM PDT 24
Peak memory	217320 kb
Host	smart-6b4fd6b1-bb7c-4740-b283-a38a37bfed42
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891887067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1891887067
Directory	/workspace/38.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/38.lc_ctrl_prog_failure.4089132119
Short name	T229
Test name
Test status
Simulation time	250008780 ps
CPU time	3.27 seconds
Started	Aug 17 06:33:05 PM PDT 24
Finished	Aug 17 06:33:08 PM PDT 24
Peak memory	218188 kb
Host	smart-2ae98c48-9613-4dba-891e-4722877ffa69
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4089132119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.4089132119
Directory	/workspace/38.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_digest.1150857242
Short name	T538
Test name
Test status
Simulation time	349025669 ps
CPU time	10.52 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	225996 kb
Host	smart-b66a2910-eed0-42c9-be15-bbfb5602e343
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150857242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d igest.1150857242
Directory	/workspace/38.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/38.lc_ctrl_sec_token_mux.1597841544
Short name	T666
Test name
Test status
Simulation time	1170466678 ps
CPU time	11.38 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:22 PM PDT 24
Peak memory	226036 kb
Host	smart-1a3c9b2a-f2c4-4c8a-89a9-5652b065e1d3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597841544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux. 1597841544
Directory	/workspace/38.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/38.lc_ctrl_security_escalation.2751246950
Short name	T572
Test name
Test status
Simulation time	349282609 ps
CPU time	7.85 seconds
Started	Aug 17 06:32:59 PM PDT 24
Finished	Aug 17 06:33:07 PM PDT 24
Peak memory	224972 kb
Host	smart-86286927-b4e5-4e14-992a-3083913513c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2751246950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2751246950
Directory	/workspace/38.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/38.lc_ctrl_smoke.3947958763
Short name	T801
Test name
Test status
Simulation time	166642726 ps
CPU time	4.81 seconds
Started	Aug 17 06:33:06 PM PDT 24
Finished	Aug 17 06:33:11 PM PDT 24
Peak memory	217700 kb
Host	smart-9993db5c-11c5-45ea-8e4d-db7975d19066
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3947958763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3947958763
Directory	/workspace/38.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_failure.3994656040
Short name	T215
Test name
Test status
Simulation time	553010800 ps
CPU time	24.8 seconds
Started	Aug 17 06:32:59 PM PDT 24
Finished	Aug 17 06:33:24 PM PDT 24
Peak memory	250792 kb
Host	smart-db936f6e-2fbd-4c7f-91ba-6419fcd84dcf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994656040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3994656040
Directory	/workspace/38.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/38.lc_ctrl_state_post_trans.3980855242
Short name	T645
Test name
Test status
Simulation time	512261800 ps
CPU time	8.5 seconds
Started	Aug 17 06:32:52 PM PDT 24
Finished	Aug 17 06:33:01 PM PDT 24
Peak memory	250824 kb
Host	smart-0dc08e75-f700-49e7-a475-9b87dc1476f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980855242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3980855242
Directory	/workspace/38.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.55780685
Short name	T501
Test name
Test status
Simulation time	22572146 ps
CPU time	0.89 seconds
Started	Aug 17 06:32:56 PM PDT 24
Finished	Aug 17 06:32:57 PM PDT 24
Peak memory	211864 kb
Host	smart-e22e6e49-3234-4ca3-b99a-ad77c9208651
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55780685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctr l_volatile_unlock_smoke.55780685
Directory	/workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_alert_test.2450306759
Short name	T550
Test name
Test status
Simulation time	32172642 ps
CPU time	0.93 seconds
Started	Aug 17 06:33:11 PM PDT 24
Finished	Aug 17 06:33:12 PM PDT 24
Peak memory	208808 kb
Host	smart-47b7c688-9acb-4ea1-8c6c-7622566b2bdb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450306759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2450306759
Directory	/workspace/39.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.lc_ctrl_errors.377416465
Short name	T601
Test name
Test status
Simulation time	2810491016 ps
CPU time	14.09 seconds
Started	Aug 17 06:33:14 PM PDT 24
Finished	Aug 17 06:33:28 PM PDT 24
Peak memory	218352 kb
Host	smart-e96beba6-32ba-4c5f-bce5-067549f6d260
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=377416465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.377416465
Directory	/workspace/39.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/39.lc_ctrl_jtag_access.3247365835
Short name	T673
Test name
Test status
Simulation time	637770596 ps
CPU time	2.85 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:16 PM PDT 24
Peak memory	217104 kb
Host	smart-c46e4c87-dbc1-441c-bcc5-1d07bc6042ce
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247365835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3247365835
Directory	/workspace/39.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/39.lc_ctrl_prog_failure.3170407312
Short name	T722
Test name
Test status
Simulation time	41513389 ps
CPU time	2.72 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:19 PM PDT 24
Peak memory	218296 kb
Host	smart-fbff7479-102f-4f93-9d9d-700b04aa1da2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3170407312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3170407312
Directory	/workspace/39.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_mubi.3612833684
Short name	T465
Test name
Test status
Simulation time	1535386068 ps
CPU time	14.36 seconds
Started	Aug 17 06:33:07 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	226052 kb
Host	smart-86c678f8-d155-4ab2-b870-02224c91ffcf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612833684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3612833684
Directory	/workspace/39.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_digest.513913002
Short name	T841
Test name
Test status
Simulation time	1248461471 ps
CPU time	21.72 seconds
Started	Aug 17 06:33:12 PM PDT 24
Finished	Aug 17 06:33:34 PM PDT 24
Peak memory	226004 kb
Host	smart-19669c06-71dc-43d5-8afe-eb3fb8970013
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513913002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di gest.513913002
Directory	/workspace/39.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/39.lc_ctrl_sec_token_mux.2360650619
Short name	T15
Test name
Test status
Simulation time	791354904 ps
CPU time	13.23 seconds
Started	Aug 17 06:33:09 PM PDT 24
Finished	Aug 17 06:33:22 PM PDT 24
Peak memory	218136 kb
Host	smart-488fceb7-f6e8-4d17-80f9-a6da1d19cc58
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360650619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux. 2360650619
Directory	/workspace/39.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/39.lc_ctrl_security_escalation.2917878922
Short name	T473
Test name
Test status
Simulation time	614844363 ps
CPU time	12.74 seconds
Started	Aug 17 06:33:14 PM PDT 24
Finished	Aug 17 06:33:27 PM PDT 24
Peak memory	225652 kb
Host	smart-acb21c76-399d-4482-93dc-bd3534c9ca32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2917878922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2917878922
Directory	/workspace/39.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/39.lc_ctrl_smoke.3449329565
Short name	T255
Test name
Test status
Simulation time	75997973 ps
CPU time	2.81 seconds
Started	Aug 17 06:33:18 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	217644 kb
Host	smart-fdfb80c3-8e45-4e93-948f-b821c2b9f57d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449329565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3449329565
Directory	/workspace/39.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_failure.1547578444
Short name	T647
Test name
Test status
Simulation time	1324862414 ps
CPU time	24.5 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:34 PM PDT 24
Peak memory	250900 kb
Host	smart-270b59e0-d5e5-4ee0-a571-d56839347941
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1547578444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1547578444
Directory	/workspace/39.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/39.lc_ctrl_state_post_trans.3975928384
Short name	T716
Test name
Test status
Simulation time	316054711 ps
CPU time	3.1 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:13 PM PDT 24
Peak memory	222168 kb
Host	smart-0225e231-8998-4dab-b529-f5d4889f10d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3975928384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3975928384
Directory	/workspace/39.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/39.lc_ctrl_stress_all.1986514172
Short name	T828
Test name
Test status
Simulation time	16345549025 ps
CPU time	24.49 seconds
Started	Aug 17 06:33:17 PM PDT 24
Finished	Aug 17 06:33:42 PM PDT 24
Peak memory	226228 kb
Host	smart-2a0f384e-b85e-442c-9fc1-7016b6e8c41f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986514172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all.1986514172
Directory	/workspace/39.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.793443597
Short name	T390
Test name
Test status
Simulation time	51738772 ps
CPU time	0.86 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:16 PM PDT 24
Peak memory	211876 kb
Host	smart-6d520845-44e6-44d6-8112-f76e8527f608
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793443597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct rl_volatile_unlock_smoke.793443597
Directory	/workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_alert_test.1029901105
Short name	T336
Test name
Test status
Simulation time	72748042 ps
CPU time	0.89 seconds
Started	Aug 17 06:32:11 PM PDT 24
Finished	Aug 17 06:32:12 PM PDT 24
Peak memory	208812 kb
Host	smart-036a429a-4a77-4d17-b3d2-ccef5183609e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029901105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1029901105
Directory	/workspace/4.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.lc_ctrl_errors.2964767456
Short name	T17
Test name
Test status
Simulation time	349312891 ps
CPU time	15.49 seconds
Started	Aug 17 06:31:49 PM PDT 24
Finished	Aug 17 06:32:04 PM PDT 24
Peak memory	226084 kb
Host	smart-05922063-932d-455b-992f-3af10f3d2d63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2964767456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2964767456
Directory	/workspace/4.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_access.100454281
Short name	T707
Test name
Test status
Simulation time	797978595 ps
CPU time	9.36 seconds
Started	Aug 17 06:32:04 PM PDT 24
Finished	Aug 17 06:32:14 PM PDT 24
Peak memory	217348 kb
Host	smart-dceffb0a-335b-4f08-b1e6-35608817f932
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100454281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.100454281
Directory	/workspace/4.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_errors.167528191
Short name	T549
Test name
Test status
Simulation time	2496161658 ps
CPU time	72.87 seconds
Started	Aug 17 06:32:10 PM PDT 24
Finished	Aug 17 06:33:23 PM PDT 24
Peak memory	218332 kb
Host	smart-9377f155-ae1a-4c09-bc66-24b6fb6fcc3b
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167528191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err ors.167528191
Directory	/workspace/4.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_priority.615300685
Short name	T367
Test name
Test status
Simulation time	2233563206 ps
CPU time	49.81 seconds
Started	Aug 17 06:32:15 PM PDT 24
Finished	Aug 17 06:33:05 PM PDT 24
Peak memory	217784 kb
Host	smart-58dd93c6-ad96-46cd-b0ba-734aef692ea2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615300685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.615300685
Directory	/workspace/4.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.314533947
Short name	T869
Test name
Test status
Simulation time	1764213934 ps
CPU time	11.83 seconds
Started	Aug 17 06:32:10 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	218220 kb
Host	smart-32b775d3-526d-4a0d-836a-9af9a403f0c1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314533947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_ prog_failure.314533947
Directory	/workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2303330676
Short name	T781
Test name
Test status
Simulation time	936876931 ps
CPU time	28.95 seconds
Started	Aug 17 06:31:48 PM PDT 24
Finished	Aug 17 06:32:17 PM PDT 24
Peak memory	217568 kb
Host	smart-a88615d1-708a-4e8a-af1a-82dce460e9cf
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303330676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_regwen_during_op.2303330676
Directory	/workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_smoke.2770240389
Short name	T655
Test name
Test status
Simulation time	364788551 ps
CPU time	5.67 seconds
Started	Aug 17 06:32:05 PM PDT 24
Finished	Aug 17 06:32:11 PM PDT 24
Peak memory	217580 kb
Host	smart-013b1200-2f1f-4904-98b8-273064d2bf5a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770240389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke. 2770240389
Directory	/workspace/4.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_failure.768722003
Short name	T663
Test name
Test status
Simulation time	3030084483 ps
CPU time	53.99 seconds
Started	Aug 17 06:31:47 PM PDT 24
Finished	Aug 17 06:32:41 PM PDT 24
Peak memory	275412 kb
Host	smart-a5f29156-211b-4cc4-a7e0-07ec8f0b0657
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768722003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag _state_failure.768722003
Directory	/workspace/4.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3144599275
Short name	T161
Test name
Test status
Simulation time	7282768777 ps
CPU time	16.1 seconds
Started	Aug 17 06:31:51 PM PDT 24
Finished	Aug 17 06:32:07 PM PDT 24
Peak memory	250660 kb
Host	smart-073fe8ea-8790-4d70-bcbb-7de4cec72d23
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144599275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_state_post_trans.3144599275
Directory	/workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_prog_failure.3143575674
Short name	T143
Test name
Test status
Simulation time	114607852 ps
CPU time	4.71 seconds
Started	Aug 17 06:31:47 PM PDT 24
Finished	Aug 17 06:31:52 PM PDT 24
Peak memory	218128 kb
Host	smart-05b2f0d9-b105-44e0-9d0d-fed1fbb6d89c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143575674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3143575674
Directory	/workspace/4.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_regwen_during_op.3767071906
Short name	T570
Test name
Test status
Simulation time	294431552 ps
CPU time	19.37 seconds
Started	Aug 17 06:31:38 PM PDT 24
Finished	Aug 17 06:31:57 PM PDT 24
Peak memory	214612 kb
Host	smart-3ccb2c3a-8a59-48d7-a53c-cdb3c2e744f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3767071906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3767071906
Directory	/workspace/4.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_cm.1506157387
Short name	T89
Test name
Test status
Simulation time	213283673 ps
CPU time	35.59 seconds
Started	Aug 17 06:31:32 PM PDT 24
Finished	Aug 17 06:32:08 PM PDT 24
Peak memory	282644 kb
Host	smart-f3da90c0-63da-4fea-beeb-834837ad2b22
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506157387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1506157387
Directory	/workspace/4.lc_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_mubi.2525022391
Short name	T219
Test name
Test status
Simulation time	690734579 ps
CPU time	14.44 seconds
Started	Aug 17 06:31:53 PM PDT 24
Finished	Aug 17 06:32:08 PM PDT 24
Peak memory	225992 kb
Host	smart-c51f6541-f910-45d5-a837-b3f14a7b0480
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525022391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2525022391
Directory	/workspace/4.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_digest.2326479519
Short name	T660
Test name
Test status
Simulation time	316709494 ps
CPU time	12.31 seconds
Started	Aug 17 06:32:03 PM PDT 24
Finished	Aug 17 06:32:15 PM PDT 24
Peak memory	225932 kb
Host	smart-a8f7594f-0c59-46b8-9461-716f7efbdbbc
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326479519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di gest.2326479519
Directory	/workspace/4.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/4.lc_ctrl_sec_token_mux.886304910
Short name	T342
Test name
Test status
Simulation time	2545975297 ps
CPU time	14 seconds
Started	Aug 17 06:31:51 PM PDT 24
Finished	Aug 17 06:32:06 PM PDT 24
Peak memory	226064 kb
Host	smart-2034322e-2784-40d5-a4ba-71767c2bf4b5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886304910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.886304910
Directory	/workspace/4.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/4.lc_ctrl_security_escalation.2655675730
Short name	T713
Test name
Test status
Simulation time	244420563 ps
CPU time	9.13 seconds
Started	Aug 17 06:32:01 PM PDT 24
Finished	Aug 17 06:32:11 PM PDT 24
Peak memory	218272 kb
Host	smart-061c4684-08d2-4a5a-b1fc-2b1eea0017ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2655675730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2655675730
Directory	/workspace/4.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/4.lc_ctrl_smoke.3670127130
Short name	T463
Test name
Test status
Simulation time	57793445 ps
CPU time	2.29 seconds
Started	Aug 17 06:31:50 PM PDT 24
Finished	Aug 17 06:31:52 PM PDT 24
Peak memory	214332 kb
Host	smart-19f84282-0d51-4b9e-9ef6-e95c9133cc3e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670127130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3670127130
Directory	/workspace/4.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_failure.1441868341
Short name	T675
Test name
Test status
Simulation time	886736205 ps
CPU time	22.23 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:41 PM PDT 24
Peak memory	250900 kb
Host	smart-28055706-732e-4cb1-9af9-6992062588a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441868341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1441868341
Directory	/workspace/4.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/4.lc_ctrl_state_post_trans.183243664
Short name	T426
Test name
Test status
Simulation time	75590667 ps
CPU time	3.29 seconds
Started	Aug 17 06:31:46 PM PDT 24
Finished	Aug 17 06:31:49 PM PDT 24
Peak memory	222408 kb
Host	smart-63bc6984-3ddf-4b67-a877-efff697cf318
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183243664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.183243664
Directory	/workspace/4.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/4.lc_ctrl_stress_all.3724999932
Short name	T76
Test name
Test status
Simulation time	8479784206 ps
CPU time	56.98 seconds
Started	Aug 17 06:31:59 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	270300 kb
Host	smart-5dfee5b3-ac43-4f66-bc7f-f5ede754437e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724999932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all.3724999932
Directory	/workspace/4.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.357524897
Short name	T134
Test name
Test status
Simulation time	5024944280 ps
CPU time	35.89 seconds
Started	Aug 17 06:31:47 PM PDT 24
Finished	Aug 17 06:32:23 PM PDT 24
Peak memory	254200 kb
Host	smart-9439a17c-052b-4a06-a3e2-bc45dfb750aa
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=357524897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.357524897
Directory	/workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3387998918
Short name	T475
Test name
Test status
Simulation time	78087627 ps
CPU time	1.02 seconds
Started	Aug 17 06:31:54 PM PDT 24
Finished	Aug 17 06:31:55 PM PDT 24
Peak memory	212952 kb
Host	smart-d17c9e84-7c70-4a35-ad45-8d8ae0d2ede7
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387998918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct rl_volatile_unlock_smoke.3387998918
Directory	/workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_alert_test.2743164457
Short name	T871
Test name
Test status
Simulation time	84973321 ps
CPU time	1.06 seconds
Started	Aug 17 06:33:01 PM PDT 24
Finished	Aug 17 06:33:03 PM PDT 24
Peak memory	208992 kb
Host	smart-5bd00750-d9d0-4fa0-9ad7-016a1000383c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743164457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2743164457
Directory	/workspace/40.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.lc_ctrl_errors.2670594491
Short name	T579
Test name
Test status
Simulation time	1707055358 ps
CPU time	11.52 seconds
Started	Aug 17 06:33:05 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	218136 kb
Host	smart-d62e6419-e1b9-4666-b1f2-6105a56d0ebf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670594491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2670594491
Directory	/workspace/40.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/40.lc_ctrl_jtag_access.1394734001
Short name	T820
Test name
Test status
Simulation time	647947966 ps
CPU time	8 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:24 PM PDT 24
Peak memory	217100 kb
Host	smart-9baed0de-3751-4991-af1b-8b2747b9434b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394734001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1394734001
Directory	/workspace/40.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/40.lc_ctrl_prog_failure.2943465755
Short name	T315
Test name
Test status
Simulation time	28439329 ps
CPU time	2.14 seconds
Started	Aug 17 06:33:03 PM PDT 24
Finished	Aug 17 06:33:05 PM PDT 24
Peak memory	218260 kb
Host	smart-5e481081-b6a1-4b78-8ea1-9974f8648e8c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943465755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2943465755
Directory	/workspace/40.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_mubi.511516422
Short name	T694
Test name
Test status
Simulation time	180969858 ps
CPU time	9.99 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:23 PM PDT 24
Peak memory	226044 kb
Host	smart-2312596b-8735-4831-928f-6ff7df4eb012
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511516422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.511516422
Directory	/workspace/40.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_digest.3100898786
Short name	T872
Test name
Test status
Simulation time	333960688 ps
CPU time	11.15 seconds
Started	Aug 17 06:33:08 PM PDT 24
Finished	Aug 17 06:33:19 PM PDT 24
Peak memory	226020 kb
Host	smart-1cbe0799-5fec-4e91-ba93-7a2a99ac1bc9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100898786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d igest.3100898786
Directory	/workspace/40.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/40.lc_ctrl_sec_token_mux.2452230991
Short name	T481
Test name
Test status
Simulation time	1436456846 ps
CPU time	13.11 seconds
Started	Aug 17 06:33:11 PM PDT 24
Finished	Aug 17 06:33:25 PM PDT 24
Peak memory	225992 kb
Host	smart-0f8e0048-a3c4-4f53-a344-537cea7b4d09
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452230991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux. 2452230991
Directory	/workspace/40.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/40.lc_ctrl_security_escalation.3819758610
Short name	T50
Test name
Test status
Simulation time	677120618 ps
CPU time	8.43 seconds
Started	Aug 17 06:33:08 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	226092 kb
Host	smart-8dabcdb6-d8b1-4d45-9f86-05eadd573713
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3819758610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3819758610
Directory	/workspace/40.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/40.lc_ctrl_smoke.3516733593
Short name	T526
Test name
Test status
Simulation time	28958122 ps
CPU time	1.94 seconds
Started	Aug 17 06:33:18 PM PDT 24
Finished	Aug 17 06:33:25 PM PDT 24
Peak memory	214012 kb
Host	smart-5f5e391c-2aaa-46e5-a18a-91aebf9f73c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516733593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3516733593
Directory	/workspace/40.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_failure.2059289719
Short name	T441
Test name
Test status
Simulation time	753314891 ps
CPU time	21.57 seconds
Started	Aug 17 06:33:12 PM PDT 24
Finished	Aug 17 06:33:43 PM PDT 24
Peak memory	250916 kb
Host	smart-34530f89-7601-4591-85b4-31bbc461cbe6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2059289719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2059289719
Directory	/workspace/40.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/40.lc_ctrl_state_post_trans.2855103341
Short name	T319
Test name
Test status
Simulation time	722844992 ps
CPU time	7.63 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:23 PM PDT 24
Peak memory	250828 kb
Host	smart-33e3cd49-4e16-4e81-9a0c-ed182c0e5b83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2855103341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2855103341
Directory	/workspace/40.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/40.lc_ctrl_stress_all.95299690
Short name	T638
Test name
Test status
Simulation time	4318068584 ps
CPU time	68.01 seconds
Started	Aug 17 06:33:09 PM PDT 24
Finished	Aug 17 06:34:17 PM PDT 24
Peak memory	279824 kb
Host	smart-eba0560c-a5d0-45f4-a052-cc4b3c46d7b1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95299690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.lc_ctrl_stress_all.95299690
Directory	/workspace/40.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.4178346015
Short name	T398
Test name
Test status
Simulation time	44067718 ps
CPU time	0.82 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:14 PM PDT 24
Peak memory	211960 kb
Host	smart-e583f1bf-31c5-49de-8136-7c431fd9a441
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178346015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c trl_volatile_unlock_smoke.4178346015
Directory	/workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_alert_test.3639315453
Short name	T254
Test name
Test status
Simulation time	14755953 ps
CPU time	0.89 seconds
Started	Aug 17 06:33:06 PM PDT 24
Finished	Aug 17 06:33:07 PM PDT 24
Peak memory	208680 kb
Host	smart-459cb755-7c1f-4aaf-b234-6296083353b2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639315453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3639315453
Directory	/workspace/41.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.lc_ctrl_errors.592901292
Short name	T656
Test name
Test status
Simulation time	1175002965 ps
CPU time	10.25 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:26 PM PDT 24
Peak memory	226084 kb
Host	smart-4d67cc72-9783-45a0-b7ad-0aa2642276b4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592901292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.592901292
Directory	/workspace/41.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/41.lc_ctrl_jtag_access.566597865
Short name	T365
Test name
Test status
Simulation time	2420317072 ps
CPU time	7.52 seconds
Started	Aug 17 06:33:14 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	217528 kb
Host	smart-23db8b28-b18d-41a8-a86a-755d5412e23b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566597865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.566597865
Directory	/workspace/41.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/41.lc_ctrl_prog_failure.2831440473
Short name	T793
Test name
Test status
Simulation time	21095423 ps
CPU time	1.6 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:12 PM PDT 24
Peak memory	218248 kb
Host	smart-2743743b-5e4c-4249-ae85-00b7f206b338
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2831440473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2831440473
Directory	/workspace/41.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_mubi.2840312808
Short name	T502
Test name
Test status
Simulation time	226682513 ps
CPU time	8.32 seconds
Started	Aug 17 06:33:18 PM PDT 24
Finished	Aug 17 06:33:27 PM PDT 24
Peak memory	218860 kb
Host	smart-a3d153b6-b074-406e-916e-6d0b16f42378
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840312808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2840312808
Directory	/workspace/41.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_digest.4163493222
Short name	T204
Test name
Test status
Simulation time	1194314792 ps
CPU time	11.85 seconds
Started	Aug 17 06:33:07 PM PDT 24
Finished	Aug 17 06:33:19 PM PDT 24
Peak memory	225988 kb
Host	smart-151e61ca-7710-477c-80cb-9e7c44e8597c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163493222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d igest.4163493222
Directory	/workspace/41.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/41.lc_ctrl_sec_token_mux.3074932792
Short name	T816
Test name
Test status
Simulation time	1935447734 ps
CPU time	10.37 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:26 PM PDT 24
Peak memory	218168 kb
Host	smart-33f13afd-ede6-4c01-8a54-81d288538c74
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074932792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux. 3074932792
Directory	/workspace/41.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/41.lc_ctrl_security_escalation.3976929348
Short name	T151
Test name
Test status
Simulation time	678241454 ps
CPU time	13.19 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:28 PM PDT 24
Peak memory	226088 kb
Host	smart-8f654d68-ea05-4303-86d1-e791d1b7010b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976929348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3976929348
Directory	/workspace/41.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/41.lc_ctrl_smoke.2470363368
Short name	T774
Test name
Test status
Simulation time	21263877 ps
CPU time	1.69 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	213764 kb
Host	smart-6b2217ff-7e5a-4c97-8312-977352aeb675
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2470363368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2470363368
Directory	/workspace/41.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_failure.3935979529
Short name	T741
Test name
Test status
Simulation time	1062434054 ps
CPU time	19.81 seconds
Started	Aug 17 06:33:14 PM PDT 24
Finished	Aug 17 06:33:34 PM PDT 24
Peak memory	250912 kb
Host	smart-ce444a1c-2b5c-4498-b39a-500ba486c871
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935979529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3935979529
Directory	/workspace/41.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/41.lc_ctrl_state_post_trans.2207959514
Short name	T710
Test name
Test status
Simulation time	112543112 ps
CPU time	10.09 seconds
Started	Aug 17 06:33:11 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	250840 kb
Host	smart-437eebbf-f881-47a6-af6f-f8979ab93326
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2207959514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2207959514
Directory	/workspace/41.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/41.lc_ctrl_stress_all.600423516
Short name	T163
Test name
Test status
Simulation time	5323607878 ps
CPU time	53.42 seconds
Started	Aug 17 06:33:17 PM PDT 24
Finished	Aug 17 06:34:11 PM PDT 24
Peak memory	249488 kb
Host	smart-37b0dc6a-1e21-4618-9bb3-108486f754c8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600423516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all.600423516
Directory	/workspace/41.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4019649997
Short name	T603
Test name
Test status
Simulation time	16020719 ps
CPU time	0.91 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	217676 kb
Host	smart-15062070-153f-477e-bfdf-b2860bc82b3e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019649997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c trl_volatile_unlock_smoke.4019649997
Directory	/workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_alert_test.990209717
Short name	T251
Test name
Test status
Simulation time	12088495 ps
CPU time	0.95 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:15 PM PDT 24
Peak memory	208896 kb
Host	smart-846f5c7e-d5b8-4632-aff1-df7d14e94f4c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990209717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.990209717
Directory	/workspace/42.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.lc_ctrl_errors.487345927
Short name	T821
Test name
Test status
Simulation time	283204799 ps
CPU time	13.43 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:24 PM PDT 24
Peak memory	218288 kb
Host	smart-12a70c94-86e1-4fdd-88c2-87a916ab2ec1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487345927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.487345927
Directory	/workspace/42.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/42.lc_ctrl_jtag_access.1817992450
Short name	T565
Test name
Test status
Simulation time	1159937290 ps
CPU time	3.74 seconds
Started	Aug 17 06:33:11 PM PDT 24
Finished	Aug 17 06:33:15 PM PDT 24
Peak memory	217116 kb
Host	smart-8d4b0047-4a8d-4d57-9a96-00c559c7de58
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817992450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1817992450
Directory	/workspace/42.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/42.lc_ctrl_prog_failure.1909637661
Short name	T474
Test name
Test status
Simulation time	27039330 ps
CPU time	2.07 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:18 PM PDT 24
Peak memory	218216 kb
Host	smart-d1a3b352-38ff-4504-868d-9c6be47fbe0c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1909637661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.1909637661
Directory	/workspace/42.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_mubi.489828500
Short name	T410
Test name
Test status
Simulation time	1278035837 ps
CPU time	11.68 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:26 PM PDT 24
Peak memory	226076 kb
Host	smart-a72366fb-f6e8-4300-a1d4-fe17072fcd47
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489828500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.489828500
Directory	/workspace/42.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_digest.4030894632
Short name	T317
Test name
Test status
Simulation time	331218477 ps
CPU time	7.83 seconds
Started	Aug 17 06:33:12 PM PDT 24
Finished	Aug 17 06:33:20 PM PDT 24
Peak memory	225932 kb
Host	smart-80c293ef-d73c-477a-83f9-82396a3e397f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030894632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d igest.4030894632
Directory	/workspace/42.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/42.lc_ctrl_sec_token_mux.518842216
Short name	T378
Test name
Test status
Simulation time	324484351 ps
CPU time	8.67 seconds
Started	Aug 17 06:33:18 PM PDT 24
Finished	Aug 17 06:33:27 PM PDT 24
Peak memory	218224 kb
Host	smart-72a0223f-646a-4d9c-95be-2496ea1fb658
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518842216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.518842216
Directory	/workspace/42.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/42.lc_ctrl_security_escalation.958663361
Short name	T453
Test name
Test status
Simulation time	179969492 ps
CPU time	6.46 seconds
Started	Aug 17 06:33:00 PM PDT 24
Finished	Aug 17 06:33:07 PM PDT 24
Peak memory	225164 kb
Host	smart-d6ad6e56-fd7f-40da-a87d-3c10b20b9da3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958663361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.958663361
Directory	/workspace/42.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/42.lc_ctrl_smoke.2596333588
Short name	T350
Test name
Test status
Simulation time	168382671 ps
CPU time	1.19 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:14 PM PDT 24
Peak memory	213628 kb
Host	smart-4d729464-c045-4363-b83e-e57c8af91582
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596333588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2596333588
Directory	/workspace/42.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_failure.3425013198
Short name	T221
Test name
Test status
Simulation time	575573647 ps
CPU time	27.7 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:38 PM PDT 24
Peak memory	250832 kb
Host	smart-484e14b6-badd-4b59-84d7-766cb4e9338a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3425013198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3425013198
Directory	/workspace/42.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/42.lc_ctrl_state_post_trans.3810533953
Short name	T541
Test name
Test status
Simulation time	127814778 ps
CPU time	7.33 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	250392 kb
Host	smart-a6093d10-6eee-4cf0-979c-8b6354c971e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3810533953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3810533953
Directory	/workspace/42.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/42.lc_ctrl_stress_all.1262727842
Short name	T699
Test name
Test status
Simulation time	3835970301 ps
CPU time	92.07 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:34:47 PM PDT 24
Peak memory	273640 kb
Host	smart-f8fe9ac1-fc17-439d-b07d-13da8765756b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262727842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all.1262727842
Directory	/workspace/42.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.3018171518
Short name	T87
Test name
Test status
Simulation time	13212599284 ps
CPU time	114.53 seconds
Started	Aug 17 06:33:12 PM PDT 24
Finished	Aug 17 06:35:06 PM PDT 24
Peak memory	260172 kb
Host	smart-265a9dcd-7682-4651-a0de-9d95a4de4e88
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3018171518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.3018171518
Directory	/workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3472726376
Short name	T815
Test name
Test status
Simulation time	43374017 ps
CPU time	0.83 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:14 PM PDT 24
Peak memory	211860 kb
Host	smart-d4d42a9e-3070-48f2-89d2-095e7fc8279b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472726376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c trl_volatile_unlock_smoke.3472726376
Directory	/workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_alert_test.2150377895
Short name	T754
Test name
Test status
Simulation time	111024427 ps
CPU time	0.94 seconds
Started	Aug 17 06:33:11 PM PDT 24
Finished	Aug 17 06:33:13 PM PDT 24
Peak memory	208820 kb
Host	smart-ad8b5d62-c90b-459e-844f-9a07de337df7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150377895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2150377895
Directory	/workspace/43.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.lc_ctrl_errors.2043166315
Short name	T780
Test name
Test status
Simulation time	5547918201 ps
CPU time	12.45 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:26 PM PDT 24
Peak memory	226044 kb
Host	smart-f57222e2-977b-4c37-a535-6e3dbfcb1284
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043166315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2043166315
Directory	/workspace/43.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/43.lc_ctrl_jtag_access.3928815669
Short name	T37
Test name
Test status
Simulation time	1411533228 ps
CPU time	17.91 seconds
Started	Aug 17 06:33:17 PM PDT 24
Finished	Aug 17 06:33:35 PM PDT 24
Peak memory	217372 kb
Host	smart-1a37ee74-01ba-4d31-9508-1b0854737b5c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928815669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3928815669
Directory	/workspace/43.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/43.lc_ctrl_prog_failure.2654591666
Short name	T559
Test name
Test status
Simulation time	66003550 ps
CPU time	3.36 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:20 PM PDT 24
Peak memory	222672 kb
Host	smart-e21a40e6-f674-40b5-b79f-c8e5fe02ce0e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2654591666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2654591666
Directory	/workspace/43.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_mubi.1250941854
Short name	T275
Test name
Test status
Simulation time	812285382 ps
CPU time	13.72 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:24 PM PDT 24
Peak memory	219956 kb
Host	smart-92740884-975f-4105-98d0-508f63c2b9bd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250941854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1250941854
Directory	/workspace/43.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_digest.2591083647
Short name	T632
Test name
Test status
Simulation time	575480412 ps
CPU time	16.08 seconds
Started	Aug 17 06:33:19 PM PDT 24
Finished	Aug 17 06:33:35 PM PDT 24
Peak memory	218200 kb
Host	smart-b7158add-5298-4831-ade7-a8015d6fe48f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591083647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d igest.2591083647
Directory	/workspace/43.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/43.lc_ctrl_sec_token_mux.1399645440
Short name	T804
Test name
Test status
Simulation time	2857058027 ps
CPU time	8.16 seconds
Started	Aug 17 06:33:12 PM PDT 24
Finished	Aug 17 06:33:20 PM PDT 24
Peak memory	225184 kb
Host	smart-de9d6823-41dc-49ba-86ad-86b91c937744
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399645440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux. 1399645440
Directory	/workspace/43.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/43.lc_ctrl_security_escalation.1143939405
Short name	T52
Test name
Test status
Simulation time	248060869 ps
CPU time	9.89 seconds
Started	Aug 17 06:33:18 PM PDT 24
Finished	Aug 17 06:33:28 PM PDT 24
Peak memory	218312 kb
Host	smart-d15d4827-07be-4832-8e90-b42831dc52c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143939405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1143939405
Directory	/workspace/43.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/43.lc_ctrl_smoke.3794830352
Short name	T227
Test name
Test status
Simulation time	227036854 ps
CPU time	1.67 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	217616 kb
Host	smart-fde2a97e-32a9-43ae-a5cf-00410f2ca18f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3794830352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3794830352
Directory	/workspace/43.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_failure.3473419350
Short name	T341
Test name
Test status
Simulation time	727845497 ps
CPU time	22.2 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:35 PM PDT 24
Peak memory	245100 kb
Host	smart-144b7066-3922-4096-a237-0062528e8f07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3473419350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3473419350
Directory	/workspace/43.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/43.lc_ctrl_state_post_trans.262933081
Short name	T635
Test name
Test status
Simulation time	258243038 ps
CPU time	3.93 seconds
Started	Aug 17 06:33:08 PM PDT 24
Finished	Aug 17 06:33:12 PM PDT 24
Peak memory	222268 kb
Host	smart-d06e811a-06fe-44cf-8e0d-7d34bd417427
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262933081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.262933081
Directory	/workspace/43.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/43.lc_ctrl_stress_all.4106264556
Short name	T46
Test name
Test status
Simulation time	86733132544 ps
CPU time	179.84 seconds
Started	Aug 17 06:33:08 PM PDT 24
Finished	Aug 17 06:36:08 PM PDT 24
Peak memory	279800 kb
Host	smart-121db54c-b097-4db8-8e6b-7c1389dd6d1c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106264556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all.4106264556
Directory	/workspace/43.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3385398994
Short name	T850
Test name
Test status
Simulation time	21998825 ps
CPU time	0.84 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:15 PM PDT 24
Peak memory	211372 kb
Host	smart-ef0727ac-c432-4291-aa39-7d52fe2e057e
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385398994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c trl_volatile_unlock_smoke.3385398994
Directory	/workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_alert_test.1143957923
Short name	T512
Test name
Test status
Simulation time	32886894 ps
CPU time	1.05 seconds
Started	Aug 17 06:33:20 PM PDT 24
Finished	Aug 17 06:33:22 PM PDT 24
Peak memory	208892 kb
Host	smart-c7429fae-ed01-4921-bd9c-de0dd84d091d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143957923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1143957923
Directory	/workspace/44.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.lc_ctrl_errors.3889866288
Short name	T794
Test name
Test status
Simulation time	809983102 ps
CPU time	9.95 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:26 PM PDT 24
Peak memory	225988 kb
Host	smart-b40caf1b-e30b-4c54-9c42-e54a8ead8b62
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3889866288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3889866288
Directory	/workspace/44.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/44.lc_ctrl_jtag_access.1478349841
Short name	T38
Test name
Test status
Simulation time	621388197 ps
CPU time	15.41 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:31 PM PDT 24
Peak memory	217324 kb
Host	smart-e5fbe156-6387-48d2-9669-1db386a31cac
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478349841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1478349841
Directory	/workspace/44.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/44.lc_ctrl_prog_failure.1770139739
Short name	T43
Test name
Test status
Simulation time	134756372 ps
CPU time	3.49 seconds
Started	Aug 17 06:33:14 PM PDT 24
Finished	Aug 17 06:33:18 PM PDT 24
Peak memory	218264 kb
Host	smart-ec5f2cb2-2d39-4fe7-b695-be67a0202387
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1770139739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.1770139739
Directory	/workspace/44.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_mubi.1444872549
Short name	T276
Test name
Test status
Simulation time	315347023 ps
CPU time	14.69 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:30 PM PDT 24
Peak memory	226052 kb
Host	smart-da62c9bf-bfad-4dd5-a943-75be20a18138
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444872549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1444872549
Directory	/workspace/44.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_digest.1752685621
Short name	T593
Test name
Test status
Simulation time	5065043524 ps
CPU time	17.32 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:30 PM PDT 24
Peak memory	225976 kb
Host	smart-c9b549bf-c8bc-4aa3-80ee-50b317ddc704
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752685621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d igest.1752685621
Directory	/workspace/44.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/44.lc_ctrl_sec_token_mux.604919712
Short name	T401
Test name
Test status
Simulation time	263141116 ps
CPU time	9.9 seconds
Started	Aug 17 06:33:12 PM PDT 24
Finished	Aug 17 06:33:22 PM PDT 24
Peak memory	225936 kb
Host	smart-ad71c30c-af68-493f-921f-9cd9a262c820
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604919712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.604919712
Directory	/workspace/44.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/44.lc_ctrl_security_escalation.3952712866
Short name	T323
Test name
Test status
Simulation time	426301131 ps
CPU time	11.12 seconds
Started	Aug 17 06:33:11 PM PDT 24
Finished	Aug 17 06:33:22 PM PDT 24
Peak memory	226000 kb
Host	smart-91469b2f-c154-4a65-bcd9-a1da377fcc1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3952712866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3952712866
Directory	/workspace/44.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/44.lc_ctrl_smoke.1279598290
Short name	T79
Test name
Test status
Simulation time	47645457 ps
CPU time	1.92 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:18 PM PDT 24
Peak memory	214168 kb
Host	smart-7434b95f-f7c7-425d-a190-c4c20e25d110
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1279598290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1279598290
Directory	/workspace/44.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_failure.2341581396
Short name	T238
Test name
Test status
Simulation time	260221330 ps
CPU time	28.03 seconds
Started	Aug 17 06:33:12 PM PDT 24
Finished	Aug 17 06:33:40 PM PDT 24
Peak memory	250848 kb
Host	smart-a34b6d6e-2652-4be2-9912-d2f75e88d7dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2341581396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2341581396
Directory	/workspace/44.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/44.lc_ctrl_state_post_trans.1907237555
Short name	T266
Test name
Test status
Simulation time	83508733 ps
CPU time	7.37 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	250336 kb
Host	smart-8ee5371f-1d78-4ac8-a99d-37fc72ef4b50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907237555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1907237555
Directory	/workspace/44.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/44.lc_ctrl_stress_all.3086911547
Short name	T580
Test name
Test status
Simulation time	1340208821 ps
CPU time	31.42 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:47 PM PDT 24
Peak memory	250876 kb
Host	smart-3526a38f-7db9-4170-a752-12d16d0ce9e3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086911547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all.3086911547
Directory	/workspace/44.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.1369281726
Short name	T95
Test name
Test status
Simulation time	18194755382 ps
CPU time	99.3 seconds
Started	Aug 17 06:33:17 PM PDT 24
Finished	Aug 17 06:34:56 PM PDT 24
Peak memory	259272 kb
Host	smart-67429e27-8cb6-457b-ab91-9825338e2d3a
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1369281726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.1369281726
Directory	/workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1653534667
Short name	T349
Test name
Test status
Simulation time	16000327 ps
CPU time	1.09 seconds
Started	Aug 17 06:33:09 PM PDT 24
Finished	Aug 17 06:33:10 PM PDT 24
Peak memory	211972 kb
Host	smart-0d4f54cb-b4d7-4bd9-bb89-9dbfe864f173
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653534667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c trl_volatile_unlock_smoke.1653534667
Directory	/workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_alert_test.3518427980
Short name	T386
Test name
Test status
Simulation time	20629513 ps
CPU time	1.01 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:16 PM PDT 24
Peak memory	208880 kb
Host	smart-68130c0e-79b2-4d49-8323-d40a05095bb1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518427980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3518427980
Directory	/workspace/45.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.lc_ctrl_errors.4097705324
Short name	T582
Test name
Test status
Simulation time	1792681157 ps
CPU time	12.25 seconds
Started	Aug 17 06:33:14 PM PDT 24
Finished	Aug 17 06:33:26 PM PDT 24
Peak memory	218160 kb
Host	smart-3911e7fc-2e1f-40be-9ff6-ddeda4a546b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097705324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.4097705324
Directory	/workspace/45.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/45.lc_ctrl_prog_failure.3201851166
Short name	T337
Test name
Test status
Simulation time	356971069 ps
CPU time	3.41 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:19 PM PDT 24
Peak memory	218240 kb
Host	smart-3acf687d-4ebd-45b7-af2d-303cda7765b5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3201851166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3201851166
Directory	/workspace/45.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_mubi.2044949987
Short name	T479
Test name
Test status
Simulation time	2148735877 ps
CPU time	21.31 seconds
Started	Aug 17 06:33:09 PM PDT 24
Finished	Aug 17 06:33:30 PM PDT 24
Peak memory	225988 kb
Host	smart-31f98d10-d950-4113-9c00-cd45df63900f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044949987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2044949987
Directory	/workspace/45.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_digest.1729585056
Short name	T343
Test name
Test status
Simulation time	1558754838 ps
CPU time	8.17 seconds
Started	Aug 17 06:33:07 PM PDT 24
Finished	Aug 17 06:33:16 PM PDT 24
Peak memory	224700 kb
Host	smart-c61106d9-a8d1-496c-b99d-8a29b8daa863
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729585056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d igest.1729585056
Directory	/workspace/45.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/45.lc_ctrl_sec_token_mux.2289387803
Short name	T418
Test name
Test status
Simulation time	1122662675 ps
CPU time	7.56 seconds
Started	Aug 17 06:33:14 PM PDT 24
Finished	Aug 17 06:33:22 PM PDT 24
Peak memory	218208 kb
Host	smart-c4558023-5059-4020-8a87-4137faf86d4d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289387803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux. 2289387803
Directory	/workspace/45.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/45.lc_ctrl_security_escalation.2348927722
Short name	T44
Test name
Test status
Simulation time	289224891 ps
CPU time	11.15 seconds
Started	Aug 17 06:33:22 PM PDT 24
Finished	Aug 17 06:33:38 PM PDT 24
Peak memory	218360 kb
Host	smart-6048665e-aa9f-4785-9b1c-2000071c31cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348927722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2348927722
Directory	/workspace/45.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/45.lc_ctrl_smoke.2389457763
Short name	T12
Test name
Test status
Simulation time	55550139 ps
CPU time	1.33 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	213608 kb
Host	smart-9d37e712-0b4a-4edb-84e4-fdc625b0b5ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389457763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2389457763
Directory	/workspace/45.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_failure.3572813556
Short name	T228
Test name
Test status
Simulation time	547329099 ps
CPU time	29.77 seconds
Started	Aug 17 06:33:12 PM PDT 24
Finished	Aug 17 06:33:42 PM PDT 24
Peak memory	250868 kb
Host	smart-4d749d5f-4e24-46b4-aefa-459e5e2e8ed7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3572813556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3572813556
Directory	/workspace/45.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/45.lc_ctrl_state_post_trans.2512534037
Short name	T744
Test name
Test status
Simulation time	442686391 ps
CPU time	7.69 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:23 PM PDT 24
Peak memory	250912 kb
Host	smart-be69a025-e5c9-48e3-a23f-a409373bfbce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512534037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2512534037
Directory	/workspace/45.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/45.lc_ctrl_stress_all.2270426095
Short name	T835
Test name
Test status
Simulation time	103109045604 ps
CPU time	415.78 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:40:06 PM PDT 24
Peak memory	250956 kb
Host	smart-b333cdb6-4c0a-4933-8fdc-c4b50aa0acda
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270426095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all.2270426095
Directory	/workspace/45.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2704442266
Short name	T334
Test name
Test status
Simulation time	34640082 ps
CPU time	0.82 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:16 PM PDT 24
Peak memory	211880 kb
Host	smart-8473f896-30a4-4b56-94a6-e34f302fd21b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704442266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c trl_volatile_unlock_smoke.2704442266
Directory	/workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_alert_test.1619275943
Short name	T484
Test name
Test status
Simulation time	27176966 ps
CPU time	0.81 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	208648 kb
Host	smart-0a907078-fdb2-46f0-a747-34b12a820c51
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619275943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1619275943
Directory	/workspace/46.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.lc_ctrl_errors.1103455375
Short name	T208
Test name
Test status
Simulation time	1477681832 ps
CPU time	26.1 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:41 PM PDT 24
Peak memory	226072 kb
Host	smart-a57c783b-4a69-4742-8731-694b0847c9ff
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1103455375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1103455375
Directory	/workspace/46.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/46.lc_ctrl_jtag_access.950126387
Short name	T10
Test name
Test status
Simulation time	153147935 ps
CPU time	4.44 seconds
Started	Aug 17 06:33:10 PM PDT 24
Finished	Aug 17 06:33:14 PM PDT 24
Peak memory	217640 kb
Host	smart-ffddfe7e-1036-4a94-9d38-9601906b8f50
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950126387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.950126387
Directory	/workspace/46.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/46.lc_ctrl_prog_failure.240828290
Short name	T653
Test name
Test status
Simulation time	106905038 ps
CPU time	3.29 seconds
Started	Aug 17 06:33:07 PM PDT 24
Finished	Aug 17 06:33:11 PM PDT 24
Peak memory	222420 kb
Host	smart-11e247c3-a12a-4158-880e-60ebafc02677
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240828290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.240828290
Directory	/workspace/46.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_mubi.1692798797
Short name	T812
Test name
Test status
Simulation time	614994512 ps
CPU time	16.99 seconds
Started	Aug 17 06:33:09 PM PDT 24
Finished	Aug 17 06:33:26 PM PDT 24
Peak memory	218996 kb
Host	smart-541dbe22-d249-440d-8334-65fe432e898c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692798797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1692798797
Directory	/workspace/46.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_digest.697116136
Short name	T279
Test name
Test status
Simulation time	1525203426 ps
CPU time	15.19 seconds
Started	Aug 17 06:33:11 PM PDT 24
Finished	Aug 17 06:33:26 PM PDT 24
Peak memory	225976 kb
Host	smart-6bef51bb-2ac8-4f2c-b411-f82d6bc2cd9f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697116136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di gest.697116136
Directory	/workspace/46.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/46.lc_ctrl_sec_token_mux.698920419
Short name	T438
Test name
Test status
Simulation time	1398444827 ps
CPU time	13.22 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:28 PM PDT 24
Peak memory	218164 kb
Host	smart-be5bbc50-de74-4e36-b862-d5c73859824d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698920419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.698920419
Directory	/workspace/46.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/46.lc_ctrl_security_escalation.1828828430
Short name	T523
Test name
Test status
Simulation time	1671784744 ps
CPU time	9.84 seconds
Started	Aug 17 06:33:31 PM PDT 24
Finished	Aug 17 06:33:41 PM PDT 24
Peak memory	225892 kb
Host	smart-89c2252a-071c-4136-a7f7-7aed8db6f7dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1828828430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1828828430
Directory	/workspace/46.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/46.lc_ctrl_smoke.3137357782
Short name	T840
Test name
Test status
Simulation time	297563151 ps
CPU time	7.98 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:22 PM PDT 24
Peak memory	217656 kb
Host	smart-7c88c700-f5e3-4378-a99a-abb5f27dbc2b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3137357782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3137357782
Directory	/workspace/46.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_failure.1737742134
Short name	T641
Test name
Test status
Simulation time	980186777 ps
CPU time	17.75 seconds
Started	Aug 17 06:33:11 PM PDT 24
Finished	Aug 17 06:33:29 PM PDT 24
Peak memory	250652 kb
Host	smart-8c8b4f85-e217-4403-9e51-b9f603be15cb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1737742134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1737742134
Directory	/workspace/46.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/46.lc_ctrl_state_post_trans.3217254281
Short name	T284
Test name
Test status
Simulation time	256999240 ps
CPU time	3.99 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:18 PM PDT 24
Peak memory	222184 kb
Host	smart-1eec542f-f94a-4b6d-b0e7-f19f56b15573
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217254281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3217254281
Directory	/workspace/46.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/46.lc_ctrl_stress_all.3930945659
Short name	T858
Test name
Test status
Simulation time	152088970584 ps
CPU time	498.82 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:41:34 PM PDT 24
Peak memory	267328 kb
Host	smart-a28c2917-9b9f-460c-a460-23f8f4ac0fa4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930945659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all.3930945659
Directory	/workspace/46.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2912435344
Short name	T184
Test name
Test status
Simulation time	22862944 ps
CPU time	0.96 seconds
Started	Aug 17 06:33:12 PM PDT 24
Finished	Aug 17 06:33:13 PM PDT 24
Peak memory	211796 kb
Host	smart-45bbd107-6bac-4e8c-bc70-525ea6a14fac
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912435344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c trl_volatile_unlock_smoke.2912435344
Directory	/workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_alert_test.2672805337
Short name	T533
Test name
Test status
Simulation time	28478061 ps
CPU time	0.86 seconds
Started	Aug 17 06:33:19 PM PDT 24
Finished	Aug 17 06:33:20 PM PDT 24
Peak memory	208656 kb
Host	smart-b53e8670-d8d6-4a3f-9378-16876bee3a9d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672805337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2672805337
Directory	/workspace/47.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.lc_ctrl_errors.1349605317
Short name	T260
Test name
Test status
Simulation time	993979706 ps
CPU time	9.39 seconds
Started	Aug 17 06:33:14 PM PDT 24
Finished	Aug 17 06:33:24 PM PDT 24
Peak memory	226056 kb
Host	smart-364b748c-c8c6-4926-af85-a093d7805246
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349605317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1349605317
Directory	/workspace/47.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/47.lc_ctrl_jtag_access.513401903
Short name	T864
Test name
Test status
Simulation time	518065863 ps
CPU time	1.11 seconds
Started	Aug 17 06:33:14 PM PDT 24
Finished	Aug 17 06:33:15 PM PDT 24
Peak memory	216988 kb
Host	smart-f16a06a6-413f-4e14-9e4a-f74966e8bcc5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513401903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.513401903
Directory	/workspace/47.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/47.lc_ctrl_prog_failure.617671525
Short name	T566
Test name
Test status
Simulation time	42822810 ps
CPU time	2.06 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	218332 kb
Host	smart-3748e669-148b-4645-b5b0-e30f4fcd0373
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=617671525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.617671525
Directory	/workspace/47.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_mubi.1926443730
Short name	T784
Test name
Test status
Simulation time	1246932761 ps
CPU time	23.15 seconds
Started	Aug 17 06:33:20 PM PDT 24
Finished	Aug 17 06:33:44 PM PDT 24
Peak memory	226064 kb
Host	smart-135c5c70-8486-4560-89a8-b2b6aed48fb3
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926443730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1926443730
Directory	/workspace/47.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_digest.487118444
Short name	T802
Test name
Test status
Simulation time	297399396 ps
CPU time	10.86 seconds
Started	Aug 17 06:33:17 PM PDT 24
Finished	Aug 17 06:33:28 PM PDT 24
Peak memory	226012 kb
Host	smart-54e0f62e-1043-4ef3-8197-039f3264aa63
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487118444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di gest.487118444
Directory	/workspace/47.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/47.lc_ctrl_sec_token_mux.3328302825
Short name	T290
Test name
Test status
Simulation time	2747436083 ps
CPU time	8.5 seconds
Started	Aug 17 06:33:12 PM PDT 24
Finished	Aug 17 06:33:20 PM PDT 24
Peak memory	218264 kb
Host	smart-f8c85212-6b31-448c-8321-45104a70bb6e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328302825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux. 3328302825
Directory	/workspace/47.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/47.lc_ctrl_security_escalation.1062065057
Short name	T382
Test name
Test status
Simulation time	318784308 ps
CPU time	8.45 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:23 PM PDT 24
Peak memory	225388 kb
Host	smart-26aa16f1-4e8c-4f75-81ab-7f7db0ab17df
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1062065057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1062065057
Directory	/workspace/47.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/47.lc_ctrl_smoke.963035696
Short name	T220
Test name
Test status
Simulation time	56367639 ps
CPU time	2.13 seconds
Started	Aug 17 06:33:15 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	214352 kb
Host	smart-37627568-8668-435a-b5a1-16e25e2b02cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963035696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.963035696
Directory	/workspace/47.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_failure.73786829
Short name	T321
Test name
Test status
Simulation time	925010859 ps
CPU time	22.8 seconds
Started	Aug 17 06:33:18 PM PDT 24
Finished	Aug 17 06:33:40 PM PDT 24
Peak memory	250820 kb
Host	smart-b779f28c-9da7-4831-875d-2b8d3d3cba0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=73786829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.73786829
Directory	/workspace/47.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/47.lc_ctrl_state_post_trans.2647085989
Short name	T411
Test name
Test status
Simulation time	377023049 ps
CPU time	9.83 seconds
Started	Aug 17 06:33:07 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	250828 kb
Host	smart-77d22ee7-673b-495b-a68b-396479bbf981
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2647085989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2647085989
Directory	/workspace/47.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/47.lc_ctrl_stress_all.1720132698
Short name	T659
Test name
Test status
Simulation time	7589749716 ps
CPU time	152.76 seconds
Started	Aug 17 06:33:21 PM PDT 24
Finished	Aug 17 06:35:54 PM PDT 24
Peak memory	274344 kb
Host	smart-57c0babd-6b2a-43e3-9f64-c94acf1700bf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720132698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all.1720132698
Directory	/workspace/47.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1381172578
Short name	T789
Test name
Test status
Simulation time	35889591 ps
CPU time	0.91 seconds
Started	Aug 17 06:33:31 PM PDT 24
Finished	Aug 17 06:33:32 PM PDT 24
Peak memory	211796 kb
Host	smart-f6c323ed-2015-433b-bd08-a196e280487f
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381172578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c trl_volatile_unlock_smoke.1381172578
Directory	/workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_alert_test.3605168639
Short name	T662
Test name
Test status
Simulation time	93253829 ps
CPU time	1.2 seconds
Started	Aug 17 06:33:20 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	208940 kb
Host	smart-56cf979f-5655-4776-bcec-ebd7dff78388
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605168639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3605168639
Directory	/workspace/48.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.lc_ctrl_errors.3464331219
Short name	T633
Test name
Test status
Simulation time	7950089985 ps
CPU time	22.85 seconds
Started	Aug 17 06:33:13 PM PDT 24
Finished	Aug 17 06:33:36 PM PDT 24
Peak memory	218288 kb
Host	smart-da748794-b3b9-4daa-9d2f-533d7e1d33e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3464331219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3464331219
Directory	/workspace/48.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/48.lc_ctrl_jtag_access.2794566700
Short name	T33
Test name
Test status
Simulation time	2810713287 ps
CPU time	6.73 seconds
Started	Aug 17 06:33:17 PM PDT 24
Finished	Aug 17 06:33:23 PM PDT 24
Peak memory	217564 kb
Host	smart-4dc8fdd7-e0e9-49fc-8e39-0b23707062c4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794566700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2794566700
Directory	/workspace/48.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/48.lc_ctrl_prog_failure.3042514565
Short name	T773
Test name
Test status
Simulation time	33762406 ps
CPU time	2.18 seconds
Started	Aug 17 06:33:19 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	218400 kb
Host	smart-3a5da888-bf18-44b2-9287-f1d2ba2d745e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3042514565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3042514565
Directory	/workspace/48.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_mubi.2321664999
Short name	T450
Test name
Test status
Simulation time	7132874622 ps
CPU time	16.79 seconds
Started	Aug 17 06:33:27 PM PDT 24
Finished	Aug 17 06:33:44 PM PDT 24
Peak memory	219984 kb
Host	smart-b27caf6b-a708-4970-b99d-bf178cbb0cd7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321664999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2321664999
Directory	/workspace/48.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_digest.2888650521
Short name	T369
Test name
Test status
Simulation time	9270342923 ps
CPU time	14.18 seconds
Started	Aug 17 06:33:22 PM PDT 24
Finished	Aug 17 06:33:36 PM PDT 24
Peak memory	226084 kb
Host	smart-6fac3489-7caa-4ed4-93b5-95f84da880a0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888650521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d igest.2888650521
Directory	/workspace/48.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/48.lc_ctrl_sec_token_mux.1630177838
Short name	T482
Test name
Test status
Simulation time	299380393 ps
CPU time	11.49 seconds
Started	Aug 17 06:33:19 PM PDT 24
Finished	Aug 17 06:33:30 PM PDT 24
Peak memory	218188 kb
Host	smart-097e9d11-cd06-4127-bf52-3e8eae672464
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630177838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux. 1630177838
Directory	/workspace/48.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/48.lc_ctrl_security_escalation.1344397773
Short name	T193
Test name
Test status
Simulation time	430619259 ps
CPU time	8.59 seconds
Started	Aug 17 06:33:44 PM PDT 24
Finished	Aug 17 06:33:53 PM PDT 24
Peak memory	224956 kb
Host	smart-fb82ce8e-09e5-4c74-8cd8-03076bf9e44a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1344397773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1344397773
Directory	/workspace/48.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/48.lc_ctrl_smoke.1336834854
Short name	T59
Test name
Test status
Simulation time	101912428 ps
CPU time	3.39 seconds
Started	Aug 17 06:33:18 PM PDT 24
Finished	Aug 17 06:33:22 PM PDT 24
Peak memory	217632 kb
Host	smart-fc6d8c10-2a1a-4162-8995-27a781ae462e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1336834854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1336834854
Directory	/workspace/48.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_failure.3065652916
Short name	T487
Test name
Test status
Simulation time	227402658 ps
CPU time	26.39 seconds
Started	Aug 17 06:33:18 PM PDT 24
Finished	Aug 17 06:33:44 PM PDT 24
Peak memory	250808 kb
Host	smart-c80e5c01-d7e1-4edb-94fd-0f3072e450cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3065652916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3065652916
Directory	/workspace/48.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/48.lc_ctrl_state_post_trans.3567018719
Short name	T144
Test name
Test status
Simulation time	89759161 ps
CPU time	6.47 seconds
Started	Aug 17 06:33:18 PM PDT 24
Finished	Aug 17 06:33:25 PM PDT 24
Peak memory	250916 kb
Host	smart-c760208c-2f96-49f8-a6cf-9a5489a1e520
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3567018719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3567018719
Directory	/workspace/48.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/48.lc_ctrl_stress_all.787953340
Short name	T554
Test name
Test status
Simulation time	10689975409 ps
CPU time	169.86 seconds
Started	Aug 17 06:33:18 PM PDT 24
Finished	Aug 17 06:36:08 PM PDT 24
Peak memory	269268 kb
Host	smart-803f04e1-75a5-4581-a073-1a23fb2e548f
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787953340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all.787953340
Directory	/workspace/48.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2770946839
Short name	T432
Test name
Test status
Simulation time	15719754 ps
CPU time	0.93 seconds
Started	Aug 17 06:33:17 PM PDT 24
Finished	Aug 17 06:33:18 PM PDT 24
Peak memory	211884 kb
Host	smart-d8636c1d-94e1-4b75-9392-3ef65e4eb441
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770946839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c trl_volatile_unlock_smoke.2770946839
Directory	/workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_alert_test.1748932283
Short name	T71
Test name
Test status
Simulation time	66672243 ps
CPU time	0.95 seconds
Started	Aug 17 06:33:19 PM PDT 24
Finished	Aug 17 06:33:20 PM PDT 24
Peak memory	208912 kb
Host	smart-56ebe820-cb52-42db-bdfb-9d30b6eb93fc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748932283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1748932283
Directory	/workspace/49.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.lc_ctrl_errors.642046785
Short name	T646
Test name
Test status
Simulation time	727991891 ps
CPU time	13.97 seconds
Started	Aug 17 06:33:33 PM PDT 24
Finished	Aug 17 06:33:48 PM PDT 24
Peak memory	218220 kb
Host	smart-ca82a32e-f881-4550-a648-b109df6dff8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=642046785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.642046785
Directory	/workspace/49.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/49.lc_ctrl_jtag_access.3013307553
Short name	T521
Test name
Test status
Simulation time	531336097 ps
CPU time	8.26 seconds
Started	Aug 17 06:33:25 PM PDT 24
Finished	Aug 17 06:33:33 PM PDT 24
Peak memory	217192 kb
Host	smart-95c6d272-4e8e-4e1c-b16d-f84c5e60c8ef
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013307553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3013307553
Directory	/workspace/49.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/49.lc_ctrl_prog_failure.1783337689
Short name	T562
Test name
Test status
Simulation time	114545476 ps
CPU time	2.85 seconds
Started	Aug 17 06:33:17 PM PDT 24
Finished	Aug 17 06:33:20 PM PDT 24
Peak memory	222612 kb
Host	smart-f6b54bed-31da-40f5-900e-9849a6f9bc2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783337689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1783337689
Directory	/workspace/49.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_mubi.2063505171
Short name	T478
Test name
Test status
Simulation time	925534238 ps
CPU time	14.35 seconds
Started	Aug 17 06:33:41 PM PDT 24
Finished	Aug 17 06:33:56 PM PDT 24
Peak memory	226068 kb
Host	smart-47948f5a-66c8-47a3-b686-bba5efdfeb6c
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063505171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2063505171
Directory	/workspace/49.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_digest.1458610703
Short name	T333
Test name
Test status
Simulation time	393868046 ps
CPU time	9.23 seconds
Started	Aug 17 06:33:16 PM PDT 24
Finished	Aug 17 06:33:26 PM PDT 24
Peak memory	225964 kb
Host	smart-0057f0c3-7d86-4fef-b31a-23e8682882ad
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458610703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d igest.1458610703
Directory	/workspace/49.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/49.lc_ctrl_sec_token_mux.794749647
Short name	T214
Test name
Test status
Simulation time	1672754559 ps
CPU time	6.68 seconds
Started	Aug 17 06:33:20 PM PDT 24
Finished	Aug 17 06:33:27 PM PDT 24
Peak memory	218228 kb
Host	smart-ae6c3541-fbe6-40bf-b6f8-2dbdd2795c71
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794749647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.794749647
Directory	/workspace/49.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/49.lc_ctrl_security_escalation.1604789361
Short name	T845
Test name
Test status
Simulation time	260129633 ps
CPU time	7.27 seconds
Started	Aug 17 06:33:23 PM PDT 24
Finished	Aug 17 06:33:30 PM PDT 24
Peak memory	226068 kb
Host	smart-551b15b5-320c-4def-ae21-a292fc83b0bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604789361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1604789361
Directory	/workspace/49.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/49.lc_ctrl_smoke.2338449297
Short name	T78
Test name
Test status
Simulation time	377325106 ps
CPU time	2.49 seconds
Started	Aug 17 06:33:19 PM PDT 24
Finished	Aug 17 06:33:21 PM PDT 24
Peak memory	214176 kb
Host	smart-4db53119-69b0-4c4c-b007-268592d4a89c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2338449297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2338449297
Directory	/workspace/49.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_failure.2173256424
Short name	T225
Test name
Test status
Simulation time	1016650275 ps
CPU time	28.09 seconds
Started	Aug 17 06:33:20 PM PDT 24
Finished	Aug 17 06:33:48 PM PDT 24
Peak memory	250884 kb
Host	smart-eefd2c39-0efb-4873-a92f-62dcffe3afde
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173256424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2173256424
Directory	/workspace/49.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/49.lc_ctrl_state_post_trans.4214596079
Short name	T607
Test name
Test status
Simulation time	115383129 ps
CPU time	8.41 seconds
Started	Aug 17 06:33:32 PM PDT 24
Finished	Aug 17 06:33:41 PM PDT 24
Peak memory	250916 kb
Host	smart-31a1b71a-f3af-4208-850d-5064229b4478
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4214596079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.4214596079
Directory	/workspace/49.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/49.lc_ctrl_stress_all.3151247168
Short name	T711
Test name
Test status
Simulation time	18122903728 ps
CPU time	111.38 seconds
Started	Aug 17 06:33:26 PM PDT 24
Finished	Aug 17 06:35:18 PM PDT 24
Peak memory	283740 kb
Host	smart-9062f1b0-2a38-4226-8cb7-2793d5b1a251
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151247168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all.3151247168
Directory	/workspace/49.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.744120503
Short name	T676
Test name
Test status
Simulation time	11121296140 ps
CPU time	103.04 seconds
Started	Aug 17 06:33:19 PM PDT 24
Finished	Aug 17 06:35:02 PM PDT 24
Peak memory	268896 kb
Host	smart-9b8b40e4-ea57-4527-b8bc-2394b3b91800
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=744120503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.744120503
Directory	/workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.968722401
Short name	T312
Test name
Test status
Simulation time	14323683 ps
CPU time	0.88 seconds
Started	Aug 17 06:33:36 PM PDT 24
Finished	Aug 17 06:33:38 PM PDT 24
Peak memory	211860 kb
Host	smart-1bf08c40-7912-4a7e-8b43-fd5bbc088f41
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968722401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct rl_volatile_unlock_smoke.968722401
Directory	/workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_alert_test.2911143850
Short name	T262
Test name
Test status
Simulation time	60786262 ps
CPU time	0.83 seconds
Started	Aug 17 06:32:14 PM PDT 24
Finished	Aug 17 06:32:15 PM PDT 24
Peak memory	208664 kb
Host	smart-f145345b-abb9-4504-bf23-0b672cf5d6ca
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911143850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2911143850
Directory	/workspace/5.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.lc_ctrl_errors.3022298588
Short name	T687
Test name
Test status
Simulation time	1848068387 ps
CPU time	15.24 seconds
Started	Aug 17 06:31:53 PM PDT 24
Finished	Aug 17 06:32:08 PM PDT 24
Peak memory	218216 kb
Host	smart-09a61a51-3414-41f8-adec-39d08ed72639
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022298588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3022298588
Directory	/workspace/5.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_access.3502736431
Short name	T652
Test name
Test status
Simulation time	1198810038 ps
CPU time	7.99 seconds
Started	Aug 17 06:31:52 PM PDT 24
Finished	Aug 17 06:32:00 PM PDT 24
Peak memory	217008 kb
Host	smart-481b6e7b-b0e9-4128-b635-ed2ebe36edf5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502736431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3502736431
Directory	/workspace/5.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_errors.2381701490
Short name	T604
Test name
Test status
Simulation time	15576620541 ps
CPU time	106.13 seconds
Started	Aug 17 06:32:09 PM PDT 24
Finished	Aug 17 06:33:55 PM PDT 24
Peak memory	218840 kb
Host	smart-ab9c7035-6cfe-418d-adfa-ef3a3b1e5d0f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381701490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er rors.2381701490
Directory	/workspace/5.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_priority.3564167299
Short name	T363
Test name
Test status
Simulation time	384116268 ps
CPU time	2.94 seconds
Started	Aug 17 06:32:06 PM PDT 24
Finished	Aug 17 06:32:09 PM PDT 24
Peak memory	217688 kb
Host	smart-86c81820-b3a4-4d2f-a878-4a8ac95aa5d9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564167299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3 564167299
Directory	/workspace/5.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1829213915
Short name	T527
Test name
Test status
Simulation time	4087254634 ps
CPU time	14.11 seconds
Started	Aug 17 06:32:07 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	225856 kb
Host	smart-87db8bd9-5bd5-4604-b8ce-f581f3d7a8a8
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829213915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag _prog_failure.1829213915
Directory	/workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2444664958
Short name	T634
Test name
Test status
Simulation time	6271842292 ps
CPU time	39.6 seconds
Started	Aug 17 06:32:01 PM PDT 24
Finished	Aug 17 06:32:41 PM PDT 24
Peak memory	217560 kb
Host	smart-23afdf5c-edcf-4771-83ce-3187c78afbea
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444664958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_regwen_during_op.2444664958
Directory	/workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_smoke.4006272902
Short name	T347
Test name
Test status
Simulation time	438587774 ps
CPU time	6.37 seconds
Started	Aug 17 06:31:47 PM PDT 24
Finished	Aug 17 06:31:53 PM PDT 24
Peak memory	217532 kb
Host	smart-f2650218-2d74-4ddd-a87f-019d3429abd1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006272902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke. 4006272902
Directory	/workspace/5.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2256826154
Short name	T469
Test name
Test status
Simulation time	8386619415 ps
CPU time	47.25 seconds
Started	Aug 17 06:31:44 PM PDT 24
Finished	Aug 17 06:32:31 PM PDT 24
Peak memory	279948 kb
Host	smart-f615f3f3-0e0b-4793-ad7d-66eeb8e95358
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256826154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta g_state_failure.2256826154
Directory	/workspace/5.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2821398033
Short name	T27
Test name
Test status
Simulation time	6019781991 ps
CPU time	14.21 seconds
Started	Aug 17 06:31:55 PM PDT 24
Finished	Aug 17 06:32:10 PM PDT 24
Peak memory	249404 kb
Host	smart-5d886f51-0e6c-4c56-905d-e40cedaa4fe3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821398033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_state_post_trans.2821398033
Directory	/workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_prog_failure.4221780889
Short name	T817
Test name
Test status
Simulation time	40734016 ps
CPU time	2.24 seconds
Started	Aug 17 06:31:58 PM PDT 24
Finished	Aug 17 06:32:00 PM PDT 24
Peak memory	218208 kb
Host	smart-4d2a3368-d9c9-48fa-9fcc-479f45570dbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4221780889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.4221780889
Directory	/workspace/5.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_regwen_during_op.2974417215
Short name	T758
Test name
Test status
Simulation time	268848409 ps
CPU time	15.12 seconds
Started	Aug 17 06:31:57 PM PDT 24
Finished	Aug 17 06:32:12 PM PDT 24
Peak memory	214060 kb
Host	smart-ff9fcc7c-38d9-448a-81c4-febbbc9e2b3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2974417215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2974417215
Directory	/workspace/5.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_mubi.4103743280
Short name	T420
Test name
Test status
Simulation time	718310879 ps
CPU time	12.52 seconds
Started	Aug 17 06:31:59 PM PDT 24
Finished	Aug 17 06:32:12 PM PDT 24
Peak memory	218908 kb
Host	smart-1ad02a8d-b1fb-49f5-8ea3-3dbb0305abda
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103743280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.4103743280
Directory	/workspace/5.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_digest.1283708473
Short name	T787
Test name
Test status
Simulation time	507200615 ps
CPU time	11.87 seconds
Started	Aug 17 06:32:01 PM PDT 24
Finished	Aug 17 06:32:13 PM PDT 24
Peak memory	226012 kb
Host	smart-9529587b-1f08-47e0-853a-ef87f4066ddb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283708473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di gest.1283708473
Directory	/workspace/5.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/5.lc_ctrl_sec_token_mux.742974974
Short name	T684
Test name
Test status
Simulation time	266461188 ps
CPU time	7.44 seconds
Started	Aug 17 06:32:01 PM PDT 24
Finished	Aug 17 06:32:08 PM PDT 24
Peak memory	218164 kb
Host	smart-17ce5a00-1019-4989-8120-b79d09f4f0be
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742974974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.742974974
Directory	/workspace/5.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/5.lc_ctrl_security_escalation.2460821452
Short name	T704
Test name
Test status
Simulation time	304522210 ps
CPU time	8.59 seconds
Started	Aug 17 06:32:07 PM PDT 24
Finished	Aug 17 06:32:16 PM PDT 24
Peak memory	224796 kb
Host	smart-a5a24bdd-b377-4fd3-9c3f-2aee3c4c1ab5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2460821452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2460821452
Directory	/workspace/5.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/5.lc_ctrl_smoke.1814148204
Short name	T359
Test name
Test status
Simulation time	32183538 ps
CPU time	1.01 seconds
Started	Aug 17 06:31:48 PM PDT 24
Finished	Aug 17 06:31:49 PM PDT 24
Peak memory	212128 kb
Host	smart-f520a6e6-0562-4782-9ef5-7a5a0d9a680f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814148204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1814148204
Directory	/workspace/5.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_failure.2042967026
Short name	T274
Test name
Test status
Simulation time	2199502781 ps
CPU time	31.13 seconds
Started	Aug 17 06:32:05 PM PDT 24
Finished	Aug 17 06:32:36 PM PDT 24
Peak memory	250984 kb
Host	smart-211aac66-e58f-41ad-99db-49c867824565
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2042967026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2042967026
Directory	/workspace/5.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/5.lc_ctrl_state_post_trans.406332721
Short name	T309
Test name
Test status
Simulation time	546591485 ps
CPU time	6.33 seconds
Started	Aug 17 06:32:10 PM PDT 24
Finished	Aug 17 06:32:17 PM PDT 24
Peak memory	250924 kb
Host	smart-482a889d-d676-4a46-b603-ff9f1c5f29f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406332721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.406332721
Directory	/workspace/5.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/5.lc_ctrl_stress_all.3156145129
Short name	T563
Test name
Test status
Simulation time	9157207329 ps
CPU time	87.48 seconds
Started	Aug 17 06:32:03 PM PDT 24
Finished	Aug 17 06:33:31 PM PDT 24
Peak memory	275676 kb
Host	smart-e2bbca92-9e73-4f3c-92ea-cb723c6bd159
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156145129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all.3156145129
Directory	/workspace/5.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3266867626
Short name	T627
Test name
Test status
Simulation time	10882701717 ps
CPU time	50.2 seconds
Started	Aug 17 06:32:04 PM PDT 24
Finished	Aug 17 06:32:55 PM PDT 24
Peak memory	251100 kb
Host	smart-d8688a8a-02f8-46d6-969d-a6876f579fe9
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3266867626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.3266867626
Directory	/workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2657628631
Short name	T371
Test name
Test status
Simulation time	14593715 ps
CPU time	1.02 seconds
Started	Aug 17 06:31:55 PM PDT 24
Finished	Aug 17 06:31:56 PM PDT 24
Peak memory	211780 kb
Host	smart-53990ed2-e109-409e-bc3b-705986282363
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657628631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct rl_volatile_unlock_smoke.2657628631
Directory	/workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_alert_test.1800303205
Short name	T162
Test name
Test status
Simulation time	66537973 ps
CPU time	0.9 seconds
Started	Aug 17 06:31:55 PM PDT 24
Finished	Aug 17 06:31:56 PM PDT 24
Peak memory	208884 kb
Host	smart-f89c1460-c895-4726-a678-5025aa7d3d6b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800303205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1800303205
Directory	/workspace/6.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.lc_ctrl_claim_transition_if.648407024
Short name	T836
Test name
Test status
Simulation time	63449238 ps
CPU time	0.84 seconds
Started	Aug 17 06:31:57 PM PDT 24
Finished	Aug 17 06:31:58 PM PDT 24
Peak memory	208528 kb
Host	smart-27059984-3a6c-4870-bcec-0116d7e267cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648407024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.648407024
Directory	/workspace/6.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/6.lc_ctrl_errors.3951783591
Short name	T477
Test name
Test status
Simulation time	467336812 ps
CPU time	10.45 seconds
Started	Aug 17 06:32:09 PM PDT 24
Finished	Aug 17 06:32:20 PM PDT 24
Peak memory	218240 kb
Host	smart-1eceac0e-f98a-4ae7-b3ca-1510d3de712e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951783591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3951783591
Directory	/workspace/6.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_access.1661161996
Short name	T8
Test name
Test status
Simulation time	499995567 ps
CPU time	1.57 seconds
Started	Aug 17 06:32:03 PM PDT 24
Finished	Aug 17 06:32:04 PM PDT 24
Peak memory	216916 kb
Host	smart-40afa6a4-08a6-491e-a6a1-16f66c53ce8d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661161996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1661161996
Directory	/workspace/6.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_errors.4002641099
Short name	T650
Test name
Test status
Simulation time	3268774080 ps
CPU time	29.17 seconds
Started	Aug 17 06:31:55 PM PDT 24
Finished	Aug 17 06:32:25 PM PDT 24
Peak memory	218960 kb
Host	smart-58e13897-59dd-460d-90cd-b5f30c180693
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002641099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er rors.4002641099
Directory	/workspace/6.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_priority.2230115079
Short name	T573
Test name
Test status
Simulation time	635305578 ps
CPU time	4.52 seconds
Started	Aug 17 06:31:59 PM PDT 24
Finished	Aug 17 06:32:03 PM PDT 24
Peak memory	217600 kb
Host	smart-2b17b30a-0d76-4ffe-b6bd-82f130245ce0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230115079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2 230115079
Directory	/workspace/6.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2126714823
Short name	T831
Test name
Test status
Simulation time	277403773 ps
CPU time	5.07 seconds
Started	Aug 17 06:31:57 PM PDT 24
Finished	Aug 17 06:32:03 PM PDT 24
Peak memory	218220 kb
Host	smart-973fcd4f-7b43-4908-8efe-1b7105996594
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126714823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag _prog_failure.2126714823
Directory	/workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.613548514
Short name	T80
Test name
Test status
Simulation time	1007620528 ps
CPU time	27.71 seconds
Started	Aug 17 06:32:14 PM PDT 24
Finished	Aug 17 06:32:41 PM PDT 24
Peak memory	217568 kb
Host	smart-1ba918d8-7c49-468f-ad2f-8e19a7e7b541
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613548514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j tag_regwen_during_op.613548514
Directory	/workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_smoke.3781904000
Short name	T503
Test name
Test status
Simulation time	2067132087 ps
CPU time	6.36 seconds
Started	Aug 17 06:32:06 PM PDT 24
Finished	Aug 17 06:32:12 PM PDT 24
Peak memory	217728 kb
Host	smart-1de2b1ef-8268-4372-9b81-33270895e4b0
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781904000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke. 3781904000
Directory	/workspace/6.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1726353351
Short name	T431
Test name
Test status
Simulation time	1862828428 ps
CPU time	37.45 seconds
Started	Aug 17 06:32:11 PM PDT 24
Finished	Aug 17 06:32:49 PM PDT 24
Peak memory	250844 kb
Host	smart-4ce14869-ba61-41e0-aa7e-947cd903e7d9
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726353351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta g_state_failure.1726353351
Directory	/workspace/6.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3381653893
Short name	T853
Test name
Test status
Simulation time	409408166 ps
CPU time	13.31 seconds
Started	Aug 17 06:32:06 PM PDT 24
Finished	Aug 17 06:32:20 PM PDT 24
Peak memory	250844 kb
Host	smart-5d9f4887-4754-4422-afa0-08d206548409
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381653893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_ jtag_state_post_trans.3381653893
Directory	/workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_prog_failure.1391321533
Short name	T291
Test name
Test status
Simulation time	100065233 ps
CPU time	4.45 seconds
Started	Aug 17 06:32:14 PM PDT 24
Finished	Aug 17 06:32:19 PM PDT 24
Peak memory	222892 kb
Host	smart-fdd4d11e-b5e9-4cb3-8bea-e91eaf087bf6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1391321533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1391321533
Directory	/workspace/6.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_regwen_during_op.1197595402
Short name	T396
Test name
Test status
Simulation time	794740564 ps
CPU time	13.94 seconds
Started	Aug 17 06:32:09 PM PDT 24
Finished	Aug 17 06:32:23 PM PDT 24
Peak memory	217644 kb
Host	smart-117f7cf5-322f-431a-bbf4-d4e4e561ee29
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1197595402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1197595402
Directory	/workspace/6.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/6.lc_ctrl_sec_token_digest.3001473273
Short name	T444
Test name
Test status
Simulation time	5441881432 ps
CPU time	26.96 seconds
Started	Aug 17 06:32:09 PM PDT 24
Finished	Aug 17 06:32:36 PM PDT 24
Peak memory	226068 kb
Host	smart-10fc8f1a-934b-46af-8740-d296f5b46467
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001473273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di gest.3001473273
Directory	/workspace/6.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/6.lc_ctrl_security_escalation.3618351413
Short name	T798
Test name
Test status
Simulation time	280976950 ps
CPU time	6.6 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	224516 kb
Host	smart-8ce39f65-3888-4d38-91e5-3f044aa3a6e7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3618351413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3618351413
Directory	/workspace/6.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/6.lc_ctrl_smoke.972401875
Short name	T153
Test name
Test status
Simulation time	282553393 ps
CPU time	1.38 seconds
Started	Aug 17 06:31:59 PM PDT 24
Finished	Aug 17 06:32:00 PM PDT 24
Peak memory	213644 kb
Host	smart-a14bd3b0-c1b9-4acc-a9aa-8451a3d7170e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=972401875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.972401875
Directory	/workspace/6.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_failure.1018319270
Short name	T695
Test name
Test status
Simulation time	563059681 ps
CPU time	22.27 seconds
Started	Aug 17 06:31:59 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	251080 kb
Host	smart-a334f2e8-0b5d-42de-8ef1-95ee63e1d470
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1018319270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1018319270
Directory	/workspace/6.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/6.lc_ctrl_state_post_trans.274748196
Short name	T233
Test name
Test status
Simulation time	372475766 ps
CPU time	8 seconds
Started	Aug 17 06:31:48 PM PDT 24
Finished	Aug 17 06:31:56 PM PDT 24
Peak memory	250896 kb
Host	smart-6a1b53ab-dfae-439d-956f-ad290dedc45a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=274748196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.274748196
Directory	/workspace/6.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/6.lc_ctrl_stress_all.393791028
Short name	T47
Test name
Test status
Simulation time	15074775241 ps
CPU time	225.69 seconds
Started	Aug 17 06:32:00 PM PDT 24
Finished	Aug 17 06:35:46 PM PDT 24
Peak memory	226144 kb
Host	smart-06288cf8-f841-4086-abd4-a0800baab2d7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393791028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all.393791028
Directory	/workspace/6.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.4124641338
Short name	T130
Test name
Test status
Simulation time	12640355599 ps
CPU time	70.47 seconds
Started	Aug 17 06:32:06 PM PDT 24
Finished	Aug 17 06:33:17 PM PDT 24
Peak memory	262760 kb
Host	smart-616c0949-1641-47c0-bfed-75267aee1282
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4124641338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.4124641338
Directory	/workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.914803989
Short name	T701
Test name
Test status
Simulation time	42651510 ps
CPU time	0.98 seconds
Started	Aug 17 06:31:56 PM PDT 24
Finished	Aug 17 06:31:57 PM PDT 24
Peak memory	211912 kb
Host	smart-3f1a83db-7075-4ea1-b1cd-507dfea0334c
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914803989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr l_volatile_unlock_smoke.914803989
Directory	/workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_alert_test.2192652273
Short name	T753
Test name
Test status
Simulation time	140939243 ps
CPU time	1.14 seconds
Started	Aug 17 06:32:07 PM PDT 24
Finished	Aug 17 06:32:08 PM PDT 24
Peak memory	208976 kb
Host	smart-7820a79f-ae22-4fc7-89d9-30673e48925b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192652273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2192652273
Directory	/workspace/7.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.lc_ctrl_claim_transition_if.2860757469
Short name	T190
Test name
Test status
Simulation time	12007889 ps
CPU time	0.97 seconds
Started	Aug 17 06:32:20 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	208684 kb
Host	smart-2b01c989-7837-4f13-8027-3f78aa73245b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2860757469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2860757469
Directory	/workspace/7.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/7.lc_ctrl_errors.1814216043
Short name	T264
Test name
Test status
Simulation time	1972875882 ps
CPU time	13.55 seconds
Started	Aug 17 06:32:00 PM PDT 24
Finished	Aug 17 06:32:14 PM PDT 24
Peak memory	218232 kb
Host	smart-1737f765-bd30-4a04-a025-d589b833aecb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814216043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1814216043
Directory	/workspace/7.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_access.4201433223
Short name	T344
Test name
Test status
Simulation time	1463295795 ps
CPU time	1.93 seconds
Started	Aug 17 06:32:10 PM PDT 24
Finished	Aug 17 06:32:12 PM PDT 24
Peak memory	216952 kb
Host	smart-af7d9515-7751-4b55-8d86-6d6f7803ffcb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201433223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.4201433223
Directory	/workspace/7.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_errors.2852224806
Short name	T327
Test name
Test status
Simulation time	1784743257 ps
CPU time	17.64 seconds
Started	Aug 17 06:32:14 PM PDT 24
Finished	Aug 17 06:32:31 PM PDT 24
Peak memory	218228 kb
Host	smart-b06d723b-017e-4a3c-b703-e1384763287f
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852224806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er rors.2852224806
Directory	/workspace/7.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_priority.3735872432
Short name	T459
Test name
Test status
Simulation time	252950137 ps
CPU time	3.48 seconds
Started	Aug 17 06:31:57 PM PDT 24
Finished	Aug 17 06:32:00 PM PDT 24
Peak memory	217340 kb
Host	smart-b32cb96b-e636-404e-8638-4f9be3f0f2cb
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735872432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3 735872432
Directory	/workspace/7.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.702948069
Short name	T287
Test name
Test status
Simulation time	1683553178 ps
CPU time	11.94 seconds
Started	Aug 17 06:32:15 PM PDT 24
Finished	Aug 17 06:32:27 PM PDT 24
Peak memory	223044 kb
Host	smart-cfa4a034-2e33-4e0f-8d55-3f86ec5e9d18
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702948069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_ prog_failure.702948069
Directory	/workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.846478748
Short name	T851
Test name
Test status
Simulation time	1345397991 ps
CPU time	34.69 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:32:53 PM PDT 24
Peak memory	217556 kb
Host	smart-e1897ba6-32b4-4fcf-92eb-16e98c9d9e2a
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846478748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j tag_regwen_during_op.846478748
Directory	/workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_smoke.2837737670
Short name	T537
Test name
Test status
Simulation time	2291480727 ps
CPU time	15.12 seconds
Started	Aug 17 06:32:11 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	217648 kb
Host	smart-6b2d7bbf-cd1b-4800-af67-e0dce52b3c33
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837737670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke. 2837737670
Directory	/workspace/7.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_failure.817451514
Short name	T205
Test name
Test status
Simulation time	7620111579 ps
CPU time	65.91 seconds
Started	Aug 17 06:32:04 PM PDT 24
Finished	Aug 17 06:33:10 PM PDT 24
Peak memory	267224 kb
Host	smart-20308a53-4742-4d16-aba0-b5a618bd344d
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817451514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag _state_failure.817451514
Directory	/workspace/7.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.56110933
Short name	T790
Test name
Test status
Simulation time	1769540073 ps
CPU time	30.63 seconds
Started	Aug 17 06:32:04 PM PDT 24
Finished	Aug 17 06:32:34 PM PDT 24
Peak memory	250720 kb
Host	smart-a76413bb-8ec7-4885-8612-a3eea09f9ce1
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56110933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jt ag_state_post_trans.56110933
Directory	/workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_prog_failure.1553166651
Short name	T425
Test name
Test status
Simulation time	180163852 ps
CPU time	4.35 seconds
Started	Aug 17 06:32:12 PM PDT 24
Finished	Aug 17 06:32:16 PM PDT 24
Peak memory	222436 kb
Host	smart-183b5517-14df-4b3a-b741-2acca70499e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553166651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1553166651
Directory	/workspace/7.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_regwen_during_op.3727957747
Short name	T152
Test name
Test status
Simulation time	1315674372 ps
CPU time	7.51 seconds
Started	Aug 17 06:32:16 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	217628 kb
Host	smart-a6c7eee8-d627-4abc-becf-c2bfef7c0045
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3727957747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3727957747
Directory	/workspace/7.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_mubi.579607566
Short name	T421
Test name
Test status
Simulation time	259016451 ps
CPU time	11.52 seconds
Started	Aug 17 06:32:08 PM PDT 24
Finished	Aug 17 06:32:20 PM PDT 24
Peak memory	226020 kb
Host	smart-15c8cacb-a663-4790-8980-78d091ae85e0
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579607566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.579607566
Directory	/workspace/7.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_digest.2942546853
Short name	T749
Test name
Test status
Simulation time	556351147 ps
CPU time	13.94 seconds
Started	Aug 17 06:32:01 PM PDT 24
Finished	Aug 17 06:32:15 PM PDT 24
Peak memory	226012 kb
Host	smart-6a7ceb73-a2fd-4588-a405-287449ead49e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942546853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di gest.2942546853
Directory	/workspace/7.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/7.lc_ctrl_sec_token_mux.62582915
Short name	T738
Test name
Test status
Simulation time	1294691903 ps
CPU time	13.93 seconds
Started	Aug 17 06:32:00 PM PDT 24
Finished	Aug 17 06:32:14 PM PDT 24
Peak memory	226008 kb
Host	smart-b8b988c5-d422-4474-8353-67b2209cf5a7
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62582915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.62582915
Directory	/workspace/7.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/7.lc_ctrl_security_escalation.500506051
Short name	T57
Test name
Test status
Simulation time	209200670 ps
CPU time	6.53 seconds
Started	Aug 17 06:32:05 PM PDT 24
Finished	Aug 17 06:32:12 PM PDT 24
Peak memory	224648 kb
Host	smart-787e9600-b695-4bf1-8157-2dd3a710e5eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500506051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.500506051
Directory	/workspace/7.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/7.lc_ctrl_smoke.2129076594
Short name	T41
Test name
Test status
Simulation time	42992275 ps
CPU time	3.2 seconds
Started	Aug 17 06:32:04 PM PDT 24
Finished	Aug 17 06:32:07 PM PDT 24
Peak memory	224264 kb
Host	smart-ae07f408-a79c-4425-8e57-b27eea6e2e58
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2129076594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2129076594
Directory	/workspace/7.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_failure.2950189926
Short name	T688
Test name
Test status
Simulation time	1979886652 ps
CPU time	27.02 seconds
Started	Aug 17 06:32:12 PM PDT 24
Finished	Aug 17 06:32:39 PM PDT 24
Peak memory	250900 kb
Host	smart-7df0eb1e-dda5-43dc-bbf6-df61305a53b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950189926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2950189926
Directory	/workspace/7.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/7.lc_ctrl_state_post_trans.2038499915
Short name	T654
Test name
Test status
Simulation time	174466113 ps
CPU time	3.02 seconds
Started	Aug 17 06:32:00 PM PDT 24
Finished	Aug 17 06:32:03 PM PDT 24
Peak memory	223924 kb
Host	smart-a8a1cf27-5aad-44b1-a636-8b63a24aff03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2038499915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2038499915
Directory	/workspace/7.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/7.lc_ctrl_stress_all.3120402399
Short name	T148
Test name
Test status
Simulation time	19432920815 ps
CPU time	346.79 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:38:05 PM PDT 24
Peak memory	221580 kb
Host	smart-c2ed21f2-36f2-4d78-b5de-acac74ca7fba
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120402399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM _TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all.3120402399
Directory	/workspace/7.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3806655595
Short name	T150
Test name
Test status
Simulation time	13756140 ps
CPU time	1.06 seconds
Started	Aug 17 06:31:55 PM PDT 24
Finished	Aug 17 06:31:56 PM PDT 24
Peak memory	211852 kb
Host	smart-dfdcd9f4-106e-4fa0-8466-4f008438360b
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806655595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct rl_volatile_unlock_smoke.3806655595
Directory	/workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_alert_test.2767866853
Short name	T85
Test name
Test status
Simulation time	15844587 ps
CPU time	1.06 seconds
Started	Aug 17 06:32:10 PM PDT 24
Finished	Aug 17 06:32:11 PM PDT 24
Peak memory	209056 kb
Host	smart-d4f2eded-fcc5-42e9-9227-1c52973b9900
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767866853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2767866853
Directory	/workspace/8.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.lc_ctrl_errors.2542355034
Short name	T792
Test name
Test status
Simulation time	914344396 ps
CPU time	9.48 seconds
Started	Aug 17 06:32:01 PM PDT 24
Finished	Aug 17 06:32:11 PM PDT 24
Peak memory	218268 kb
Host	smart-a6b034bf-27f0-4a7b-b18f-496e773f3b83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542355034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2542355034
Directory	/workspace/8.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_access.3738721145
Short name	T34
Test name
Test status
Simulation time	795535974 ps
CPU time	9.68 seconds
Started	Aug 17 06:31:56 PM PDT 24
Finished	Aug 17 06:32:06 PM PDT 24
Peak memory	217152 kb
Host	smart-51cbedd5-ece3-4299-97b3-593330e1d1cd
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738721145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3738721145
Directory	/workspace/8.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_errors.3058783847
Short name	T403
Test name
Test status
Simulation time	20324103049 ps
CPU time	133.54 seconds
Started	Aug 17 06:32:04 PM PDT 24
Finished	Aug 17 06:34:17 PM PDT 24
Peak memory	219884 kb
Host	smart-30b0fa0e-5e47-4372-baf6-e6402b1542dd
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058783847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er rors.3058783847
Directory	/workspace/8.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_priority.2123451189
Short name	T436
Test name
Test status
Simulation time	149555499 ps
CPU time	2.66 seconds
Started	Aug 17 06:31:52 PM PDT 24
Finished	Aug 17 06:31:54 PM PDT 24
Peak memory	217696 kb
Host	smart-b019cb9a-7128-47ad-8492-36e544599257
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123451189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2 123451189
Directory	/workspace/8.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.577645947
Short name	T472
Test name
Test status
Simulation time	2514683946 ps
CPU time	13.83 seconds
Started	Aug 17 06:32:11 PM PDT 24
Finished	Aug 17 06:32:25 PM PDT 24
Peak memory	224764 kb
Host	smart-2a497170-eb3e-4f2a-a7a9-cabfa2e2ba67
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577645947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_ prog_failure.577645947
Directory	/workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1171573049
Short name	T270
Test name
Test status
Simulation time	4047791764 ps
CPU time	26.89 seconds
Started	Aug 17 06:31:59 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	217608 kb
Host	smart-6a4b9d6c-2395-4ab8-a6bc-141fe8b69664
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171573049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_regwen_during_op.1171573049
Directory	/workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_smoke.2294832627
Short name	T591
Test name
Test status
Simulation time	123673175 ps
CPU time	1.54 seconds
Started	Aug 17 06:32:02 PM PDT 24
Finished	Aug 17 06:32:04 PM PDT 24
Peak memory	217540 kb
Host	smart-89a63801-512a-4d5b-8f79-e124935a3ade
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294832627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke. 2294832627
Directory	/workspace/8.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3271741703
Short name	T435
Test name
Test status
Simulation time	5430056815 ps
CPU time	42.7 seconds
Started	Aug 17 06:32:13 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	267272 kb
Host	smart-411f25a3-2b8d-442c-afc7-3a4fb770f742
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271741703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta g_state_failure.3271741703
Directory	/workspace/8.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.545323819
Short name	T447
Test name
Test status
Simulation time	537900214 ps
CPU time	20.34 seconds
Started	Aug 17 06:32:07 PM PDT 24
Finished	Aug 17 06:32:27 PM PDT 24
Peak memory	250696 kb
Host	smart-fc8e49fb-3b27-4bff-ba98-56fabb11ced4
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545323819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j tag_state_post_trans.545323819
Directory	/workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_prog_failure.1880208639
Short name	T300
Test name
Test status
Simulation time	105051575 ps
CPU time	2.22 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:32:20 PM PDT 24
Peak memory	222340 kb
Host	smart-413664bc-4ae3-445d-aa0c-7ac572d48b4b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880208639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1880208639
Directory	/workspace/8.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_regwen_during_op.2383297794
Short name	T797
Test name
Test status
Simulation time	689578933 ps
CPU time	8.69 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:32:26 PM PDT 24
Peak memory	214696 kb
Host	smart-283b08a8-4b0b-4df5-b261-57b4f6219719
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2383297794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2383297794
Directory	/workspace/8.lc_ctrl_regwen_during_op/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_mubi.3924392649
Short name	T693
Test name
Test status
Simulation time	1084170490 ps
CPU time	13.38 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:32 PM PDT 24
Peak memory	219096 kb
Host	smart-18be0f67-0ec1-4949-b0ee-01ffcfdb0202
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924392649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3924392649
Directory	/workspace/8.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_digest.1149723723
Short name	T102
Test name
Test status
Simulation time	282263619 ps
CPU time	10.91 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:32:28 PM PDT 24
Peak memory	225928 kb
Host	smart-9596dfca-dce7-403d-bb8e-3e41297e7a07
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149723723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di gest.1149723723
Directory	/workspace/8.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/8.lc_ctrl_sec_token_mux.1949819831
Short name	T311
Test name
Test status
Simulation time	5128115144 ps
CPU time	8.91 seconds
Started	Aug 17 06:32:09 PM PDT 24
Finished	Aug 17 06:32:18 PM PDT 24
Peak memory	218292 kb
Host	smart-02a1cb9c-35fd-4fb9-a104-d902db0f85d8
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949819831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1 949819831
Directory	/workspace/8.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/8.lc_ctrl_security_escalation.67285778
Short name	T53
Test name
Test status
Simulation time	400215859 ps
CPU time	8.39 seconds
Started	Aug 17 06:32:03 PM PDT 24
Finished	Aug 17 06:32:12 PM PDT 24
Peak memory	224764 kb
Host	smart-89ffcc8c-8fcd-4f74-9190-d89ecd989eb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67285778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.67285778
Directory	/workspace/8.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/8.lc_ctrl_smoke.408061213
Short name	T253
Test name
Test status
Simulation time	66832740 ps
CPU time	1.52 seconds
Started	Aug 17 06:32:09 PM PDT 24
Finished	Aug 17 06:32:11 PM PDT 24
Peak memory	213700 kb
Host	smart-969b65e0-9163-4303-9366-8ef228c62e80
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408061213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.408061213
Directory	/workspace/8.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_failure.2573959746
Short name	T719
Test name
Test status
Simulation time	1127582072 ps
CPU time	25.35 seconds
Started	Aug 17 06:32:16 PM PDT 24
Finished	Aug 17 06:32:42 PM PDT 24
Peak memory	250904 kb
Host	smart-1e7861e0-9485-47d8-827e-c6d701c57476
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573959746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2573959746
Directory	/workspace/8.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/8.lc_ctrl_state_post_trans.454137131
Short name	T355
Test name
Test status
Simulation time	795043913 ps
CPU time	7.17 seconds
Started	Aug 17 06:31:59 PM PDT 24
Finished	Aug 17 06:32:06 PM PDT 24
Peak memory	246676 kb
Host	smart-b805c49e-107e-4351-8f7d-7d95bbce2b63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=454137131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.454137131
Directory	/workspace/8.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/8.lc_ctrl_stress_all.461061458
Short name	T147
Test name
Test status
Simulation time	8880198289 ps
CPU time	81.94 seconds
Started	Aug 17 06:32:10 PM PDT 24
Finished	Aug 17 06:33:32 PM PDT 24
Peak memory	239892 kb
Host	smart-aee58f93-807c-4e71-8149-671fca4747d1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461061458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_ TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all.461061458
Directory	/workspace/8.lc_ctrl_stress_all/latest

Test location	/workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2473057388
Short name	T395
Test name
Test status
Simulation time	49622449 ps
CPU time	0.98 seconds
Started	Aug 17 06:32:12 PM PDT 24
Finished	Aug 17 06:32:13 PM PDT 24
Peak memory	217684 kb
Host	smart-a0935b0f-7752-48e3-a2f8-c6b6c3aefda0
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473057388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct rl_volatile_unlock_smoke.2473057388
Directory	/workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_alert_test.4025172192
Short name	T42
Test name
Test status
Simulation time	22996607 ps
CPU time	0.9 seconds
Started	Aug 17 06:32:03 PM PDT 24
Finished	Aug 17 06:32:04 PM PDT 24
Peak memory	208856 kb
Host	smart-52d68a4e-2636-4910-88c9-230b5ca0f32b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025172192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.4025172192
Directory	/workspace/9.lc_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.lc_ctrl_claim_transition_if.707282059
Short name	T186
Test name
Test status
Simulation time	22352076 ps
CPU time	0.78 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:20 PM PDT 24
Peak memory	208544 kb
Host	smart-9b533812-1142-4b14-919b-52965757f700
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707282059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.707282059
Directory	/workspace/9.lc_ctrl_claim_transition_if/latest

Test location	/workspace/coverage/default/9.lc_ctrl_errors.1119170123
Short name	T159
Test name
Test status
Simulation time	225333398 ps
CPU time	11.51 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:31 PM PDT 24
Peak memory	218280 kb
Host	smart-c6d2e337-28c9-476a-b31d-33dd01bd4ed5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1119170123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1119170123
Directory	/workspace/9.lc_ctrl_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_access.2795393368
Short name	T165
Test name
Test status
Simulation time	787875424 ps
CPU time	10.65 seconds
Started	Aug 17 06:32:45 PM PDT 24
Finished	Aug 17 06:32:56 PM PDT 24
Peak memory	217376 kb
Host	smart-f43d1798-fb6b-4e56-abdb-eb16e8553346
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795393368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2795393368
Directory	/workspace/9.lc_ctrl_jtag_access/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_errors.4268359764
Short name	T606
Test name
Test status
Simulation time	19085748729 ps
CPU time	60.16 seconds
Started	Aug 17 06:32:13 PM PDT 24
Finished	Aug 17 06:33:13 PM PDT 24
Peak memory	219804 kb
Host	smart-ed5aecfe-05fb-4fe7-bd42-0fdb98be1f16
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268359764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er rors.4268359764
Directory	/workspace/9.lc_ctrl_jtag_errors/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_priority.2524771379
Short name	T9
Test name
Test status
Simulation time	1229703385 ps
CPU time	9.69 seconds
Started	Aug 17 06:32:15 PM PDT 24
Finished	Aug 17 06:32:25 PM PDT 24
Peak memory	217708 kb
Host	smart-45ec4eaa-1500-4903-af59-0dbc28004c5e
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524771379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2 524771379
Directory	/workspace/9.lc_ctrl_jtag_priority/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2687720385
Short name	T499
Test name
Test status
Simulation time	1225655294 ps
CPU time	11.63 seconds
Started	Aug 17 06:32:12 PM PDT 24
Finished	Aug 17 06:32:24 PM PDT 24
Peak memory	218228 kb
Host	smart-cd868c70-5ba2-4468-ac5f-da3482e91db3
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687720385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag _prog_failure.2687720385
Directory	/workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2996180220
Short name	T626
Test name
Test status
Simulation time	1143018198 ps
CPU time	21.21 seconds
Started	Aug 17 06:32:06 PM PDT 24
Finished	Aug 17 06:32:27 PM PDT 24
Peak memory	217592 kb
Host	smart-80f0650b-9e57-4b8e-8f61-711fa57e0fcf
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996180220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_ jtag_regwen_during_op.2996180220
Directory	/workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_smoke.2701633013
Short name	T326
Test name
Test status
Simulation time	297192111 ps
CPU time	2.35 seconds
Started	Aug 17 06:32:11 PM PDT 24
Finished	Aug 17 06:32:13 PM PDT 24
Peak memory	217568 kb
Host	smart-6668297a-eeb7-4fb0-a9ed-567d53eb87ab
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701633013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke. 2701633013
Directory	/workspace/9.lc_ctrl_jtag_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3180127964
Short name	T576
Test name
Test status
Simulation time	8544277504 ps
CPU time	49.45 seconds
Started	Aug 17 06:32:18 PM PDT 24
Finished	Aug 17 06:33:08 PM PDT 24
Peak memory	267320 kb
Host	smart-87c7d7a4-1300-41ca-a05d-7ce2467b1752
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180127964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl _state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta g_state_failure.3180127964
Directory	/workspace/9.lc_ctrl_jtag_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.795351163
Short name	T237
Test name
Test status
Simulation time	1407325693 ps
CPU time	15.46 seconds
Started	Aug 17 06:32:17 PM PDT 24
Finished	Aug 17 06:32:32 PM PDT 24
Peak memory	226352 kb
Host	smart-2fc84ddf-2d47-4456-b42c-61a948f525fd
User	root
Command	/workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795351163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_ state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j tag_state_post_trans.795351163
Directory	/workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_prog_failure.161997901
Short name	T301
Test name
Test status
Simulation time	64002051 ps
CPU time	1.53 seconds
Started	Aug 17 06:32:15 PM PDT 24
Finished	Aug 17 06:32:17 PM PDT 24
Peak memory	218240 kb
Host	smart-66e5015b-a67f-4d15-8e54-c420329f3736
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161997901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.161997901
Directory	/workspace/9.lc_ctrl_prog_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_mubi.351306456
Short name	T362
Test name
Test status
Simulation time	230736349 ps
CPU time	9.61 seconds
Started	Aug 17 06:32:21 PM PDT 24
Finished	Aug 17 06:32:31 PM PDT 24
Peak memory	218212 kb
Host	smart-cede6fda-c728-4106-ac8d-772808e4a4a1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351306456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.351306456
Directory	/workspace/9.lc_ctrl_sec_mubi/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_digest.2280550457
Short name	T714
Test name
Test status
Simulation time	2863039807 ps
CPU time	8.31 seconds
Started	Aug 17 06:32:12 PM PDT 24
Finished	Aug 17 06:32:21 PM PDT 24
Peak memory	226016 kb
Host	smart-0dbe8ce5-b345-43b1-9826-cdbef9813081
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280550457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di gest.2280550457
Directory	/workspace/9.lc_ctrl_sec_token_digest/latest

Test location	/workspace/coverage/default/9.lc_ctrl_sec_token_mux.3558918913
Short name	T388
Test name
Test status
Simulation time	264215979 ps
CPU time	10.15 seconds
Started	Aug 17 06:32:08 PM PDT 24
Finished	Aug 17 06:32:18 PM PDT 24
Peak memory	226008 kb
Host	smart-80be4a94-2675-4acd-87b0-45a57fa21337
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558918913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3 558918913
Directory	/workspace/9.lc_ctrl_sec_token_mux/latest

Test location	/workspace/coverage/default/9.lc_ctrl_security_escalation.2921540846
Short name	T513
Test name
Test status
Simulation time	968244374 ps
CPU time	9.58 seconds
Started	Aug 17 06:32:19 PM PDT 24
Finished	Aug 17 06:32:29 PM PDT 24
Peak memory	226068 kb
Host	smart-5c75046c-d8aa-429f-a76e-84d534875970
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921540846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2921540846
Directory	/workspace/9.lc_ctrl_security_escalation/latest

Test location	/workspace/coverage/default/9.lc_ctrl_smoke.3686186429
Short name	T520
Test name
Test status
Simulation time	62505628 ps
CPU time	1.07 seconds
Started	Aug 17 06:32:03 PM PDT 24
Finished	Aug 17 06:32:04 PM PDT 24
Peak memory	213708 kb
Host	smart-69ebc4b4-a705-4ffe-a321-86b6fbc795b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686186429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3686186429
Directory	/workspace/9.lc_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_failure.573367490
Short name	T244
Test name
Test status
Simulation time	247616294 ps
CPU time	23.88 seconds
Started	Aug 17 06:32:13 PM PDT 24
Finished	Aug 17 06:32:37 PM PDT 24
Peak memory	245376 kb
Host	smart-b56f565a-db61-4c13-ad2e-96b1d078c1e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=573367490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.573367490
Directory	/workspace/9.lc_ctrl_state_failure/latest

Test location	/workspace/coverage/default/9.lc_ctrl_state_post_trans.106472367
Short name	T361
Test name
Test status
Simulation time	57441365 ps
CPU time	7.27 seconds
Started	Aug 17 06:32:14 PM PDT 24
Finished	Aug 17 06:32:22 PM PDT 24
Peak memory	250884 kb
Host	smart-d46f7a43-5571-416c-b46c-09800b737913
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106472367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.106472367
Directory	/workspace/9.lc_ctrl_state_post_trans/latest

Test location	/workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2502403252
Short name	T387
Test name
Test status
Simulation time	11572084 ps
CPU time	1.06 seconds
Started	Aug 17 06:32:13 PM PDT 24
Finished	Aug 17 06:32:14 PM PDT 24
Peak memory	211944 kb
Host	smart-0a4cc898-defc-4416-a95b-32671266d754
User	root
Command	/workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502403252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct rl_volatile_unlock_smoke.2502403252
Directory	/workspace/9.lc_ctrl_volatile_unlock_smoke/latest

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