Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	896124	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1082801

1

T1

2355

T2

1559

T10

696

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1688876	1			T1	4390		T2	1791		T10	560
values[0x0]	144434	1			T1	81		T2	390		T10	268
values[0x1]	145615	1			T1	107		T2	394		T10	276

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	708995	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1269930

1

T1

2782

T2

1759

T10

794

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6717	1			T1	32		T2	12		T20	1
valid_sources[0x01]	5780	1			T1	24		T2	17		T20	3
valid_sources[0x02]	5941	1			T1	9		T2	5		T20	4
valid_sources[0x03]	29813	1			T1	23		T2	5		T20	5
valid_sources[0x04]	6045	1			T1	7		T2	7		T15	18
valid_sources[0x05]	5833	1			T1	17		T2	9		T20	2
valid_sources[0x06]	8822	1			T1	19		T2	13		T20	8
valid_sources[0x07]	6019	1			T1	18		T2	1		T20	5
valid_sources[0x08]	7473	1			T1	26		T2	6		T20	1
valid_sources[0x09]	5792	1			T1	18		T2	14		T20	2
valid_sources[0x0a]	14583	1			T1	16		T2	12		T20	2
valid_sources[0x0b]	7545	1			T1	22		T2	10		T20	1
valid_sources[0x0c]	5531	1			T1	12		T2	4		T20	4
valid_sources[0x0d]	5651	1			T1	13		T2	15		T20	1
valid_sources[0x0e]	5511	1			T1	14		T2	14		T20	5
valid_sources[0x0f]	5760	1			T1	21		T2	10		T20	7
valid_sources[0x10]	5667	1			T1	12		T2	1		T20	2
valid_sources[0x11]	6837	1			T1	17		T2	18		T20	2
valid_sources[0x12]	8220	1			T1	15		T2	14		T14	1
valid_sources[0x13]	7865	1			T1	16		T2	3		T20	9
valid_sources[0x14]	8021	1			T1	22		T2	13		T20	3
valid_sources[0x15]	5474	1			T1	17		T2	2		T20	6
valid_sources[0x16]	5539	1			T1	18		T2	1		T20	5
valid_sources[0x17]	5657	1			T1	17		T2	10		T20	6
valid_sources[0x18]	5665	1			T1	16		T2	13		T15	7
valid_sources[0x19]	6816	1			T1	20		T2	9		T20	2
valid_sources[0x1a]	5743	1			T1	26		T2	6		T20	2
valid_sources[0x1b]	8091	1			T1	18		T2	5		T20	4
valid_sources[0x1c]	7924	1			T1	11		T2	3		T20	2
valid_sources[0x1d]	5604	1			T1	35		T2	5		T20	2
valid_sources[0x1e]	5571	1			T1	18		T2	2		T15	12
valid_sources[0x1f]	6226	1			T1	18		T2	14		T20	1
valid_sources[0x20]	25849	1			T1	16		T2	1		T20	4
valid_sources[0x21]	7228	1			T1	22		T2	11		T20	5
valid_sources[0x22]	9444	1			T1	17		T2	21		T11	1
valid_sources[0x23]	6081	1			T1	14		T2	9		T20	4
valid_sources[0x24]	5688	1			T1	16		T2	31		T5	2
valid_sources[0x25]	5817	1			T1	8		T2	15		T15	2
valid_sources[0x26]	7498	1			T1	17		T2	10		T20	5
valid_sources[0x27]	5682	1			T1	11		T2	17		T20	4
valid_sources[0x28]	5762	1			T1	16		T2	9		T20	3
valid_sources[0x29]	6242	1			T1	17		T2	7		T20	1
valid_sources[0x2a]	6433	1			T1	17		T2	3		T20	3
valid_sources[0x2b]	8345	1			T1	17		T2	6		T15	4
valid_sources[0x2c]	6017	1			T1	8		T2	19		T20	5
valid_sources[0x2d]	5741	1			T1	22		T2	4		T20	4
valid_sources[0x2e]	5561	1			T1	20		T2	9		T20	2
valid_sources[0x2f]	5493	1			T1	11		T2	9		T20	3
valid_sources[0x30]	8943	1			T1	17		T2	21		T20	5
valid_sources[0x31]	5775	1			T1	9		T2	11		T20	2
valid_sources[0x32]	5317	1			T1	20		T2	9		T20	7
valid_sources[0x33]	5765	1			T1	25		T2	7		T15	13
valid_sources[0x34]	5608	1			T1	18		T2	3		T20	3
valid_sources[0x35]	7885	1			T1	18		T2	26		T20	1
valid_sources[0x36]	5636	1			T1	29		T2	19		T20	3
valid_sources[0x37]	5665	1			T1	11		T2	18		T20	2
valid_sources[0x38]	5679	1			T1	15		T2	12		T11	2
valid_sources[0x39]	5332	1			T1	17		T2	6		T20	3
valid_sources[0x3a]	5626	1			T1	31		T2	5		T5	8
valid_sources[0x3b]	5683	1			T1	14		T2	6		T20	1
valid_sources[0x3c]	8490	1			T1	25		T2	2		T20	6
valid_sources[0x3d]	5660	1			T1	20		T2	14		T20	2
valid_sources[0x3e]	21093	1			T1	6		T2	4		T20	4
valid_sources[0x3f]	7821	1			T1	16		T2	4		T20	3
valid_sources[0x40]	5646	1			T1	32		T2	19		T20	4
valid_sources[0x41]	7213	1			T1	12		T2	8		T14	1
valid_sources[0x42]	6717	1			T1	10		T2	12		T20	3
valid_sources[0x43]	8311	1			T1	27		T2	25		T20	1
valid_sources[0x44]	6940	1			T1	15		T2	9		T20	2
valid_sources[0x45]	5787	1			T1	23		T2	9		T20	5
valid_sources[0x46]	7016	1			T1	24		T2	24		T20	2
valid_sources[0x47]	5711	1			T1	24		T2	16		T20	3
valid_sources[0x48]	15941	1			T1	12		T2	12		T20	4
valid_sources[0x49]	5344	1			T1	29		T2	5		T20	5
valid_sources[0x4a]	5600	1			T1	20		T2	10		T20	5
valid_sources[0x4b]	7446	1			T1	10		T2	6		T20	4
valid_sources[0x4c]	7021	1			T1	32		T2	5		T20	3
valid_sources[0x4d]	8842	1			T1	22		T2	19		T20	1
valid_sources[0x4e]	66914	1			T1	14		T2	13		T20	7
valid_sources[0x4f]	5519	1			T1	17		T2	12		T20	3
valid_sources[0x50]	12261	1			T1	21		T2	12		T20	1
valid_sources[0x51]	8570	1			T1	16		T2	3		T20	4
valid_sources[0x52]	7719	1			T1	21		T2	10		T20	2
valid_sources[0x53]	5632	1			T1	7		T2	4		T20	4
valid_sources[0x54]	7601	1			T1	17		T2	16		T20	3
valid_sources[0x55]	6689	1			T1	18		T2	13		T20	4
valid_sources[0x56]	7288	1			T1	14		T2	2		T15	5
valid_sources[0x57]	6025	1			T1	16		T2	12		T20	3
valid_sources[0x58]	5857	1			T1	11		T2	11		T20	1
valid_sources[0x59]	29325	1			T1	24		T2	10		T20	1
valid_sources[0x5a]	5808	1			T1	28		T2	3		T20	8
valid_sources[0x5b]	5490	1			T1	8		T2	11		T20	3
valid_sources[0x5c]	5809	1			T1	20		T2	8		T20	2
valid_sources[0x5d]	6168	1			T1	11		T2	12		T20	2
valid_sources[0x5e]	80963	1			T1	25		T2	15		T20	3
valid_sources[0x5f]	5765	1			T1	34		T2	3		T20	2
valid_sources[0x60]	5922	1			T1	26		T2	22		T20	2
valid_sources[0x61]	6965	1			T1	10		T20	4		T15	7
valid_sources[0x62]	5807	1			T1	20		T2	20		T20	1
valid_sources[0x63]	6627	1			T1	25		T20	1		T15	9
valid_sources[0x64]	5973	1			T1	17		T2	10		T20	2
valid_sources[0x65]	6210	1			T1	10		T2	11		T20	1
valid_sources[0x66]	6462	1			T1	22		T2	15		T20	1
valid_sources[0x67]	5771	1			T1	14		T2	7		T20	4
valid_sources[0x68]	5946	1			T1	13		T2	8		T20	4
valid_sources[0x69]	22611	1			T1	22		T2	19		T14	6
valid_sources[0x6a]	5741	1			T1	10		T2	12		T20	4
valid_sources[0x6b]	10343	1			T1	29		T2	9		T11	1
valid_sources[0x6c]	8028	1			T1	10		T2	2		T20	2
valid_sources[0x6d]	5552	1			T1	15		T2	5		T20	3
valid_sources[0x6e]	7028	1			T1	21		T2	22		T20	3
valid_sources[0x6f]	7448	1			T1	25		T2	2		T20	5
valid_sources[0x70]	5958	1			T1	14		T2	6		T20	3
valid_sources[0x71]	5874	1			T1	18		T2	8		T20	4
valid_sources[0x72]	42669	1			T1	11		T2	22		T20	5
valid_sources[0x73]	5559	1			T1	13		T2	14		T15	9
valid_sources[0x74]	5834	1			T1	21		T2	9		T20	5
valid_sources[0x75]	6018	1			T1	8		T2	14		T20	4
valid_sources[0x76]	5771	1			T1	30		T2	8		T20	5
valid_sources[0x77]	5451	1			T1	19		T2	2		T20	4
valid_sources[0x78]	7153	1			T1	21		T2	9		T20	1
valid_sources[0x79]	5852	1			T1	23		T2	5		T20	3
valid_sources[0x7a]	8370	1			T1	17		T2	5		T20	1
valid_sources[0x7b]	5505	1			T1	19		T2	3		T20	5
valid_sources[0x7c]	5839	1			T1	18		T2	7		T20	1
valid_sources[0x7d]	5855	1			T1	31		T2	10		T20	4
valid_sources[0x7e]	8991	1			T1	22		T2	4		T20	4
valid_sources[0x7f]	5773	1			T1	22		T2	8		T20	4
valid_sources[0x80]	5689	1			T1	18		T2	4		T20	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

833325

1

T1

2197

T2

879

T10

228

values[0x0]

all_enables

biggest_size

125083

1

T1

70

T2

346

T10

232

values[0x1]

all_enables

biggest_size

124393

1

T1

88

T2

334

T10

236