Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	67783523	14482	0	0
claim_transition_if_regwen_rd_A	67783523	1050	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67783523	14482	0	0
T7	42316	0	0	0
T17	618195	0	0	0
T18	0	3	0	0
T23	275410	2	0	0
T24	424620	2	0	0
T32	341837	0	0	0
T33	13332	0	0	0
T52	38714	0	0	0
T66	127168	0	0	0
T67	149090	0	0	0
T86	0	6	0	0
T143	0	1	0	0
T144	0	3	0	0
T145	0	11	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	4	0	0
T149	847	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67783523	1050	0	0
T104	0	33	0	0
T115	0	86	0	0
T146	399411	3	0	0
T147	0	7	0	0
T150	0	12	0	0
T151	0	3	0	0
T152	0	131	0	0
T153	0	4	0	0
T154	0	20	0	0
T155	0	22	0	0
T156	30055	0	0	0
T157	46348	0	0	0
T158	25573	0	0	0
T159	2027	0	0	0
T160	34497	0	0	0
T161	20075	0	0	0
T162	26099	0	0	0
T163	230236	0	0	0
T164	26270	0	0	0