Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	694096	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

878599

1

T1

344

T2

131

T3

252

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1287808	1			T1	376		T2	149		T3	233
values[0x0]	141824	1			T1	95		T2	32		T3	99
values[0x1]	143063	1			T1	105		T2	40		T3	98

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	548412	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1024283

1

T1

399

T2

146

T3

288

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4858	1			T4	12		T10	21		T12	4
valid_sources[0x01]	5405	1			T4	6		T10	35		T12	6
valid_sources[0x02]	6319	1			T10	20		T12	2		T14	3
valid_sources[0x03]	4478	1			T10	29		T12	2		T14	7
valid_sources[0x04]	4843	1			T2	22		T4	2		T10	29
valid_sources[0x05]	6114	1			T4	4		T10	17		T12	20
valid_sources[0x06]	6308	1			T4	10		T10	29		T12	10
valid_sources[0x07]	5893	1			T4	4		T5	9		T10	24
valid_sources[0x08]	4432	1			T3	8		T4	4		T10	16
valid_sources[0x09]	5038	1			T10	24		T14	3		T6	99
valid_sources[0x0a]	7927	1			T3	8		T10	24		T12	7
valid_sources[0x0b]	5487	1			T2	20		T4	6		T10	21
valid_sources[0x0c]	10785	1			T4	2		T10	19		T12	1
valid_sources[0x0d]	6579	1			T10	20		T12	2		T6	85
valid_sources[0x0e]	4307	1			T4	1		T10	25		T12	5
valid_sources[0x0f]	6267	1			T3	2		T4	2		T10	29
valid_sources[0x10]	4587	1			T3	1		T4	6		T10	19
valid_sources[0x11]	4465	1			T4	3		T10	17		T6	94
valid_sources[0x12]	9036	1			T4	6		T10	16		T12	2
valid_sources[0x13]	5417	1			T2	52		T4	3		T10	21
valid_sources[0x14]	6320	1			T10	33		T12	6		T14	14
valid_sources[0x15]	4774	1			T4	6		T10	31		T12	13
valid_sources[0x16]	5348	1			T10	27		T12	10		T14	3
valid_sources[0x17]	4512	1			T10	26		T14	4		T6	117
valid_sources[0x18]	4632	1			T4	11		T10	12		T14	2
valid_sources[0x19]	4510	1			T4	3		T10	24		T13	5
valid_sources[0x1a]	4496	1			T4	2		T10	28		T12	1
valid_sources[0x1b]	4601	1			T4	5		T10	16		T12	8
valid_sources[0x1c]	7305	1			T4	8		T10	18		T12	19
valid_sources[0x1d]	6775	1			T4	4		T10	32		T12	5
valid_sources[0x1e]	5714	1			T4	2		T10	21		T12	15
valid_sources[0x1f]	4367	1			T4	3		T10	36		T12	1
valid_sources[0x20]	5518	1			T10	26		T12	4		T13	2
valid_sources[0x21]	9883	1			T3	9		T4	1		T10	25
valid_sources[0x22]	8982	1			T4	6		T10	25		T14	5
valid_sources[0x23]	5945	1			T4	2		T10	13		T12	6
valid_sources[0x24]	5020	1			T4	3		T10	21		T12	12
valid_sources[0x25]	4824	1			T3	8		T4	1		T10	17
valid_sources[0x26]	4836	1			T4	4		T10	24		T12	5
valid_sources[0x27]	4746	1			T10	23		T14	5		T6	71
valid_sources[0x28]	6480	1			T4	9		T10	18		T12	2
valid_sources[0x29]	7262	1			T2	8		T4	3		T10	20
valid_sources[0x2a]	6688	1			T4	11		T10	21		T12	4
valid_sources[0x2b]	4435	1			T10	21		T13	4		T14	4
valid_sources[0x2c]	4370	1			T4	1		T10	23		T13	1
valid_sources[0x2d]	4389	1			T10	19		T12	1		T14	1
valid_sources[0x2e]	5150	1			T4	2		T10	18		T12	4
valid_sources[0x2f]	5046	1			T4	1		T5	5		T10	23
valid_sources[0x30]	4775	1			T5	4		T10	24		T12	7
valid_sources[0x31]	7198	1			T4	4		T10	24		T14	8
valid_sources[0x32]	6623	1			T4	2		T10	15		T12	1
valid_sources[0x33]	5124	1			T4	9		T5	18		T10	24
valid_sources[0x34]	4797	1			T4	3		T10	18		T12	16
valid_sources[0x35]	9507	1			T5	6		T10	19		T12	7
valid_sources[0x36]	6512	1			T4	11		T10	28		T14	1
valid_sources[0x37]	4841	1			T4	2		T5	15		T10	27
valid_sources[0x38]	4947	1			T10	22		T12	3		T14	6
valid_sources[0x39]	9198	1			T4	6		T10	28		T12	3
valid_sources[0x3a]	5332	1			T4	4		T10	18		T14	9
valid_sources[0x3b]	4553	1			T4	17		T10	18		T12	1
valid_sources[0x3c]	5919	1			T3	10		T10	23		T12	1
valid_sources[0x3d]	4794	1			T10	27		T14	13		T6	76
valid_sources[0x3e]	4436	1			T4	8		T10	13		T12	9
valid_sources[0x3f]	8271	1			T4	17		T10	23		T12	3
valid_sources[0x40]	4869	1			T2	11		T3	7		T4	2
valid_sources[0x41]	14849	1			T4	7		T10	17		T12	1
valid_sources[0x42]	4506	1			T10	31		T12	12		T14	1
valid_sources[0x43]	5473	1			T10	18		T14	1		T6	141
valid_sources[0x44]	6609	1			T10	33		T12	6		T14	7
valid_sources[0x45]	5909	1			T4	9		T10	26		T12	1
valid_sources[0x46]	4976	1			T2	10		T4	3		T10	10
valid_sources[0x47]	7644	1			T4	3		T10	30		T12	5
valid_sources[0x48]	4687	1			T4	20		T10	22		T12	4
valid_sources[0x49]	4588	1			T3	4		T4	6		T10	18
valid_sources[0x4a]	4566	1			T10	22		T12	3		T14	3
valid_sources[0x4b]	9911	1			T3	2		T4	8		T10	26
valid_sources[0x4c]	4796	1			T3	8		T4	6		T5	1
valid_sources[0x4d]	5619	1			T4	5		T10	19		T12	9
valid_sources[0x4e]	4552	1			T3	7		T4	1		T10	23
valid_sources[0x4f]	4634	1			T3	1		T4	1		T10	25
valid_sources[0x50]	4455	1			T4	4		T10	27		T12	4
valid_sources[0x51]	5298	1			T4	2		T10	17		T12	1
valid_sources[0x52]	5095	1			T3	2		T4	8		T10	15
valid_sources[0x53]	110131	1			T3	5		T10	20		T12	8
valid_sources[0x54]	4384	1			T4	7		T10	24		T12	12
valid_sources[0x55]	4684	1			T3	4		T10	21		T12	14
valid_sources[0x56]	4481	1			T4	2		T10	35		T12	12
valid_sources[0x57]	6228	1			T4	6		T10	24		T12	1
valid_sources[0x58]	6200	1			T4	9		T10	18		T12	11
valid_sources[0x59]	7697	1			T10	20		T12	11		T14	6
valid_sources[0x5a]	6855	1			T10	18		T12	4		T14	14
valid_sources[0x5b]	4917	1			T3	51		T10	20		T12	4
valid_sources[0x5c]	10193	1			T3	11		T10	25		T12	4
valid_sources[0x5d]	9511	1			T4	1		T10	27		T12	4
valid_sources[0x5e]	4290	1			T4	6		T10	23		T14	5
valid_sources[0x5f]	4880	1			T10	27		T12	7		T13	2
valid_sources[0x60]	6306	1			T4	16		T10	21		T14	2
valid_sources[0x61]	5005	1			T3	5		T4	14		T10	22
valid_sources[0x62]	10414	1			T4	1		T5	13		T10	11
valid_sources[0x63]	4354	1			T4	5		T10	21		T12	1
valid_sources[0x64]	4702	1			T4	11		T10	24		T14	1
valid_sources[0x65]	4437	1			T4	1		T10	21		T12	4
valid_sources[0x66]	4421	1			T4	2		T5	3		T10	16
valid_sources[0x67]	8363	1			T4	5		T10	38		T12	14
valid_sources[0x68]	4785	1			T4	1		T10	20		T12	15
valid_sources[0x69]	4823	1			T3	8		T10	17		T13	2
valid_sources[0x6a]	4405	1			T4	1		T10	32		T12	5
valid_sources[0x6b]	5100	1			T4	15		T10	24		T12	8
valid_sources[0x6c]	4923	1			T3	10		T4	4		T10	25
valid_sources[0x6d]	5155	1			T1	576		T4	6		T10	22
valid_sources[0x6e]	6338	1			T5	4		T10	23		T12	12
valid_sources[0x6f]	4687	1			T10	14		T12	1		T6	107
valid_sources[0x70]	4623	1			T10	27		T12	10		T13	1
valid_sources[0x71]	4883	1			T10	21		T12	11		T14	3
valid_sources[0x72]	4568	1			T4	6		T10	23		T12	1
valid_sources[0x73]	5224	1			T3	28		T4	9		T10	27
valid_sources[0x74]	5472	1			T4	13		T10	17		T12	2
valid_sources[0x75]	5114	1			T4	6		T10	27		T12	3
valid_sources[0x76]	4798	1			T10	14		T12	6		T14	10
valid_sources[0x77]	4531	1			T4	7		T10	22		T14	5
valid_sources[0x78]	6273	1			T3	9		T10	36		T12	8
valid_sources[0x79]	4632	1			T3	6		T10	21		T12	9
valid_sources[0x7a]	4738	1			T10	21		T12	7		T13	3
valid_sources[0x7b]	4742	1			T4	6		T10	23		T12	3
valid_sources[0x7c]	4649	1			T2	4		T4	1		T10	32
valid_sources[0x7d]	4727	1			T10	19		T12	8		T14	7
valid_sources[0x7e]	4760	1			T3	32		T4	1		T10	22
valid_sources[0x7f]	4731	1			T10	26		T12	15		T14	8
valid_sources[0x80]	4832	1			T3	6		T4	6		T10	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

633033

1

T1

173

T2

69

T3

113

values[0x0]

all_enables

biggest_size

123004

1

T1

77

T2

26

T3

71

values[0x1]

all_enables

biggest_size

122562

1

T1

94

T2

36

T3

68