Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	60643288	14569	0	0
claim_transition_if_regwen_rd_A	60643288	1697	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60643288	14569	0	0
T6	159503	8	0	0
T18	1062	0	0	0
T22	27228	0	0	0
T23	26915	0	0	0
T25	35214	0	0	0
T26	83208	0	0	0
T27	162921	0	0	0
T28	399351	0	0	0
T48	0	6	0	0
T89	1519	0	0	0
T90	6249	0	0	0
T94	0	10	0	0
T95	0	4	0	0
T100	0	14	0	0
T108	0	4	0	0
T146	0	5	0	0
T147	0	10	0	0
T148	0	10	0	0
T149	0	9	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	60643288	1697	0	0
T111	0	39	0	0
T113	0	32	0	0
T115	0	12	0	0
T124	0	2	0	0
T141	0	27	0	0
T146	201104	6	0	0
T150	0	9	0	0
T151	0	2	0	0
T152	0	7	0	0
T153	0	4	0	0
T154	1903	0	0	0
T155	18633	0	0	0
T156	59754	0	0	0
T157	224665	0	0	0
T158	1403	0	0	0
T159	1324	0	0	0
T160	75645	0	0	0
T161	1321	0	0	0
T162	4958	0	0	0