Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	809516	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1004986

1

T1

41

T2

5

T3

96

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1518898	1			T1	49		T2	24		T3	92
values[0x0]	147846	1			T1	11		T2	5		T3	35
values[0x1]	147758	1			T1	6		T2	3		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	639706	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1174796

1

T1

44

T2

15

T3

117

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7862	1			T3	2		T18	10		T23	10
valid_sources[0x01]	6156	1			T16	1		T18	3		T22	2
valid_sources[0x02]	4837	1			T3	2		T18	5		T30	1
valid_sources[0x03]	5148	1			T3	2		T18	5		T22	3
valid_sources[0x04]	69438	1			T18	3		T23	3		T30	4
valid_sources[0x05]	5066	1			T16	5		T18	5		T23	14
valid_sources[0x06]	7097	1			T3	1		T18	6		T22	1
valid_sources[0x07]	7218	1			T3	1		T18	5		T22	3
valid_sources[0x08]	5311	1			T3	1		T18	5		T22	1
valid_sources[0x09]	4912	1			T16	1		T18	4		T33	2
valid_sources[0x0a]	8167	1			T18	2		T22	1		T6	1
valid_sources[0x0b]	4833	1			T18	2		T22	3		T6	1
valid_sources[0x0c]	5205	1			T3	2		T18	7		T22	1
valid_sources[0x0d]	5623	1			T3	1		T16	4		T18	3
valid_sources[0x0e]	5833	1			T15	5		T18	6		T6	1
valid_sources[0x0f]	5194	1			T13	1		T18	6		T22	1
valid_sources[0x10]	4948	1			T2	32		T3	1		T18	9
valid_sources[0x11]	10218	1			T18	4		T22	3		T6	1
valid_sources[0x12]	6142	1			T18	3		T22	2		T23	2
valid_sources[0x13]	7247	1			T18	6		T6	1		T23	5
valid_sources[0x14]	4618	1			T18	5		T22	1		T23	3
valid_sources[0x15]	4914	1			T18	6		T22	1		T6	1
valid_sources[0x16]	5599	1			T18	6		T22	3		T26	1
valid_sources[0x17]	4995	1			T18	8		T22	1		T23	3
valid_sources[0x18]	4937	1			T18	1		T22	1		T23	5
valid_sources[0x19]	5306	1			T18	3		T22	1		T23	6
valid_sources[0x1a]	7587	1			T18	9		T26	3		T23	31
valid_sources[0x1b]	16196	1			T18	2		T23	7		T29	5
valid_sources[0x1c]	5140	1			T18	7		T22	1		T26	1
valid_sources[0x1d]	5006	1			T3	1		T16	2		T18	9
valid_sources[0x1e]	6154	1			T3	2		T18	8		T22	2
valid_sources[0x1f]	5287	1			T18	6		T23	4		T30	5
valid_sources[0x20]	5085	1			T16	1		T18	3		T22	1
valid_sources[0x21]	6585	1			T18	3		T23	11		T29	14
valid_sources[0x22]	5262	1			T3	1		T18	2		T6	1
valid_sources[0x23]	5046	1			T3	4		T15	1		T18	3
valid_sources[0x24]	4663	1			T18	5		T33	3		T23	5
valid_sources[0x25]	6177	1			T15	8		T18	3		T22	2
valid_sources[0x26]	5248	1			T18	1		T22	2		T6	2
valid_sources[0x27]	17580	1			T3	2		T18	13		T22	1
valid_sources[0x28]	4824	1			T18	5		T6	2		T23	5
valid_sources[0x29]	23329	1			T3	1		T18	5		T22	4
valid_sources[0x2a]	4960	1			T3	1		T16	1		T18	6
valid_sources[0x2b]	5148	1			T18	6		T22	2		T6	1
valid_sources[0x2c]	6246	1			T3	1		T18	1		T23	3
valid_sources[0x2d]	6911	1			T3	1		T18	3		T6	1
valid_sources[0x2e]	6915	1			T18	1		T22	1		T23	18
valid_sources[0x2f]	5205	1			T3	2		T18	7		T22	1
valid_sources[0x30]	6578	1			T18	3		T22	2		T23	2
valid_sources[0x31]	12324	1			T3	3		T18	2		T23	6
valid_sources[0x32]	6895	1			T3	1		T18	4		T22	3
valid_sources[0x33]	5102	1			T18	8		T22	1		T6	1
valid_sources[0x34]	6647	1			T15	7		T16	1		T18	5
valid_sources[0x35]	5327	1			T3	1		T18	4		T22	1
valid_sources[0x36]	5150	1			T3	1		T18	8		T22	1
valid_sources[0x37]	4851	1			T18	4		T37	1		T23	10
valid_sources[0x38]	4986	1			T3	1		T18	5		T6	1
valid_sources[0x39]	5806	1			T18	5		T22	3		T26	1
valid_sources[0x3a]	5295	1			T3	1		T15	3		T16	1
valid_sources[0x3b]	5137	1			T3	1		T18	7		T55	1
valid_sources[0x3c]	5191	1			T18	8		T22	1		T6	1
valid_sources[0x3d]	5018	1			T18	8		T22	1		T29	4
valid_sources[0x3e]	7015	1			T3	3		T15	5		T18	4
valid_sources[0x3f]	5137	1			T4	448		T18	4		T23	3
valid_sources[0x40]	5043	1			T18	2		T22	2		T23	9
valid_sources[0x41]	4636	1			T3	1		T18	6		T22	1
valid_sources[0x42]	5044	1			T18	3		T22	1		T55	3
valid_sources[0x43]	4918	1			T3	1		T15	1		T18	2
valid_sources[0x44]	4892	1			T3	2		T15	16		T18	5
valid_sources[0x45]	5500	1			T18	5		T22	3		T55	2
valid_sources[0x46]	5702	1			T18	2		T22	1		T23	10
valid_sources[0x47]	4897	1			T18	9		T6	1		T23	11
valid_sources[0x48]	5032	1			T18	7		T22	2		T33	5
valid_sources[0x49]	4758	1			T3	1		T18	3		T22	3
valid_sources[0x4a]	5089	1			T3	1		T18	3		T22	2
valid_sources[0x4b]	4663	1			T18	2		T22	3		T23	2
valid_sources[0x4c]	6276	1			T18	4		T6	1		T23	6
valid_sources[0x4d]	5302	1			T15	4		T16	1		T18	5
valid_sources[0x4e]	5047	1			T18	2		T55	1		T30	6
valid_sources[0x4f]	4785	1			T18	6		T22	1		T23	5
valid_sources[0x50]	6057	1			T3	1		T18	5		T22	1
valid_sources[0x51]	5171	1			T18	3		T22	1		T6	1
valid_sources[0x52]	4531	1			T3	2		T18	5		T22	2
valid_sources[0x53]	5658	1			T3	1		T18	3		T30	3
valid_sources[0x54]	5151	1			T3	2		T18	10		T6	2
valid_sources[0x55]	6156	1			T3	4		T18	11		T22	1
valid_sources[0x56]	4977	1			T18	8		T22	2		T6	1
valid_sources[0x57]	4948	1			T3	1		T18	7		T22	2
valid_sources[0x58]	9333	1			T18	10		T22	1		T23	12
valid_sources[0x59]	4930	1			T14	3		T18	5		T6	1
valid_sources[0x5a]	5132	1			T18	2		T22	2		T37	1
valid_sources[0x5b]	4945	1			T16	1		T18	3		T6	2
valid_sources[0x5c]	4720	1			T18	3		T7	4		T23	1
valid_sources[0x5d]	7396	1			T18	3		T22	3		T6	1
valid_sources[0x5e]	5217	1			T3	2		T18	4		T22	1
valid_sources[0x5f]	38235	1			T3	2		T18	2		T26	1
valid_sources[0x60]	6631	1			T3	2		T15	8		T18	17
valid_sources[0x61]	15753	1			T18	1		T22	1		T26	2
valid_sources[0x62]	6191	1			T3	2		T18	4		T22	1
valid_sources[0x63]	4789	1			T18	6		T22	1		T6	1
valid_sources[0x64]	5104	1			T18	5		T22	1		T6	1
valid_sources[0x65]	4721	1			T18	4		T22	1		T23	8
valid_sources[0x66]	4835	1			T3	2		T18	3		T6	1
valid_sources[0x67]	7485	1			T18	3		T22	2		T29	1
valid_sources[0x68]	4870	1			T3	1		T18	4		T22	5
valid_sources[0x69]	4890	1			T15	13		T18	4		T22	2
valid_sources[0x6a]	5382	1			T18	2		T22	1		T6	1
valid_sources[0x6b]	4692	1			T3	3		T18	4		T22	3
valid_sources[0x6c]	7680	1			T16	1		T18	3		T33	1
valid_sources[0x6d]	5443	1			T3	1		T18	3		T23	27
valid_sources[0x6e]	6668	1			T3	1		T16	1		T18	2
valid_sources[0x6f]	5285	1			T18	8		T22	2		T23	2
valid_sources[0x70]	5212	1			T18	6		T22	1		T6	1
valid_sources[0x71]	4838	1			T3	2		T18	3		T22	3
valid_sources[0x72]	5258	1			T3	2		T18	5		T22	2
valid_sources[0x73]	5198	1			T18	7		T23	10		T55	2
valid_sources[0x74]	9023	1			T3	1		T18	6		T23	13
valid_sources[0x75]	4918	1			T3	2		T16	1		T18	1
valid_sources[0x76]	5017	1			T18	9		T23	3		T55	1
valid_sources[0x77]	5529	1			T3	2		T18	4		T22	1
valid_sources[0x78]	5350	1			T18	12		T22	1		T6	1
valid_sources[0x79]	5100	1			T3	2		T18	5		T22	1
valid_sources[0x7a]	5643	1			T18	4		T22	1		T6	1
valid_sources[0x7b]	4587	1			T18	9		T22	3		T6	1
valid_sources[0x7c]	5090	1			T3	1		T18	4		T22	1
valid_sources[0x7d]	4674	1			T18	11		T22	4		T55	1
valid_sources[0x7e]	4992	1			T3	2		T13	1		T18	6
valid_sources[0x7f]	4992	1			T16	2		T18	4		T6	1
valid_sources[0x80]	5012	1			T18	5		T22	1		T23	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

750216

1

T1

29

T3

35

T4

146

values[0x0]

all_enables

biggest_size

128196

1

T1

8

T2

4

T3

32

values[0x1]

all_enables

biggest_size

126574

1

T1

4

T2

1

T3

29