Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	58718556	14835	0	0
claim_transition_if_regwen_rd_A	58718556	1280	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58718556	14835	0	0
T63	233858	18	0	0
T102	0	3	0	0
T103	0	2	0	0
T111	0	16	0	0
T146	0	1	0	0
T147	0	7	0	0
T148	0	1	0	0
T149	0	4	0	0
T150	0	4	0	0
T151	0	3	0	0
T152	25230	0	0	0
T153	45316	0	0	0
T154	54039	0	0	0
T155	136848	0	0	0
T156	16574	0	0	0
T157	2249	0	0	0
T158	773	0	0	0
T159	36981	0	0	0
T160	102515	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58718556	1280	0	0
T70	36072	0	0	0
T102	194854	6	0	0
T109	0	46	0	0
T123	0	10	0	0
T149	0	20	0	0
T161	0	7	0	0
T162	0	5	0	0
T163	0	114	0	0
T164	0	108	0	0
T165	0	225	0	0
T166	0	27	0	0
T167	32517	0	0	0
T168	2796	0	0	0
T169	8416	0	0	0
T170	117277	0	0	0
T171	1094	0	0	0
T172	1145	0	0	0
T173	1647	0	0	0
T174	18795	0	0	0