Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59100173

1

T1

926

T2

2760

T3

1912

auto[1]

1080079

1

T4

198

T11

686

T13

9353

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59082616

1

T1

926

T2

2760

T3

1615

auto[1]

1097636

1

T3

297

T4

396

T11

980

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5300584	1			T1	84		T2	1331		T3	330
auto[IdleSt]	15203022	1			T1	63		T2	375		T3	986
auto[ClkMuxSt]	29494	1			T1	1		T2	13		T3	3
auto[CntIncrSt]	29314	1			T1	1		T2	13		T3	3
auto[CntProgSt]	1039550	1			T1	2		T2	26		T3	6
auto[TransCheckSt]	23275	1			T1	1		T2	13		T4	5
auto[TokenHashSt]	18485943	1			T1	105		T2	144		T4	506
auto[FlashRmaSt]	29015	1			T2	71		T4	11		T7	17
auto[TokenCheck0St]	10366	1			T2	13		T4	5		T7	17
auto[TokenCheck1St]	7486	1			T2	13		T4	5		T7	17
auto[TransProgSt]	273519	1			T2	26		T4	1847		T7	34
auto[PostTransSt]	8432345	1			T1	669		T2	713		T3	172
auto[ScrapSt]	90585	1			T2	9		T7	284		T13	16
auto[EscalateSt]	4410314	1			T3	412		T4	1024		T11	6374
auto[InvalidSt]	6814153	1			T4	442		T30	7391		T26	686

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1287	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6814153	1			T4	442		T30	7391		T26	686
EscalateSt	4410314	1			T3	412		T4	1024		T11	6374
ScrapSt	90585	1			T2	9		T7	284		T13	16
PostTransSt	8432345	1			T1	669		T2	713		T3	172
TransProgSt	273519	1			T2	26		T4	1847		T7	34
TokenCheck1St	7486	1			T2	13		T4	5		T7	17
TokenCheck0St	10366	1			T2	13		T4	5		T7	17
FlashRmaSt	29015	1			T2	71		T4	11		T7	17
TokenHashSt	18485943	1			T1	105		T2	144		T4	506
TransCheckSt	23275	1			T1	1		T2	13		T4	5
CntProgSt	1039550	1			T1	2		T2	26		T3	6
CntIncrSt	29314	1			T1	1		T2	13		T3	3
ClkMuxSt	29494	1			T1	1		T2	13		T3	3
IdleSt	15203022	1			T1	63		T2	375		T3	986
ResetSt	5300584	1			T1	84		T2	1331		T3	330
arcs[ResetSt=>IdleSt]	42178	1			T1	1		T2	14		T3	4
arcs[IdleSt=>ScrapSt]	247	1			T2	1		T7	1		T13	4
arcs[IdleSt=>ClkMuxSt]	29345	1			T1	1		T2	13		T3	3
arcs[ClkMuxSt=>CntIncrSt]	29314	1			T1	1		T2	13		T3	3
arcs[CntIncrSt=>PostTransSt]	1325	1			T17	12		T28	5		T29	9
arcs[CntIncrSt=>CntProgSt]	27918	1			T1	1		T2	13		T3	3
arcs[CntProgSt=>PostTransSt]	3634	1			T3	3		T11	17		T17	13
arcs[CntProgSt=>TransCheckSt]	23275	1			T1	1		T2	13		T4	5
arcs[TransCheckSt=>PostTransSt]	3242	1			T17	11		T14	39		T28	6
arcs[TransCheckSt=>TokenHashSt]	19924	1			T1	1		T2	13		T4	5
arcs[TokenHashSt=>PostTransSt]	8677	1			T1	1		T17	29		T19	1
arcs[TokenHashSt=>FlashRmaSt]	10399	1			T2	13		T4	5		T7	17
arcs[FlashRmaSt=>TokenCheck0St]	10366	1			T2	13		T4	5		T7	17
arcs[TokenCheck0St=>PostTransSt]	2820	1			T17	11		T14	13		T20	17
arcs[TokenCheck0St=>TokenCheck1St]	7486	1			T2	13		T4	5		T7	17
arcs[TokenCheck1St=>PostTransSt]	619	1			T14	10		T20	3		T25	4
arcs[TransProgSt=>PostTransSt]	6048	1			T2	13		T4	5		T7	17
arcs[IdleSt=>EscalateSt]	150	1			T22	7		T53	6		T54	4
arcs[ClkMuxSt=>EscalateSt]	31	1			T22	1		T53	1		T54	2
arcs[CntIncrSt=>EscalateSt]	71	1			T13	1		T22	2		T53	1
arcs[CntProgSt=>EscalateSt]	1009	1			T13	45		T22	26		T53	23
arcs[TransCheckSt=>EscalateSt]	109	1			T13	1		T55	3		T59	2
arcs[TokenHashSt=>EscalateSt]	848	1			T13	10		T22	5		T53	8
arcs[FlashRmaSt=>EscalateSt]	33	1			T53	1		T55	1		T56	2
arcs[TokenCheck0St=>EscalateSt]	60	1			T13	4		T22	2		T53	1
arcs[TokenCheck1St=>EscalateSt]	28	1			T59	2		T56	2		T60	3
arcs[TransProgSt=>EscalateSt]	791	1			T13	19		T22	11		T53	13
arcs[PostTransSt=>EscalateSt]	4027	1			T3	3		T11	17		T13	1
arcs[InvalidSt=>EscalateSt]	9256	1			T4	6		T30	5		T26	3

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5300438	1			T1	84		T2	1331		T3	330
auto[0]	auto[IdleSt]	15202927	1			T1	63		T2	375		T3	986
auto[0]	auto[ClkMuxSt]	29476	1			T1	1		T2	13		T3	3
auto[0]	auto[CntIncrSt]	29267	1			T1	1		T2	13		T3	3
auto[0]	auto[CntProgSt]	1038866	1			T1	2		T2	26		T3	6
auto[0]	auto[TransCheckSt]	23201	1			T1	1		T2	13		T4	5
auto[0]	auto[TokenHashSt]	18485370	1			T1	105		T2	144		T4	506
auto[0]	auto[FlashRmaSt]	28996	1			T2	71		T4	11		T7	17
auto[0]	auto[TokenCheck0St]	10327	1			T2	13		T4	5		T7	17
auto[0]	auto[TokenCheck1St]	7467	1			T2	13		T4	5		T7	17
auto[0]	auto[TransProgSt]	272999	1			T2	26		T4	1847		T7	34
auto[0]	auto[PostTransSt]	8430305	1			T1	669		T2	713		T3	172
auto[0]	auto[ScrapSt]	90526	1			T2	9		T7	284		T13	13
auto[0]	auto[EscalateSt]	3339114	1			T3	412		T4	828		T11	5695
auto[0]	auto[InvalidSt]	6809607	1			T4	440		T30	7388		T26	685
auto[1]	auto[ResetSt]	146	1			T13	3		T22	2		T53	4
auto[1]	auto[IdleSt]	95	1			T22	4		T53	3		T54	3
auto[1]	auto[ClkMuxSt]	18	1			T53	1		T54	1		T60	2
auto[1]	auto[CntIncrSt]	47	1			T13	1		T22	2		T53	1
auto[1]	auto[CntProgSt]	684	1			T13	31		T22	21		T53	18
auto[1]	auto[TransCheckSt]	74	1			T13	1		T55	2		T59	2
auto[1]	auto[TokenHashSt]	573	1			T13	4		T22	5		T53	5
auto[1]	auto[FlashRmaSt]	19	1			T56	2		T54	1		T232	1
auto[1]	auto[TokenCheck0St]	39	1			T13	1		T22	2		T53	1
auto[1]	auto[TokenCheck1St]	19	1			T59	1		T56	1		T60	2
auto[1]	auto[TransProgSt]	520	1			T13	13		T22	6		T53	8
auto[1]	auto[PostTransSt]	2040	1			T11	7		T13	1		T17	6
auto[1]	auto[ScrapSt]	59	1			T13	3		T55	2		T56	1
auto[1]	auto[EscalateSt]	1071200	1			T4	196		T11	679		T13	9295
auto[1]	auto[InvalidSt]	4546	1			T4	2		T30	3		T26	1

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5300437	1			T1	84		T2	1331		T3	330
auto[0]	auto[IdleSt]	15202921	1			T1	63		T2	375		T3	986
auto[0]	auto[ClkMuxSt]	29469	1			T1	1		T2	13		T3	3
auto[0]	auto[CntIncrSt]	29268	1			T1	1		T2	13		T3	3
auto[0]	auto[CntProgSt]	1038887	1			T1	2		T2	26		T3	6
auto[0]	auto[TransCheckSt]	23209	1			T1	1		T2	13		T4	5
auto[0]	auto[TokenHashSt]	18485370	1			T1	105		T2	144		T4	506
auto[0]	auto[FlashRmaSt]	28991	1			T2	71		T4	11		T7	17
auto[0]	auto[TokenCheck0St]	10328	1			T2	13		T4	5		T7	17
auto[0]	auto[TokenCheck1St]	7468	1			T2	13		T4	5		T7	17
auto[0]	auto[TransProgSt]	272994	1			T2	26		T4	1847		T7	34
auto[0]	auto[PostTransSt]	8430244	1			T1	669		T2	713		T3	169
auto[0]	auto[ScrapSt]	90542	1			T2	9		T7	284		T13	14
auto[0]	auto[EscalateSt]	3321758	1			T3	118		T4	632		T11	5404
auto[0]	auto[InvalidSt]	6809443	1			T4	438		T30	7389		T26	684
auto[1]	auto[ResetSt]	147	1			T13	5		T22	3		T53	3
auto[1]	auto[IdleSt]	101	1			T22	4		T53	3		T54	3
auto[1]	auto[ClkMuxSt]	25	1			T22	1		T53	1		T54	2
auto[1]	auto[CntIncrSt]	46	1			T13	1		T22	1		T55	1
auto[1]	auto[CntProgSt]	663	1			T13	28		T22	15		T53	17
auto[1]	auto[TransCheckSt]	66	1			T13	1		T55	3		T56	1
auto[1]	auto[TokenHashSt]	573	1			T13	9		T22	3		T53	6
auto[1]	auto[FlashRmaSt]	24	1			T53	1		T55	1		T56	1
auto[1]	auto[TokenCheck0St]	38	1			T13	3		T22	2		T59	1
auto[1]	auto[TokenCheck1St]	18	1			T59	1		T56	1		T60	2
auto[1]	auto[TransProgSt]	525	1			T13	16		T22	8		T53	8
auto[1]	auto[PostTransSt]	2101	1			T3	3		T11	10		T13	1
auto[1]	auto[ScrapSt]	43	1			T13	2		T55	1		T56	1
auto[1]	auto[EscalateSt]	1088556	1			T3	294		T4	392		T11	970
auto[1]	auto[InvalidSt]	4710	1			T4	4		T30	2		T26	2