Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.96 97.92 96.12 93.40 97.62 98.52 99.00 96.11


Total tests in report: 1000
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.91 67.91 81.74 81.74 46.03 46.03 55.79 55.79 61.90 61.90 82.84 82.84 92.29 92.29 54.77 54.77 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1488849372
78.88 10.97 88.48 6.75 75.51 29.48 74.36 18.57 66.67 4.76 88.56 5.72 94.28 1.99 64.31 9.54 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.4095864217
83.46 4.58 95.18 6.70 77.08 1.57 81.86 7.50 73.81 7.14 91.53 2.97 94.28 0.00 70.49 6.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.4101541567
85.91 2.45 95.69 0.51 79.57 2.50 82.91 1.05 80.95 7.14 93.43 1.91 94.28 0.00 74.56 4.06 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.258506578
87.64 1.73 96.70 1.01 85.21 5.64 83.12 0.20 80.95 0.00 94.92 1.48 95.02 0.75 77.56 3.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3064473945
89.25 1.61 96.70 0.00 85.21 0.00 83.12 0.00 90.48 9.52 94.92 0.00 95.02 0.00 79.33 1.77 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.2712932771
90.81 1.56 96.70 0.00 86.32 1.11 89.13 6.01 90.48 0.00 94.92 0.00 95.27 0.25 82.86 3.53 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3664461901
92.12 1.31 96.80 0.10 89.09 2.77 89.17 0.04 90.48 0.00 95.55 0.64 96.27 1.00 87.46 4.59 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.150737747
92.96 0.84 96.91 0.10 89.83 0.74 89.51 0.34 92.86 2.38 96.40 0.85 96.52 0.25 88.69 1.24 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.1274107278
93.54 0.58 96.91 0.00 89.93 0.09 89.53 0.02 95.24 2.38 96.40 0.00 96.52 0.00 90.28 1.59 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.3680139288
94.03 0.49 97.01 0.10 90.20 0.28 90.58 1.04 95.24 0.00 96.82 0.42 96.52 0.00 91.87 1.59 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.774084330
94.49 0.46 97.16 0.15 91.40 1.20 90.58 0.00 95.24 0.00 97.25 0.42 96.52 0.00 93.29 1.41 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1437776066
94.83 0.34 97.16 0.00 91.40 0.00 90.58 0.00 97.62 2.38 97.25 0.00 96.52 0.00 93.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.2279140991
95.07 0.24 97.31 0.15 91.68 0.28 91.17 0.60 97.62 0.00 97.46 0.21 96.77 0.25 93.46 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.3420825470
95.28 0.21 97.31 0.00 91.68 0.00 91.17 0.00 97.62 0.00 97.46 0.00 98.26 1.49 93.46 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2914471256
95.49 0.21 97.67 0.36 92.61 0.92 91.36 0.18 97.62 0.00 97.46 0.00 98.26 0.00 93.46 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2433819691
95.65 0.16 97.67 0.00 92.98 0.37 91.36 0.00 97.62 0.00 97.46 0.00 98.51 0.25 93.99 0.53 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.303030817
95.79 0.13 97.67 0.00 92.98 0.00 92.29 0.93 97.62 0.00 97.46 0.00 98.51 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.3084481160
95.91 0.12 97.82 0.15 93.25 0.28 92.29 0.00 97.62 0.00 97.88 0.42 98.51 0.00 93.99 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.3957210835
96.02 0.11 97.92 0.10 93.25 0.00 92.42 0.13 97.62 0.00 98.09 0.21 98.51 0.00 94.35 0.35 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.3172579170
96.12 0.10 97.92 0.00 93.25 0.00 92.88 0.47 97.62 0.00 98.31 0.21 98.51 0.00 94.35 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.3585440908
96.20 0.08 97.92 0.00 93.81 0.55 92.88 0.00 97.62 0.00 98.31 0.00 98.51 0.00 94.35 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3679445303
96.27 0.07 97.92 0.00 93.81 0.00 93.01 0.12 97.62 0.00 98.31 0.00 98.51 0.00 94.70 0.35 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.28827717
96.33 0.07 97.92 0.00 93.90 0.09 93.17 0.16 97.62 0.00 98.52 0.21 98.51 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.213157553
96.40 0.06 97.92 0.00 94.18 0.28 93.17 0.00 97.62 0.00 98.52 0.00 98.51 0.00 94.88 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1475388591
96.46 0.06 97.92 0.00 94.45 0.28 93.17 0.00 97.62 0.00 98.52 0.00 98.51 0.00 95.05 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2590327177
96.51 0.05 97.92 0.00 94.45 0.00 93.17 0.00 97.62 0.00 98.52 0.00 98.51 0.00 95.41 0.35 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.3153106571
96.55 0.04 97.92 0.00 94.73 0.28 93.17 0.00 97.62 0.00 98.52 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2180692156
96.59 0.04 97.92 0.00 95.01 0.28 93.17 0.00 97.62 0.00 98.52 0.00 98.51 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3785413735
96.63 0.04 97.92 0.00 95.01 0.00 93.17 0.00 97.62 0.00 98.52 0.00 98.76 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3661303789
96.66 0.04 97.92 0.00 95.01 0.00 93.17 0.00 97.62 0.00 98.52 0.00 99.00 0.25 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1776678325
96.69 0.03 97.92 0.00 95.01 0.00 93.20 0.03 97.62 0.00 98.52 0.00 99.00 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1911401360
96.72 0.03 97.92 0.00 95.19 0.18 93.20 0.00 97.62 0.00 98.52 0.00 99.00 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1755238490
96.75 0.03 97.92 0.00 95.38 0.18 93.20 0.00 97.62 0.00 98.52 0.00 99.00 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1590361418
96.77 0.03 97.92 0.00 95.56 0.18 93.20 0.00 97.62 0.00 98.52 0.00 99.00 0.00 95.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3012696496
96.80 0.03 97.92 0.00 95.56 0.00 93.20 0.00 97.62 0.00 98.52 0.00 99.00 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.69429530
96.82 0.03 97.92 0.00 95.56 0.00 93.20 0.00 97.62 0.00 98.52 0.00 99.00 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1801641160
96.85 0.03 97.92 0.00 95.56 0.00 93.20 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3698326895
96.87 0.02 97.92 0.00 95.56 0.00 93.34 0.14 97.62 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.2355199916
96.88 0.01 97.92 0.00 95.66 0.09 93.34 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2634595809
96.89 0.01 97.92 0.00 95.75 0.09 93.34 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3694081232
96.91 0.01 97.92 0.00 95.84 0.09 93.34 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.869822824
96.92 0.01 97.92 0.00 95.93 0.09 93.34 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1860131703
96.93 0.01 97.92 0.00 96.03 0.09 93.34 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1923913700
96.95 0.01 97.92 0.00 96.12 0.09 93.34 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.121072349
96.95 0.01 97.92 0.00 96.12 0.00 93.39 0.05 97.62 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3054194261
96.96 0.01 97.92 0.00 96.12 0.00 93.40 0.01 97.62 0.00 98.52 0.00 99.00 0.00 96.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1398973182

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.399161401
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1298108698
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3371029913
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.624221012
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3655024002
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.395413634
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3437685046
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1454897040
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2832534454
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1659870186
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1169456340
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.4207483483
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1069093100
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2049863718
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1121743781
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2956515632
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4114665929
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.67113913
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3933275872
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3592053733
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2619028242
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3811621005
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.295699883
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1994763872
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3882964071
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2723406253
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.737147147
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.4067826363
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2969620407
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3708393985
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2728290384
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3394189285
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1466273821
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2222011598
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2402297674
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1902764616
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2152946831
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4175549923
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.924539094
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3582050725
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2713792461
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1502922443
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Total test records in report: 1000
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1911401360 Aug 23 10:05:53 PM UTC 24 Aug 23 10:05:54 PM UTC 24 46357974 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.323828107 Aug 23 10:05:53 PM UTC 24 Aug 23 10:05:56 PM UTC 24 115046636 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.1129087382 Aug 23 10:05:55 PM UTC 24 Aug 23 10:05:57 PM UTC 24 20150120 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.3709409990 Aug 23 10:05:56 PM UTC 24 Aug 23 10:05:58 PM UTC 24 126141028 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3034225051 Aug 23 10:05:57 PM UTC 24 Aug 23 10:06:01 PM UTC 24 632501173 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.2552985706 Aug 23 10:05:58 PM UTC 24 Aug 23 10:06:01 PM UTC 24 88790991 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.385725199 Aug 23 10:05:54 PM UTC 24 Aug 23 10:06:02 PM UTC 24 94978680 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1398973182 Aug 23 10:05:56 PM UTC 24 Aug 23 10:06:03 PM UTC 24 271166675 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.3172579170 Aug 23 10:05:57 PM UTC 24 Aug 23 10:06:04 PM UTC 24 411482718 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1488849372 Aug 23 10:05:55 PM UTC 24 Aug 23 10:06:06 PM UTC 24 1641293786 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.3420825470 Aug 23 10:05:55 PM UTC 24 Aug 23 10:06:08 PM UTC 24 1550407037 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.3054194261 Aug 23 10:05:55 PM UTC 24 Aug 23 10:06:09 PM UTC 24 287297084 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.4095864217 Aug 23 10:05:57 PM UTC 24 Aug 23 10:06:09 PM UTC 24 410100760 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.4245477260 Aug 23 10:06:10 PM UTC 24 Aug 23 10:06:11 PM UTC 24 37722157 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.774084330 Aug 23 10:06:02 PM UTC 24 Aug 23 10:06:12 PM UTC 24 268025662 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2433819691 Aug 23 10:06:10 PM UTC 24 Aug 23 10:06:12 PM UTC 24 24296113 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.711806438 Aug 23 10:06:10 PM UTC 24 Aug 23 10:06:12 PM UTC 24 105729065 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.267300203 Aug 23 10:06:03 PM UTC 24 Aug 23 10:06:13 PM UTC 24 251876764 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.28827717 Aug 23 10:06:13 PM UTC 24 Aug 23 10:06:17 PM UTC 24 86783124 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1141853120 Aug 23 10:06:13 PM UTC 24 Aug 23 10:06:17 PM UTC 24 80242372 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1724651639 Aug 23 10:05:58 PM UTC 24 Aug 23 10:06:18 PM UTC 24 5575584228 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.1608936060 Aug 23 10:06:18 PM UTC 24 Aug 23 10:06:20 PM UTC 24 11599118 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.3632939285 Aug 23 10:05:53 PM UTC 24 Aug 23 10:06:20 PM UTC 24 1250043265 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.742611330 Aug 23 10:06:01 PM UTC 24 Aug 23 10:06:21 PM UTC 24 2861201731 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3146656761 Aug 23 10:06:14 PM UTC 24 Aug 23 10:06:22 PM UTC 24 263401614 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.258506578 Aug 23 10:06:13 PM UTC 24 Aug 23 10:06:24 PM UTC 24 295299072 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.2447349579 Aug 23 10:06:19 PM UTC 24 Aug 23 10:06:27 PM UTC 24 1822356875 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.2153700195 Aug 23 10:06:22 PM UTC 24 Aug 23 10:06:27 PM UTC 24 356219556 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.3064473945 Aug 23 10:06:25 PM UTC 24 Aug 23 10:06:32 PM UTC 24 431487313 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.1930047778 Aug 23 10:06:18 PM UTC 24 Aug 23 10:06:34 PM UTC 24 1254213793 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2370431011 Aug 23 10:06:06 PM UTC 24 Aug 23 10:06:35 PM UTC 24 492145491 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.1752399756 Aug 23 10:06:27 PM UTC 24 Aug 23 10:06:36 PM UTC 24 338905548 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.3100680179 Aug 23 10:06:35 PM UTC 24 Aug 23 10:06:41 PM UTC 24 472576765 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.896314787 Aug 23 10:06:27 PM UTC 24 Aug 23 10:06:42 PM UTC 24 3594160159 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.4145961913 Aug 23 10:06:13 PM UTC 24 Aug 23 10:06:43 PM UTC 24 399487162 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.2479641992 Aug 23 10:06:21 PM UTC 24 Aug 23 10:06:45 PM UTC 24 4066523357 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.3962316971 Aug 23 10:06:44 PM UTC 24 Aug 23 10:06:46 PM UTC 24 52378094 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.1557021978 Aug 23 10:06:36 PM UTC 24 Aug 23 10:06:48 PM UTC 24 452872769 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.61195939 Aug 23 10:06:47 PM UTC 24 Aug 23 10:06:49 PM UTC 24 29642306 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1597845083 Aug 23 10:06:46 PM UTC 24 Aug 23 10:06:49 PM UTC 24 75280974 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.4101541567 Aug 23 10:06:33 PM UTC 24 Aug 23 10:06:52 PM UTC 24 422036691 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.3279522880 Aug 23 10:06:50 PM UTC 24 Aug 23 10:06:53 PM UTC 24 57249282 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2127682702 Aug 23 10:06:50 PM UTC 24 Aug 23 10:06:54 PM UTC 24 110891634 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.3072903700 Aug 23 10:06:54 PM UTC 24 Aug 23 10:06:56 PM UTC 24 52632103 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.2254330241 Aug 23 10:05:56 PM UTC 24 Aug 23 10:06:56 PM UTC 24 2583089565 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.4089679731 Aug 23 10:06:04 PM UTC 24 Aug 23 10:06:59 PM UTC 24 4461194791 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.4290784068 Aug 23 10:06:37 PM UTC 24 Aug 23 10:07:01 PM UTC 24 1060435071 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.4000745375 Aug 23 10:06:53 PM UTC 24 Aug 23 10:07:01 PM UTC 24 262887153 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.2116737222 Aug 23 10:06:52 PM UTC 24 Aug 23 10:07:02 PM UTC 24 3254237107 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.1124356960 Aug 23 10:06:51 PM UTC 24 Aug 23 10:07:02 PM UTC 24 785309361 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2154477593 Aug 23 10:05:57 PM UTC 24 Aug 23 10:07:07 PM UTC 24 5689924755 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.613515855 Aug 23 10:07:00 PM UTC 24 Aug 23 10:07:07 PM UTC 24 318818237 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2859958936 Aug 23 10:06:56 PM UTC 24 Aug 23 10:07:08 PM UTC 24 445886616 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.636705437 Aug 23 10:07:03 PM UTC 24 Aug 23 10:07:08 PM UTC 24 613709602 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.1197697798 Aug 23 10:07:00 PM UTC 24 Aug 23 10:07:09 PM UTC 24 2074836637 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.2100779223 Aug 23 10:07:02 PM UTC 24 Aug 23 10:07:09 PM UTC 24 2149463879 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.2355199916 Aug 23 10:06:48 PM UTC 24 Aug 23 10:07:15 PM UTC 24 204797160 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1645262805 Aug 23 10:07:08 PM UTC 24 Aug 23 10:07:16 PM UTC 24 680984975 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.3898202379 Aug 23 10:07:15 PM UTC 24 Aug 23 10:07:17 PM UTC 24 28495512 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.3957210835 Aug 23 10:07:08 PM UTC 24 Aug 23 10:07:19 PM UTC 24 527730166 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1966116486 Aug 23 10:07:18 PM UTC 24 Aug 23 10:07:19 PM UTC 24 20946154 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.141157932 Aug 23 10:07:09 PM UTC 24 Aug 23 10:07:20 PM UTC 24 1190418310 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.4091816772 Aug 23 10:07:17 PM UTC 24 Aug 23 10:07:21 PM UTC 24 225326997 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1810838625 Aug 23 10:07:20 PM UTC 24 Aug 23 10:07:23 PM UTC 24 83071892 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.3770508498 Aug 23 10:07:21 PM UTC 24 Aug 23 10:07:23 PM UTC 24 20937559 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.852570878 Aug 23 10:07:03 PM UTC 24 Aug 23 10:07:24 PM UTC 24 3326476745 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.1274107278 Aug 23 10:06:43 PM UTC 24 Aug 23 10:07:25 PM UTC 24 911851153 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.2302695180 Aug 23 10:07:25 PM UTC 24 Aug 23 10:07:27 PM UTC 24 33480828 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1789167746 Aug 23 10:07:24 PM UTC 24 Aug 23 10:07:31 PM UTC 24 3379068870 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.341683727 Aug 23 10:07:22 PM UTC 24 Aug 23 10:07:32 PM UTC 24 537008239 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.393999544 Aug 23 10:06:58 PM UTC 24 Aug 23 10:07:37 PM UTC 24 2207315902 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.1865321351 Aug 23 10:07:24 PM UTC 24 Aug 23 10:07:39 PM UTC 24 1881310927 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.45004279 Aug 23 10:07:26 PM UTC 24 Aug 23 10:07:40 PM UTC 24 477472089 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.4084948432 Aug 23 10:07:33 PM UTC 24 Aug 23 10:07:41 PM UTC 24 366002723 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.24008531 Aug 23 10:07:32 PM UTC 24 Aug 23 10:07:44 PM UTC 24 2181964669 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.3333957831 Aug 23 10:07:40 PM UTC 24 Aug 23 10:07:44 PM UTC 24 170922972 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.949937838 Aug 23 10:07:39 PM UTC 24 Aug 23 10:07:46 PM UTC 24 454443135 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.3788784378 Aug 23 10:07:02 PM UTC 24 Aug 23 10:07:48 PM UTC 24 1734215582 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.1221437716 Aug 23 10:07:10 PM UTC 24 Aug 23 10:07:51 PM UTC 24 469710043 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.3691534009 Aug 23 10:06:22 PM UTC 24 Aug 23 10:07:52 PM UTC 24 5922238569 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2546877163 Aug 23 10:07:20 PM UTC 24 Aug 23 10:07:55 PM UTC 24 384722365 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3286254913 Aug 23 10:07:45 PM UTC 24 Aug 23 10:07:57 PM UTC 24 641072221 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.20195912 Aug 23 10:07:48 PM UTC 24 Aug 23 10:07:58 PM UTC 24 1390129793 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.2509805061 Aug 23 10:07:56 PM UTC 24 Aug 23 10:07:58 PM UTC 24 82871456 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1201346736 Aug 23 10:07:42 PM UTC 24 Aug 23 10:07:59 PM UTC 24 4556694502 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3566169508 Aug 23 10:09:13 PM UTC 24 Aug 23 10:09:29 PM UTC 24 1950313588 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1097388967 Aug 23 10:07:58 PM UTC 24 Aug 23 10:08:00 PM UTC 24 53455405 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.3687735702 Aug 23 10:07:57 PM UTC 24 Aug 23 10:08:00 PM UTC 24 76421574 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.3675377565 Aug 23 10:07:45 PM UTC 24 Aug 23 10:08:01 PM UTC 24 383750625 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.3100422911 Aug 23 10:08:00 PM UTC 24 Aug 23 10:08:04 PM UTC 24 278927397 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.3271187198 Aug 23 10:08:05 PM UTC 24 Aug 23 10:08:07 PM UTC 24 13582842 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.50278749 Aug 23 10:07:59 PM UTC 24 Aug 23 10:08:07 PM UTC 24 76691778 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.273675916 Aug 23 10:08:01 PM UTC 24 Aug 23 10:08:10 PM UTC 24 247372054 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.107057612 Aug 23 10:08:02 PM UTC 24 Aug 23 10:08:11 PM UTC 24 607735809 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.2806993447 Aug 23 10:08:08 PM UTC 24 Aug 23 10:08:14 PM UTC 24 197742837 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3664461901 Aug 23 10:06:05 PM UTC 24 Aug 23 10:08:15 PM UTC 24 3236398439 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.3860130556 Aug 23 10:08:02 PM UTC 24 Aug 23 10:08:15 PM UTC 24 242767017 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2793437777 Aug 23 10:07:58 PM UTC 24 Aug 23 10:08:18 PM UTC 24 171980193 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.2777726707 Aug 23 10:06:21 PM UTC 24 Aug 23 10:08:19 PM UTC 24 16676261308 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.2960568076 Aug 23 10:07:53 PM UTC 24 Aug 23 10:08:20 PM UTC 24 265171872 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.409819318 Aug 23 10:08:12 PM UTC 24 Aug 23 10:08:22 PM UTC 24 1228208494 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.3797194368 Aug 23 10:07:28 PM UTC 24 Aug 23 10:08:22 PM UTC 24 1491800253 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.242525820 Aug 23 10:08:15 PM UTC 24 Aug 23 10:08:24 PM UTC 24 1242503473 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.2818935266 Aug 23 10:08:25 PM UTC 24 Aug 23 10:08:27 PM UTC 24 26474258 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.621575436 Aug 23 10:08:11 PM UTC 24 Aug 23 10:08:27 PM UTC 24 391929098 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3864627497 Aug 23 10:08:15 PM UTC 24 Aug 23 10:08:30 PM UTC 24 1114173928 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3237483482 Aug 23 10:08:28 PM UTC 24 Aug 23 10:08:30 PM UTC 24 40495600 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.4265990995 Aug 23 10:08:20 PM UTC 24 Aug 23 10:08:30 PM UTC 24 284892071 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.2748182469 Aug 23 10:08:15 PM UTC 24 Aug 23 10:08:31 PM UTC 24 670109240 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.4158500697 Aug 23 10:08:28 PM UTC 24 Aug 23 10:08:32 PM UTC 24 227719089 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.1200805523 Aug 23 10:08:18 PM UTC 24 Aug 23 10:08:32 PM UTC 24 2293672254 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.173532025 Aug 23 10:08:31 PM UTC 24 Aug 23 10:08:34 PM UTC 24 62267960 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.1215851441 Aug 23 10:08:33 PM UTC 24 Aug 23 10:08:34 PM UTC 24 11335182 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.961662651 Aug 23 10:08:35 PM UTC 24 Aug 23 10:08:39 PM UTC 24 532817112 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.4014204753 Aug 23 10:08:33 PM UTC 24 Aug 23 10:08:40 PM UTC 24 163654143 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.1356345351 Aug 23 10:08:30 PM UTC 24 Aug 23 10:08:40 PM UTC 24 103336053 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.1086379555 Aug 23 10:08:20 PM UTC 24 Aug 23 10:08:41 PM UTC 24 4073534445 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.3261610345 Aug 23 10:08:23 PM UTC 24 Aug 23 10:08:44 PM UTC 24 639323552 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.1875876170 Aug 23 10:08:41 PM UTC 24 Aug 23 10:08:48 PM UTC 24 342078683 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.3304988917 Aug 23 10:08:31 PM UTC 24 Aug 23 10:08:48 PM UTC 24 6925641870 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.139563282 Aug 23 10:08:45 PM UTC 24 Aug 23 10:08:49 PM UTC 24 650538323 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.2628359588 Aug 23 10:08:33 PM UTC 24 Aug 23 10:08:51 PM UTC 24 1464987744 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.819798653 Aug 23 10:08:42 PM UTC 24 Aug 23 10:08:53 PM UTC 24 565378046 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1281682786 Aug 23 10:08:30 PM UTC 24 Aug 23 10:08:58 PM UTC 24 3593472477 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.1581798261 Aug 23 10:08:50 PM UTC 24 Aug 23 10:08:58 PM UTC 24 253888238 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.2819130126 Aug 23 10:08:49 PM UTC 24 Aug 23 10:09:00 PM UTC 24 1012662006 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.3084576845 Aug 23 10:08:58 PM UTC 24 Aug 23 10:09:00 PM UTC 24 19063565 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2060571556 Aug 23 10:08:59 PM UTC 24 Aug 23 10:09:01 PM UTC 24 13395269 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.4209601869 Aug 23 10:08:58 PM UTC 24 Aug 23 10:09:01 PM UTC 24 29472084 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.4256876485 Aug 23 10:08:40 PM UTC 24 Aug 23 10:09:04 PM UTC 24 2720319998 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.905866523 Aug 23 10:09:01 PM UTC 24 Aug 23 10:09:04 PM UTC 24 36752802 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.686693584 Aug 23 10:08:52 PM UTC 24 Aug 23 10:09:05 PM UTC 24 359448615 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.3076199895 Aug 23 10:07:38 PM UTC 24 Aug 23 10:09:07 PM UTC 24 3609993605 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2687322701 Aug 23 10:08:08 PM UTC 24 Aug 23 10:09:07 PM UTC 24 3182398441 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.69429530 Aug 23 10:09:05 PM UTC 24 Aug 23 10:09:07 PM UTC 24 10977854 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.3594925886 Aug 23 10:09:01 PM UTC 24 Aug 23 10:09:09 PM UTC 24 137774086 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.4140816050 Aug 23 10:08:48 PM UTC 24 Aug 23 10:09:09 PM UTC 24 2709360559 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.3680139288 Aug 23 10:07:09 PM UTC 24 Aug 23 10:09:10 PM UTC 24 6333854969 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.1840317924 Aug 23 10:08:41 PM UTC 24 Aug 23 10:09:11 PM UTC 24 3703613005 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.879002925 Aug 23 10:09:01 PM UTC 24 Aug 23 10:09:11 PM UTC 24 984316520 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.1435665756 Aug 23 10:09:10 PM UTC 24 Aug 23 10:09:13 PM UTC 24 51778795 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.2257445757 Aug 23 10:09:10 PM UTC 24 Aug 23 10:09:13 PM UTC 24 222127053 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.3866281983 Aug 23 10:09:05 PM UTC 24 Aug 23 10:09:13 PM UTC 24 725799301 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.4252546145 Aug 23 10:08:15 PM UTC 24 Aug 23 10:09:14 PM UTC 24 8766422250 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.4165434095 Aug 23 10:09:02 PM UTC 24 Aug 23 10:09:15 PM UTC 24 287710245 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.1432424542 Aug 23 10:09:23 PM UTC 24 Aug 23 10:09:29 PM UTC 24 1055747925 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.481530292 Aug 23 10:09:15 PM UTC 24 Aug 23 10:09:17 PM UTC 24 188977257 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.975944949 Aug 23 10:09:04 PM UTC 24 Aug 23 10:09:17 PM UTC 24 1043644994 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.1903506939 Aug 23 10:09:08 PM UTC 24 Aug 23 10:09:17 PM UTC 24 534677402 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1050316495 Aug 23 10:09:16 PM UTC 24 Aug 23 10:09:18 PM UTC 24 39992771 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.975285453 Aug 23 10:09:08 PM UTC 24 Aug 23 10:09:18 PM UTC 24 582108338 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.83592560 Aug 23 10:09:17 PM UTC 24 Aug 23 10:09:19 PM UTC 24 11677163 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.1358672269 Aug 23 10:09:12 PM UTC 24 Aug 23 10:09:20 PM UTC 24 259193924 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.3012947463 Aug 23 10:09:18 PM UTC 24 Aug 23 10:09:22 PM UTC 24 512710334 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3892037657 Aug 23 10:09:12 PM UTC 24 Aug 23 10:09:23 PM UTC 24 512356194 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1801641160 Aug 23 10:09:21 PM UTC 24 Aug 23 10:09:23 PM UTC 24 124239314 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.2765576584 Aug 23 10:09:18 PM UTC 24 Aug 23 10:09:26 PM UTC 24 80612971 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.2861567189 Aug 23 10:09:20 PM UTC 24 Aug 23 10:09:27 PM UTC 24 459911551 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.2647934460 Aug 23 10:09:19 PM UTC 24 Aug 23 10:09:28 PM UTC 24 547732908 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.3305636944 Aug 23 10:09:19 PM UTC 24 Aug 23 10:09:31 PM UTC 24 723943726 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1234831598 Aug 23 10:08:59 PM UTC 24 Aug 23 10:09:36 PM UTC 24 265244889 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3153835713 Aug 23 10:10:43 PM UTC 24 Aug 23 10:10:59 PM UTC 24 413435861 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1494083642 Aug 23 10:09:28 PM UTC 24 Aug 23 10:09:37 PM UTC 24 351168124 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.420778548 Aug 23 10:09:26 PM UTC 24 Aug 23 10:09:37 PM UTC 24 1634973818 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2918196526 Aug 23 10:09:11 PM UTC 24 Aug 23 10:09:38 PM UTC 24 4014744280 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.3388453304 Aug 23 10:09:31 PM UTC 24 Aug 23 10:09:38 PM UTC 24 533559534 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.3901269986 Aug 23 10:09:29 PM UTC 24 Aug 23 10:09:38 PM UTC 24 1564197571 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.2818002986 Aug 23 10:09:30 PM UTC 24 Aug 23 10:09:39 PM UTC 24 333725975 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.630535766 Aug 23 10:09:38 PM UTC 24 Aug 23 10:09:40 PM UTC 24 37451673 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3033403088 Aug 23 10:09:18 PM UTC 24 Aug 23 10:09:41 PM UTC 24 231767186 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.4111759879 Aug 23 10:09:39 PM UTC 24 Aug 23 10:09:41 PM UTC 24 11671949 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2224004009 Aug 23 10:09:30 PM UTC 24 Aug 23 10:09:43 PM UTC 24 671107929 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.1910681088 Aug 23 10:09:39 PM UTC 24 Aug 23 10:09:43 PM UTC 24 213153152 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.2549405655 Aug 23 10:09:40 PM UTC 24 Aug 23 10:09:45 PM UTC 24 101703753 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.268365034 Aug 23 10:09:44 PM UTC 24 Aug 23 10:09:46 PM UTC 24 11198415 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.587703866 Aug 23 10:09:36 PM UTC 24 Aug 23 10:09:47 PM UTC 24 1474621370 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.46510696 Aug 23 10:09:40 PM UTC 24 Aug 23 10:09:48 PM UTC 24 567230633 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.2116143320 Aug 23 10:09:41 PM UTC 24 Aug 23 10:09:48 PM UTC 24 1085711223 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.2772286368 Aug 23 10:09:41 PM UTC 24 Aug 23 10:09:51 PM UTC 24 1368872222 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.1529834594 Aug 23 10:09:24 PM UTC 24 Aug 23 10:09:51 PM UTC 24 1408872690 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.66368366 Aug 23 10:09:45 PM UTC 24 Aug 23 10:09:55 PM UTC 24 359453071 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.157827887 Aug 23 10:09:52 PM UTC 24 Aug 23 10:09:55 PM UTC 24 76731730 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.2397680356 Aug 23 10:09:07 PM UTC 24 Aug 23 10:09:56 PM UTC 24 4199925007 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.241830370 Aug 23 10:09:48 PM UTC 24 Aug 23 10:09:56 PM UTC 24 395000355 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.4095032857 Aug 23 10:09:52 PM UTC 24 Aug 23 10:10:01 PM UTC 24 1251165912 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.808226884 Aug 23 10:09:43 PM UTC 24 Aug 23 10:10:03 PM UTC 24 1542209365 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1016015393 Aug 23 10:10:04 PM UTC 24 Aug 23 10:10:05 PM UTC 24 128672239 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.139854367 Aug 23 10:09:57 PM UTC 24 Aug 23 10:10:06 PM UTC 24 1038388359 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.3210107321 Aug 23 10:09:08 PM UTC 24 Aug 23 10:10:06 PM UTC 24 8568778260 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.400114437 Aug 23 10:09:49 PM UTC 24 Aug 23 10:10:06 PM UTC 24 609975907 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.2245254265 Aug 23 10:09:57 PM UTC 24 Aug 23 10:10:08 PM UTC 24 281117171 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1264302385 Aug 23 10:10:07 PM UTC 24 Aug 23 10:10:09 PM UTC 24 22295018 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1559683182 Aug 23 10:09:56 PM UTC 24 Aug 23 10:10:09 PM UTC 24 1012300027 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.761667543 Aug 23 10:10:07 PM UTC 24 Aug 23 10:10:10 PM UTC 24 74492987 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.134112379 Aug 23 10:09:56 PM UTC 24 Aug 23 10:10:11 PM UTC 24 4023739344 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.2252124303 Aug 23 10:09:23 PM UTC 24 Aug 23 10:10:13 PM UTC 24 2167108776 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3698326895 Aug 23 10:10:11 PM UTC 24 Aug 23 10:10:13 PM UTC 24 16665047 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.2012925175 Aug 23 10:09:39 PM UTC 24 Aug 23 10:10:14 PM UTC 24 339816320 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.2964913179 Aug 23 10:10:09 PM UTC 24 Aug 23 10:10:14 PM UTC 24 96622208 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.306235625 Aug 23 10:10:07 PM UTC 24 Aug 23 10:10:18 PM UTC 24 335637423 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.2934661723 Aug 23 10:10:09 PM UTC 24 Aug 23 10:10:19 PM UTC 24 1303989056 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.2369199470 Aug 23 10:10:10 PM UTC 24 Aug 23 10:10:21 PM UTC 24 402651979 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.948283649 Aug 23 10:10:14 PM UTC 24 Aug 23 10:10:22 PM UTC 24 577199205 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.2581596494 Aug 23 10:10:10 PM UTC 24 Aug 23 10:10:23 PM UTC 24 1526147671 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.580636717 Aug 23 10:08:35 PM UTC 24 Aug 23 10:10:24 PM UTC 24 3914878726 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.3299050927 Aug 23 10:10:55 PM UTC 24 Aug 23 10:10:59 PM UTC 24 86721716 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.4120129988 Aug 23 10:10:15 PM UTC 24 Aug 23 10:10:27 PM UTC 24 2566509790 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.655955065 Aug 23 10:10:21 PM UTC 24 Aug 23 10:10:27 PM UTC 24 163880129 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.3585440908 Aug 23 10:09:13 PM UTC 24 Aug 23 10:10:31 PM UTC 24 15268077402 ps
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T338 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3866220727 Aug 23 10:09:47 PM UTC 24 Aug 23 10:10:33 PM UTC 24 36184716091 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.2015319581 Aug 23 10:10:07 PM UTC 24 Aug 23 10:10:34 PM UTC 24 741945305 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.3907264472 Aug 23 10:10:32 PM UTC 24 Aug 23 10:10:34 PM UTC 24 30551432 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2836387009 Aug 23 10:10:34 PM UTC 24 Aug 23 10:10:36 PM UTC 24 46063109 ps
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T343 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.1600436635 Aug 23 10:09:27 PM UTC 24 Aug 23 10:10:38 PM UTC 24 24534860791 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.2134869451 Aug 23 10:10:35 PM UTC 24 Aug 23 10:10:39 PM UTC 24 92399526 ps
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T348 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.449765558 Aug 23 10:10:15 PM UTC 24 Aug 23 10:10:41 PM UTC 24 1148423358 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.3084481160 Aug 23 10:10:14 PM UTC 24 Aug 23 10:10:43 PM UTC 24 965463139 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.2172789684 Aug 23 10:10:41 PM UTC 24 Aug 23 10:10:44 PM UTC 24 247742024 ps
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T352 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.3469346114 Aug 23 10:09:49 PM UTC 24 Aug 23 10:10:47 PM UTC 24 4068140290 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.803352072 Aug 23 10:10:42 PM UTC 24 Aug 23 10:10:49 PM UTC 24 567246012 ps
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T354 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2043156886 Aug 23 10:10:50 PM UTC 24 Aug 23 10:10:52 PM UTC 24 71855798 ps
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T363 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.3480576503 Aug 23 10:11:04 PM UTC 24 Aug 23 10:11:06 PM UTC 24 545468424 ps
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T365 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.3824701446 Aug 23 10:10:59 PM UTC 24 Aug 23 10:11:08 PM UTC 24 610513357 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.2560484281 Aug 23 10:10:55 PM UTC 24 Aug 23 10:11:10 PM UTC 24 425211470 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.1214836168 Aug 23 10:11:09 PM UTC 24 Aug 23 10:11:11 PM UTC 24 24840375 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.770400034 Aug 23 10:11:11 PM UTC 24 Aug 23 10:11:13 PM UTC 24 26043820 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.3080111713 Aug 23 10:11:07 PM UTC 24 Aug 23 10:11:14 PM UTC 24 293011621 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.184920749 Aug 23 10:11:04 PM UTC 24 Aug 23 10:11:14 PM UTC 24 1251446023 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3533633698 Aug 23 10:11:07 PM UTC 24 Aug 23 10:11:16 PM UTC 24 400833500 ps
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