Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56082932

1

T1

724

T2

1463

T3

1373

auto[1]

1082527

1

T4

98

T5

99

T6

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56095250

1

T1

724

T2

1463

T3

1373

auto[1]

1070209

1

T5

297

T6

396

T28

792

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5090489	1			T1	107		T2	126		T3	102
auto[IdleSt]	15840872	1			T1	617		T2	96		T3	1271
auto[ClkMuxSt]	28271	1			T2	1		T14	1		T16	1
auto[CntIncrSt]	28173	1			T2	1		T14	1		T16	1
auto[CntProgSt]	1224416	1			T2	23		T14	52		T16	375
auto[TransCheckSt]	22316	1			T2	1		T14	1		T16	1
auto[TokenHashSt]	15200148	1			T2	340		T14	14		T16	14
auto[FlashRmaSt]	28606	1			T20	16		T27	35		T23	4
auto[TokenCheck0St]	10102	1			T20	16		T27	13		T23	4
auto[TokenCheck1St]	7346	1			T20	16		T27	13		T23	4
auto[TransProgSt]	261008	1			T20	32		T27	26		T23	718
auto[PostTransSt]	8627575	1			T2	875		T14	736		T16	780
auto[ScrapSt]	145078	1			T27	37		T7	455		T31	22
auto[EscalateSt]	4283548	1			T4	387		T5	559		T6	1074
auto[InvalidSt]	6366314	1			T29	886		T54	451		T41	285

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1197	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6366314	1			T29	886		T54	451		T41	285
EscalateSt	4283548	1			T4	387		T5	559		T6	1074
ScrapSt	145078	1			T27	37		T7	455		T31	22
PostTransSt	8627575	1			T2	875		T14	736		T16	780
TransProgSt	261008	1			T20	32		T27	26		T23	718
TokenCheck1St	7346	1			T20	16		T27	13		T23	4
TokenCheck0St	10102	1			T20	16		T27	13		T23	4
FlashRmaSt	28606	1			T20	16		T27	35		T23	4
TokenHashSt	15200148	1			T2	340		T14	14		T16	14
TransCheckSt	22316	1			T2	1		T14	1		T16	1
CntProgSt	1224416	1			T2	23		T14	52		T16	375
CntIncrSt	28173	1			T2	1		T14	1		T16	1
ClkMuxSt	28271	1			T2	1		T14	1		T16	1
IdleSt	15840872	1			T1	617		T2	96		T3	1271
ResetSt	5090489	1			T1	107		T2	126		T3	102
arcs[ResetSt=>IdleSt]	40651	1			T1	1		T2	1		T3	1
arcs[IdleSt=>ScrapSt]	223	1			T27	1		T7	1		T31	1
arcs[IdleSt=>ClkMuxSt]	28211	1			T2	1		T14	1		T16	1
arcs[ClkMuxSt=>CntIncrSt]	28173	1			T2	1		T14	1		T16	1
arcs[CntIncrSt=>PostTransSt]	1283	1			T33	6		T21	10		T42	8
arcs[CntIncrSt=>CntProgSt]	26819	1			T2	1		T14	1		T16	1
arcs[CntProgSt=>PostTransSt]	3360	1			T4	1		T5	4		T6	8
arcs[CntProgSt=>TransCheckSt]	22316	1			T2	1		T14	1		T16	1
arcs[TransCheckSt=>PostTransSt]	3212	1			T25	27		T33	10		T59	35
arcs[TransCheckSt=>TokenHashSt]	19017	1			T2	1		T14	1		T16	1
arcs[TokenHashSt=>PostTransSt]	8155	1			T2	1		T14	1		T16	1
arcs[TokenHashSt=>FlashRmaSt]	10147	1			T20	16		T27	13		T23	4
arcs[FlashRmaSt=>TokenCheck0St]	10102	1			T20	16		T27	13		T23	4
arcs[TokenCheck0St=>PostTransSt]	2704	1			T25	11		T58	14		T33	9
arcs[TokenCheck0St=>TokenCheck1St]	7346	1			T20	16		T27	13		T23	4
arcs[TokenCheck1St=>PostTransSt]	621	1			T25	9		T59	8		T21	1
arcs[TransProgSt=>PostTransSt]	5826	1			T20	16		T27	13		T23	4
arcs[IdleSt=>EscalateSt]	157	1			T36	2		T77	5		T74	7
arcs[ClkMuxSt=>EscalateSt]	38	1			T74	5		T75	1		T76	1
arcs[CntIncrSt=>EscalateSt]	71	1			T34	2		T40	5		T77	1
arcs[CntProgSt=>EscalateSt]	1143	1			T36	1		T34	31		T40	7
arcs[TransCheckSt=>EscalateSt]	87	1			T36	4		T40	4		T79	5
arcs[TokenHashSt=>EscalateSt]	715	1			T36	20		T34	15		T40	40
arcs[FlashRmaSt=>EscalateSt]	45	1			T77	1		T74	2		T75	3
arcs[TokenCheck0St=>EscalateSt]	52	1			T36	1		T34	1		T77	2
arcs[TokenCheck1St=>EscalateSt]	42	1			T34	3		T40	1		T74	1
arcs[TransProgSt=>EscalateSt]	857	1			T36	6		T34	12		T40	5
arcs[PostTransSt=>EscalateSt]	3650	1			T4	1		T5	4		T6	8
arcs[InvalidSt=>EscalateSt]	8936	1			T29	5		T54	3		T41	2

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5090336	1			T1	107		T2	126		T3	102
auto[0]	auto[IdleSt]	15840766	1			T1	617		T2	96		T3	1271
auto[0]	auto[ClkMuxSt]	28245	1			T2	1		T14	1		T16	1
auto[0]	auto[CntIncrSt]	28126	1			T2	1		T14	1		T16	1
auto[0]	auto[CntProgSt]	1223655	1			T2	23		T14	52		T16	375
auto[0]	auto[TransCheckSt]	22263	1			T2	1		T14	1		T16	1
auto[0]	auto[TokenHashSt]	15199671	1			T2	340		T14	14		T16	14
auto[0]	auto[FlashRmaSt]	28577	1			T20	16		T27	35		T23	4
auto[0]	auto[TokenCheck0St]	10067	1			T20	16		T27	13		T23	4
auto[0]	auto[TokenCheck1St]	7320	1			T20	16		T27	13		T23	4
auto[0]	auto[TransProgSt]	260417	1			T20	32		T27	26		T23	718
auto[0]	auto[PostTransSt]	8625647	1			T2	875		T14	736		T16	780
auto[0]	auto[ScrapSt]	145039	1			T27	37		T7	455		T31	22
auto[0]	auto[EscalateSt]	3209758	1			T4	290		T5	461		T6	682
auto[0]	auto[InvalidSt]	6361848	1			T29	886		T54	450		T41	284
auto[1]	auto[ResetSt]	153	1			T36	6		T34	2		T40	4
auto[1]	auto[IdleSt]	106	1			T77	3		T74	7		T79	2
auto[1]	auto[ClkMuxSt]	26	1			T74	3		T75	1		T195	3
auto[1]	auto[CntIncrSt]	47	1			T34	1		T40	3		T74	1
auto[1]	auto[CntProgSt]	761	1			T36	1		T34	20		T40	5
auto[1]	auto[TransCheckSt]	53	1			T36	1		T40	3		T79	3
auto[1]	auto[TokenHashSt]	477	1			T36	17		T34	11		T40	31
auto[1]	auto[FlashRmaSt]	29	1			T75	2		T259	1		T190	2
auto[1]	auto[TokenCheck0St]	35	1			T36	1		T34	1		T77	2
auto[1]	auto[TokenCheck1St]	26	1			T34	2		T79	1		T75	2
auto[1]	auto[TransProgSt]	591	1			T36	5		T34	9		T40	3
auto[1]	auto[PostTransSt]	1928	1			T4	1		T5	1		T6	4
auto[1]	auto[ScrapSt]	39	1			T34	1		T40	1		T77	2
auto[1]	auto[EscalateSt]	1073790	1			T4	97		T5	98		T6	392
auto[1]	auto[InvalidSt]	4466	1			T54	1		T41	1		T37	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5090333	1			T1	107		T2	126		T3	102
auto[0]	auto[IdleSt]	15840770	1			T1	617		T2	96		T3	1271
auto[0]	auto[ClkMuxSt]	28248	1			T2	1		T14	1		T16	1
auto[0]	auto[CntIncrSt]	28123	1			T2	1		T14	1		T16	1
auto[0]	auto[CntProgSt]	1223641	1			T2	23		T14	52		T16	375
auto[0]	auto[TransCheckSt]	22256	1			T2	1		T14	1		T16	1
auto[0]	auto[TokenHashSt]	15199665	1			T2	340		T14	14		T16	14
auto[0]	auto[FlashRmaSt]	28572	1			T20	16		T27	35		T23	4
auto[0]	auto[TokenCheck0St]	10066	1			T20	16		T27	13		T23	4
auto[0]	auto[TokenCheck1St]	7313	1			T20	16		T27	13		T23	4
auto[0]	auto[TransProgSt]	260447	1			T20	32		T27	26		T23	718
auto[0]	auto[PostTransSt]	8625759	1			T2	875		T14	736		T16	780
auto[0]	auto[ScrapSt]	145021	1			T27	37		T7	455		T31	22
auto[0]	auto[EscalateSt]	3221995	1			T4	387		T5	265		T6	682
auto[0]	auto[InvalidSt]	6361844	1			T29	881		T54	449		T41	284
auto[1]	auto[ResetSt]	156	1			T36	3		T34	1		T40	4
auto[1]	auto[IdleSt]	102	1			T36	2		T77	3		T74	2
auto[1]	auto[ClkMuxSt]	23	1			T74	4		T75	1		T76	1
auto[1]	auto[CntIncrSt]	50	1			T34	2		T40	4		T77	1
auto[1]	auto[CntProgSt]	775	1			T36	1		T34	22		T40	4
auto[1]	auto[TransCheckSt]	60	1			T36	3		T40	3		T79	4
auto[1]	auto[TokenHashSt]	483	1			T36	12		T34	12		T40	24
auto[1]	auto[FlashRmaSt]	34	1			T77	1		T74	2		T75	2
auto[1]	auto[TokenCheck0St]	36	1			T34	1		T77	2		T259	1
auto[1]	auto[TokenCheck1St]	33	1			T34	2		T40	1		T74	1
auto[1]	auto[TransProgSt]	561	1			T36	4		T34	9		T40	4
auto[1]	auto[PostTransSt]	1816	1			T5	3		T6	4		T28	8
auto[1]	auto[ScrapSt]	57	1			T34	1		T40	1		T77	3
auto[1]	auto[EscalateSt]	1061553	1			T5	294		T6	392		T28	784
auto[1]	auto[InvalidSt]	4470	1			T29	5		T54	2		T41	1