Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.00 97.92 95.84 93.40 97.62 98.52 99.25 96.47


Total tests in report: 999
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
45.48 45.48 74.18 74.18 39.56 39.56 16.56 16.56 23.81 23.81 58.26 58.26 90.30 90.30 15.72 15.72 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.4235671488
64.57 19.09 84.42 10.25 69.59 30.04 64.13 47.57 40.48 16.67 74.58 16.31 93.53 3.23 25.27 9.54 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.3843295830
71.36 6.79 87.47 3.04 75.14 5.55 81.01 16.88 40.48 0.00 79.87 5.30 94.03 0.50 41.52 16.25 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.2420166048
76.83 5.47 88.43 0.96 76.34 1.20 81.14 0.13 64.29 23.81 83.90 4.03 94.03 0.00 49.65 8.13 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2305264605
81.18 4.35 95.23 6.80 77.17 0.83 81.56 0.41 73.81 9.52 86.65 2.75 94.28 0.25 59.54 9.89 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.374374357
83.50 2.32 95.59 0.36 79.21 2.03 82.34 0.78 78.57 4.76 90.89 4.24 94.28 0.00 63.60 4.06 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1767954016
85.22 1.73 95.79 0.20 81.89 2.68 83.60 1.27 78.57 0.00 92.58 1.69 94.53 0.25 69.61 6.01 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3835307199
86.63 1.40 95.89 0.10 83.64 1.76 85.73 2.13 78.57 0.00 93.01 0.42 95.52 1.00 74.03 4.42 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.605713378
87.90 1.27 95.89 0.00 83.64 0.00 85.73 0.00 85.71 7.14 93.01 0.00 95.52 0.00 75.80 1.77 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.66489138
88.97 1.07 95.99 0.10 84.47 0.83 85.78 0.05 88.10 2.38 93.43 0.42 95.52 0.00 79.51 3.71 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2532005212
89.96 0.99 96.35 0.36 87.15 2.68 85.88 0.10 88.10 0.00 93.64 0.21 96.27 0.75 82.33 2.83 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.4162720495
90.89 0.93 96.60 0.25 89.09 1.94 85.94 0.06 88.10 0.00 94.28 0.64 96.52 0.25 85.69 3.36 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.509841089
91.76 0.87 97.21 0.61 89.19 0.09 86.86 0.92 88.10 0.00 96.61 2.33 96.52 0.00 87.81 2.12 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.4293389633
92.45 0.69 97.26 0.05 89.28 0.09 89.09 2.23 88.10 0.00 96.61 0.00 96.52 0.00 90.28 2.47 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.102752663
93.08 0.63 97.31 0.05 89.93 0.65 89.25 0.16 90.48 2.38 96.82 0.21 96.77 0.25 90.99 0.71 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3062244770
93.49 0.42 97.31 0.00 89.93 0.00 89.25 0.00 92.86 2.38 96.82 0.00 96.77 0.00 91.52 0.53 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.3095236484
93.90 0.41 97.31 0.00 90.20 0.28 89.25 0.00 95.24 2.38 97.03 0.21 96.77 0.00 91.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.3377105888
94.26 0.35 97.36 0.05 91.50 1.29 89.25 0.00 95.24 0.00 97.46 0.42 96.77 0.00 92.23 0.71 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4263424058
94.60 0.34 97.36 0.00 91.50 0.00 89.25 0.00 97.62 2.38 97.46 0.00 96.77 0.00 92.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.931785268
94.92 0.32 97.72 0.36 92.42 0.92 89.68 0.43 97.62 0.00 97.46 0.00 96.77 0.00 92.76 0.53 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.859636960
95.21 0.29 97.72 0.00 92.42 0.00 91.01 1.34 97.62 0.00 97.46 0.00 96.77 0.00 93.46 0.71 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1653392182
95.46 0.25 97.72 0.00 92.42 0.00 91.01 0.00 97.62 0.00 97.46 0.00 98.51 1.74 93.46 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3790396751
95.65 0.19 97.72 0.00 92.42 0.00 92.35 1.34 97.62 0.00 97.46 0.00 98.51 0.00 93.46 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.4050046385
95.81 0.16 97.72 0.00 92.51 0.09 92.44 0.09 97.62 0.00 97.67 0.21 98.51 0.00 94.17 0.71 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.297837383
95.91 0.10 97.82 0.10 92.51 0.00 92.44 0.00 97.62 0.00 98.09 0.42 98.51 0.00 94.35 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.1532325414
96.00 0.09 97.82 0.00 93.16 0.65 92.44 0.00 97.62 0.00 98.09 0.00 98.51 0.00 94.35 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2999833494
96.09 0.09 97.82 0.00 93.44 0.28 92.44 0.00 97.62 0.00 98.09 0.00 98.51 0.00 94.70 0.35 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.12936716
96.17 0.08 97.82 0.00 93.44 0.00 93.03 0.59 97.62 0.00 98.09 0.00 98.51 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.329237397
96.25 0.08 97.82 0.00 93.53 0.09 93.03 0.00 97.62 0.00 98.31 0.21 98.76 0.25 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.641165869
96.32 0.07 97.82 0.00 93.99 0.46 93.03 0.00 97.62 0.00 98.31 0.00 98.76 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3363941748
96.38 0.06 97.82 0.00 93.99 0.00 93.13 0.10 97.62 0.00 98.31 0.00 98.76 0.00 95.05 0.35 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.211084564
96.44 0.06 97.92 0.10 94.09 0.09 93.13 0.00 97.62 0.00 98.52 0.21 98.76 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.490796185
96.48 0.04 97.92 0.00 94.36 0.28 93.13 0.00 97.62 0.00 98.52 0.00 98.76 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3574026096
96.52 0.04 97.92 0.00 94.64 0.28 93.13 0.00 97.62 0.00 98.52 0.00 98.76 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.747352965
96.56 0.04 97.92 0.00 94.92 0.28 93.13 0.00 97.62 0.00 98.52 0.00 98.76 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2246131063
96.60 0.04 97.92 0.00 94.92 0.00 93.22 0.09 97.62 0.00 98.52 0.00 98.76 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3612809075
96.63 0.04 97.92 0.00 94.92 0.00 93.22 0.00 97.62 0.00 98.52 0.00 99.00 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.200153499
96.67 0.04 97.92 0.00 94.92 0.00 93.22 0.00 97.62 0.00 98.52 0.00 99.25 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.3786820704
96.70 0.03 97.92 0.00 94.92 0.00 93.24 0.02 97.62 0.00 98.52 0.00 99.25 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.579335778
96.72 0.03 97.92 0.00 94.92 0.00 93.26 0.02 97.62 0.00 98.52 0.00 99.25 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.4021791940
96.75 0.03 97.92 0.00 94.92 0.00 93.27 0.01 97.62 0.00 98.52 0.00 99.25 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3944083940
96.78 0.03 97.92 0.00 94.92 0.00 93.28 0.01 97.62 0.00 98.52 0.00 99.25 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.2145497412
96.80 0.03 97.92 0.00 95.10 0.18 93.28 0.00 97.62 0.00 98.52 0.00 99.25 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2106585809
96.83 0.03 97.92 0.00 95.29 0.18 93.28 0.00 97.62 0.00 98.52 0.00 99.25 0.00 95.94 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2497540772
96.86 0.03 97.92 0.00 95.29 0.00 93.28 0.00 97.62 0.00 98.52 0.00 99.25 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3598902793
96.88 0.03 97.92 0.00 95.29 0.00 93.28 0.00 97.62 0.00 98.52 0.00 99.25 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.3847331538
96.91 0.03 97.92 0.00 95.29 0.00 93.28 0.00 97.62 0.00 98.52 0.00 99.25 0.00 96.47 0.18 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.350039121
96.92 0.01 97.92 0.00 95.29 0.00 93.38 0.10 97.62 0.00 98.52 0.00 99.25 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.80861067
96.93 0.01 97.92 0.00 95.38 0.09 93.38 0.00 97.62 0.00 98.52 0.00 99.25 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.759988912
96.95 0.01 97.92 0.00 95.47 0.09 93.38 0.00 97.62 0.00 98.52 0.00 99.25 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3331664018
96.96 0.01 97.92 0.00 95.56 0.09 93.38 0.00 97.62 0.00 98.52 0.00 99.25 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2159634325
96.97 0.01 97.92 0.00 95.66 0.09 93.38 0.00 97.62 0.00 98.52 0.00 99.25 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.153378289
96.99 0.01 97.92 0.00 95.75 0.09 93.38 0.00 97.62 0.00 98.52 0.00 99.25 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.2984950771
97.00 0.01 97.92 0.00 95.84 0.09 93.38 0.00 97.62 0.00 98.52 0.00 99.25 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.2429938394
97.00 0.01 97.92 0.00 95.84 0.00 93.40 0.02 97.62 0.00 98.52 0.00 99.25 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1452604597

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1838320061
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4015621906
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3153229152
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2522294580
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3298978674
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3224294643
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.181357969
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2078558895
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.858314431
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1257524574
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4103599705
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3695529716
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.492336885
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3986510217
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.4294416271
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2807796713
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3850342828
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.866817880
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4156674840
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3167017827
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1275695362
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.147162048
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3156801928
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.11515358
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3527475483
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2183583914
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3647264881
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1189494755
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1812296649
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Total test records in report: 999
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.142150555 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:17 PM UTC 24 36247814 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.219922837 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:17 PM UTC 24 63646057 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.579335778 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:17 PM UTC 24 14334159 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.3612809075 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:17 PM UTC 24 45305104 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2426437644 Aug 24 08:41:13 PM UTC 24 Aug 24 08:41:17 PM UTC 24 38074119 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.831793301 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:18 PM UTC 24 19783441 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.4235671488 Aug 24 08:41:13 PM UTC 24 Aug 24 08:41:18 PM UTC 24 26129740 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.817278516 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:18 PM UTC 24 14546478 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.348326837 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:18 PM UTC 24 15234971 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3598902793 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:18 PM UTC 24 10917616 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.859636960 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:18 PM UTC 24 24804402 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.4293389633 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:18 PM UTC 24 51858898 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.627498813 Aug 24 08:41:13 PM UTC 24 Aug 24 08:41:18 PM UTC 24 216379758 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.2771256342 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:19 PM UTC 24 168453594 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.2420166048 Aug 24 08:41:13 PM UTC 24 Aug 24 08:41:19 PM UTC 24 228021558 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.1218809189 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:19 PM UTC 24 51342502 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3508912587 Aug 24 08:41:18 PM UTC 24 Aug 24 08:41:21 PM UTC 24 27560403 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.3763019348 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:21 PM UTC 24 80406237 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.999472609 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:21 PM UTC 24 110042417 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.3806839546 Aug 24 08:41:18 PM UTC 24 Aug 24 08:41:21 PM UTC 24 15572877 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3835307199 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:21 PM UTC 24 102596975 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.2465361986 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:21 PM UTC 24 220513446 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2312300450 Aug 24 08:41:19 PM UTC 24 Aug 24 08:41:22 PM UTC 24 42571846 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.211084564 Aug 24 08:41:18 PM UTC 24 Aug 24 08:41:22 PM UTC 24 31155030 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.3843295830 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:23 PM UTC 24 641966618 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.1290023572 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:23 PM UTC 24 144797214 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1767954016 Aug 24 08:41:13 PM UTC 24 Aug 24 08:41:23 PM UTC 24 3125736570 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.4162720495 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:23 PM UTC 24 295501515 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1375738336 Aug 24 08:41:18 PM UTC 24 Aug 24 08:41:23 PM UTC 24 215974121 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3944083940 Aug 24 08:41:13 PM UTC 24 Aug 24 08:41:24 PM UTC 24 135394111 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.2600908090 Aug 24 08:41:18 PM UTC 24 Aug 24 08:41:24 PM UTC 24 136856532 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.2779674548 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:24 PM UTC 24 481528004 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.4021791940 Aug 24 08:41:13 PM UTC 24 Aug 24 08:41:25 PM UTC 24 1716742509 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1452604597 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:26 PM UTC 24 1653599984 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.2633702955 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:26 PM UTC 24 649358389 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.3827184129 Aug 24 08:41:13 PM UTC 24 Aug 24 08:41:26 PM UTC 24 1227878878 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.845184054 Aug 24 08:41:24 PM UTC 24 Aug 24 08:41:26 PM UTC 24 22386853 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2458238108 Aug 24 08:41:24 PM UTC 24 Aug 24 08:41:26 PM UTC 24 19665243 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2663858646 Aug 24 08:41:27 PM UTC 24 Aug 24 08:41:31 PM UTC 24 55230907 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.616477812 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:31 PM UTC 24 3879839141 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.3099229287 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:27 PM UTC 24 1040727762 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.1346869238 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:27 PM UTC 24 415064694 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.623298386 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:27 PM UTC 24 165754972 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.2145497412 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:27 PM UTC 24 1232913016 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.2305264605 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:27 PM UTC 24 771268965 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.374374357 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:27 PM UTC 24 786741238 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3968055664 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:28 PM UTC 24 1097206840 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2532005212 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:28 PM UTC 24 496682764 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2982058018 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:28 PM UTC 24 939842292 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.219494074 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:28 PM UTC 24 2462874243 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.779130432 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:28 PM UTC 24 372450336 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.3605915099 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:28 PM UTC 24 1164618524 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.3160098349 Aug 24 08:41:13 PM UTC 24 Aug 24 08:41:29 PM UTC 24 300264671 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.3657271154 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:29 PM UTC 24 367074524 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.444254049 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:29 PM UTC 24 255004482 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.3370437100 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:29 PM UTC 24 317780442 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.1687905520 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:31 PM UTC 24 1019451682 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.7119632 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:29 PM UTC 24 438303602 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.1532325414 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:29 PM UTC 24 589905541 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.1667727868 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:29 PM UTC 24 324617087 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.2666177160 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:30 PM UTC 24 434935213 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.3847331538 Aug 24 08:41:27 PM UTC 24 Aug 24 08:41:30 PM UTC 24 12972998 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.297837383 Aug 24 08:41:13 PM UTC 24 Aug 24 08:41:30 PM UTC 24 929682804 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2990177129 Aug 24 08:41:25 PM UTC 24 Aug 24 08:41:30 PM UTC 24 81756940 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.4283069534 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:34 PM UTC 24 1151371526 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.2499929859 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:30 PM UTC 24 1068290810 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.82631967 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:30 PM UTC 24 641768869 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3138227054 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:31 PM UTC 24 248697534 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.3450227296 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:31 PM UTC 24 276248319 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.4923164 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:31 PM UTC 24 439515450 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.2780377482 Aug 24 08:41:24 PM UTC 24 Aug 24 08:41:32 PM UTC 24 411972703 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3684864678 Aug 24 08:41:13 PM UTC 24 Aug 24 08:41:33 PM UTC 24 446876187 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.1965410949 Aug 24 08:41:20 PM UTC 24 Aug 24 08:41:34 PM UTC 24 706314390 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.650365340 Aug 24 08:41:25 PM UTC 24 Aug 24 08:41:32 PM UTC 24 993087638 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.2390725371 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:33 PM UTC 24 800794902 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1098438055 Aug 24 08:41:30 PM UTC 24 Aug 24 08:41:33 PM UTC 24 15797193 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.3374025559 Aug 24 08:41:30 PM UTC 24 Aug 24 08:41:33 PM UTC 24 146509203 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.1383039952 Aug 24 08:41:30 PM UTC 24 Aug 24 08:41:33 PM UTC 24 44573887 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.3583505224 Aug 24 08:41:21 PM UTC 24 Aug 24 08:41:33 PM UTC 24 3358121294 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.1112301467 Aug 24 08:41:30 PM UTC 24 Aug 24 08:41:35 PM UTC 24 45733650 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.3056647080 Aug 24 08:41:13 PM UTC 24 Aug 24 08:41:34 PM UTC 24 718694995 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.3216206297 Aug 24 08:41:32 PM UTC 24 Aug 24 08:41:34 PM UTC 24 14980737 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.1388507901 Aug 24 08:41:19 PM UTC 24 Aug 24 08:41:35 PM UTC 24 7753726506 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.3325996602 Aug 24 08:41:28 PM UTC 24 Aug 24 08:41:35 PM UTC 24 136291731 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.1925617447 Aug 24 08:41:22 PM UTC 24 Aug 24 08:41:35 PM UTC 24 299842676 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1256461669 Aug 24 08:41:32 PM UTC 24 Aug 24 08:41:56 PM UTC 24 7480398577 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.309325049 Aug 24 08:41:21 PM UTC 24 Aug 24 08:41:36 PM UTC 24 432603019 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1686048989 Aug 24 08:41:34 PM UTC 24 Aug 24 08:41:37 PM UTC 24 13495419 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1971240045 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:37 PM UTC 24 1939828997 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.573675815 Aug 24 08:41:34 PM UTC 24 Aug 24 08:41:37 PM UTC 24 21609029 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1968386812 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:37 PM UTC 24 429155857 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.354757305 Aug 24 08:41:28 PM UTC 24 Aug 24 08:41:38 PM UTC 24 409013183 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.350039121 Aug 24 08:41:36 PM UTC 24 Aug 24 08:41:38 PM UTC 24 23085605 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2522217748 Aug 24 08:41:23 PM UTC 24 Aug 24 08:41:39 PM UTC 24 1925617006 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1355125949 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:39 PM UTC 24 6726839187 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.1240590999 Aug 24 08:41:19 PM UTC 24 Aug 24 08:41:39 PM UTC 24 333591149 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.2987505223 Aug 24 08:41:34 PM UTC 24 Aug 24 08:41:39 PM UTC 24 188653472 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.829395124 Aug 24 08:41:34 PM UTC 24 Aug 24 08:41:41 PM UTC 24 308300220 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.894330101 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:42 PM UTC 24 2746445010 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.122418309 Aug 24 08:41:30 PM UTC 24 Aug 24 08:41:42 PM UTC 24 52880191 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.639546709 Aug 24 08:41:20 PM UTC 24 Aug 24 08:41:42 PM UTC 24 1515546299 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.1997610352 Aug 24 08:41:40 PM UTC 24 Aug 24 08:41:43 PM UTC 24 33620460 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.892729432 Aug 24 08:41:34 PM UTC 24 Aug 24 08:41:43 PM UTC 24 418747571 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.4178580820 Aug 24 08:41:27 PM UTC 24 Aug 24 08:41:43 PM UTC 24 287106809 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.1436975498 Aug 24 08:41:26 PM UTC 24 Aug 24 08:41:43 PM UTC 24 1056592397 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.4221860736 Aug 24 08:41:40 PM UTC 24 Aug 24 08:41:43 PM UTC 24 25507141 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.2736287860 Aug 24 08:41:28 PM UTC 24 Aug 24 08:41:44 PM UTC 24 2207657437 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.501267292 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:44 PM UTC 24 4749372639 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.397964055 Aug 24 08:41:42 PM UTC 24 Aug 24 08:41:45 PM UTC 24 16522394 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.2657043323 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:45 PM UTC 24 1320638206 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1221265949 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:45 PM UTC 24 1438851952 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.4214231650 Aug 24 08:41:30 PM UTC 24 Aug 24 08:41:45 PM UTC 24 472040449 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.722465716 Aug 24 08:41:36 PM UTC 24 Aug 24 08:41:45 PM UTC 24 514990348 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.2805370251 Aug 24 08:41:30 PM UTC 24 Aug 24 08:41:45 PM UTC 24 390202118 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3132044847 Aug 24 08:41:32 PM UTC 24 Aug 24 08:41:45 PM UTC 24 341791523 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.535191435 Aug 24 08:41:38 PM UTC 24 Aug 24 08:41:46 PM UTC 24 179525863 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.874641838 Aug 24 08:41:38 PM UTC 24 Aug 24 08:41:46 PM UTC 24 614623711 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2764758417 Aug 24 08:41:44 PM UTC 24 Aug 24 08:41:46 PM UTC 24 15864588 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.1840555728 Aug 24 08:41:42 PM UTC 24 Aug 24 08:41:46 PM UTC 24 30412000 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.1962198437 Aug 24 08:41:32 PM UTC 24 Aug 24 08:41:47 PM UTC 24 710325397 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.2568997415 Aug 24 08:41:21 PM UTC 24 Aug 24 08:41:47 PM UTC 24 2761983332 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.3426066283 Aug 24 08:41:32 PM UTC 24 Aug 24 08:41:47 PM UTC 24 271050574 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.3112937118 Aug 24 08:41:37 PM UTC 24 Aug 24 08:41:47 PM UTC 24 551272915 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.102752663 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:47 PM UTC 24 322812714 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.3131684159 Aug 24 08:41:30 PM UTC 24 Aug 24 08:41:48 PM UTC 24 367846391 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.1759207164 Aug 24 08:41:53 PM UTC 24 Aug 24 08:41:57 PM UTC 24 50247142 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.3250536157 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:48 PM UTC 24 545128257 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1984324283 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:48 PM UTC 24 13045320468 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.3369234463 Aug 24 08:41:51 PM UTC 24 Aug 24 08:41:55 PM UTC 24 29528104 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.497844383 Aug 24 08:41:32 PM UTC 24 Aug 24 08:41:48 PM UTC 24 619354267 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1913468664 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:48 PM UTC 24 1469370160 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2942878478 Aug 24 08:41:19 PM UTC 24 Aug 24 08:41:48 PM UTC 24 384218971 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.4249005790 Aug 24 08:41:32 PM UTC 24 Aug 24 08:41:48 PM UTC 24 1959395277 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3155560094 Aug 24 08:41:30 PM UTC 24 Aug 24 08:41:49 PM UTC 24 350293863 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1259139838 Aug 24 08:41:44 PM UTC 24 Aug 24 08:41:49 PM UTC 24 175788747 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.4063840008 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:49 PM UTC 24 2822225759 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2440055119 Aug 24 08:41:39 PM UTC 24 Aug 24 08:41:50 PM UTC 24 482374326 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.2842737911 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:50 PM UTC 24 132251360 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.2995184895 Aug 24 08:41:35 PM UTC 24 Aug 24 08:41:50 PM UTC 24 558853198 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1388076000 Aug 24 08:41:47 PM UTC 24 Aug 24 08:41:50 PM UTC 24 12705476 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4087851457 Aug 24 08:41:47 PM UTC 24 Aug 24 08:41:50 PM UTC 24 64875062 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.1059877529 Aug 24 08:41:32 PM UTC 24 Aug 24 08:41:50 PM UTC 24 919619329 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.1596473287 Aug 24 08:41:46 PM UTC 24 Aug 24 08:41:50 PM UTC 24 221851396 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.588586263 Aug 24 08:41:46 PM UTC 24 Aug 24 08:41:50 PM UTC 24 430581254 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1580737091 Aug 24 08:41:28 PM UTC 24 Aug 24 08:41:51 PM UTC 24 370155387 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.1500078052 Aug 24 08:41:30 PM UTC 24 Aug 24 08:41:51 PM UTC 24 685386010 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.2928832565 Aug 24 08:41:49 PM UTC 24 Aug 24 08:41:51 PM UTC 24 19776891 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.2422183817 Aug 24 08:41:21 PM UTC 24 Aug 24 08:41:52 PM UTC 24 1159061581 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.639433000 Aug 24 08:41:42 PM UTC 24 Aug 24 08:41:52 PM UTC 24 222122265 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.1506769775 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:53 PM UTC 24 123088584 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.2710926364 Aug 24 08:41:47 PM UTC 24 Aug 24 08:41:53 PM UTC 24 55462004 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2895716137 Aug 24 08:41:18 PM UTC 24 Aug 24 08:41:53 PM UTC 24 274464231 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.2962040443 Aug 24 08:41:51 PM UTC 24 Aug 24 08:41:54 PM UTC 24 24891735 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3062244770 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:55 PM UTC 24 428508318 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.4243716341 Aug 24 08:41:30 PM UTC 24 Aug 24 08:41:53 PM UTC 24 868834257 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1227359849 Aug 24 08:41:21 PM UTC 24 Aug 24 08:41:54 PM UTC 24 19483702149 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2785326883 Aug 24 08:41:51 PM UTC 24 Aug 24 08:41:54 PM UTC 24 46207406 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.2459139721 Aug 24 08:41:49 PM UTC 24 Aug 24 08:41:54 PM UTC 24 78292010 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.344189058 Aug 24 08:41:18 PM UTC 24 Aug 24 08:41:56 PM UTC 24 221380860 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.1192006707 Aug 24 08:41:20 PM UTC 24 Aug 24 08:41:56 PM UTC 24 1096225932 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.4271685743 Aug 24 08:41:36 PM UTC 24 Aug 24 08:41:57 PM UTC 24 312625640 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.2616273974 Aug 24 08:41:32 PM UTC 24 Aug 24 08:41:57 PM UTC 24 866862272 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3259764634 Aug 24 08:41:27 PM UTC 24 Aug 24 08:41:57 PM UTC 24 352651096 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.4050046385 Aug 24 08:41:14 PM UTC 24 Aug 24 08:41:57 PM UTC 24 479267507 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.1310382041 Aug 24 08:41:34 PM UTC 24 Aug 24 08:41:58 PM UTC 24 369770067 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.3001709699 Aug 24 08:41:50 PM UTC 24 Aug 24 08:41:58 PM UTC 24 968231631 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.2872403498 Aug 24 08:41:39 PM UTC 24 Aug 24 08:41:58 PM UTC 24 1266317025 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.1260372114 Aug 24 08:41:54 PM UTC 24 Aug 24 08:41:58 PM UTC 24 108254272 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1514813783 Aug 24 08:41:49 PM UTC 24 Aug 24 08:41:58 PM UTC 24 745759841 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.270080340 Aug 24 08:41:50 PM UTC 24 Aug 24 08:41:59 PM UTC 24 391008021 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.3300561082 Aug 24 08:41:46 PM UTC 24 Aug 24 08:41:59 PM UTC 24 325582727 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.3350228128 Aug 24 08:41:39 PM UTC 24 Aug 24 08:41:59 PM UTC 24 1023478475 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2118959212 Aug 24 08:41:57 PM UTC 24 Aug 24 08:42:00 PM UTC 24 266107808 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.755820836 Aug 24 08:41:57 PM UTC 24 Aug 24 08:42:00 PM UTC 24 22521947 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.615522643 Aug 24 08:41:55 PM UTC 24 Aug 24 08:42:00 PM UTC 24 157603294 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.329237397 Aug 24 08:41:25 PM UTC 24 Aug 24 08:42:00 PM UTC 24 1750816628 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.2978931795 Aug 24 08:41:44 PM UTC 24 Aug 24 08:42:00 PM UTC 24 2093073967 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.1116307241 Aug 24 08:41:14 PM UTC 24 Aug 24 08:42:00 PM UTC 24 638402010 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.2406047121 Aug 24 08:41:49 PM UTC 24 Aug 24 08:42:00 PM UTC 24 249755019 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.3665174647 Aug 24 08:41:35 PM UTC 24 Aug 24 08:42:01 PM UTC 24 303455670 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.2990009609 Aug 24 08:41:49 PM UTC 24 Aug 24 08:42:01 PM UTC 24 577915034 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.3616386981 Aug 24 08:41:50 PM UTC 24 Aug 24 08:42:01 PM UTC 24 1406112632 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.1318704265 Aug 24 08:41:45 PM UTC 24 Aug 24 08:42:02 PM UTC 24 371257260 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.3554485934 Aug 24 08:41:30 PM UTC 24 Aug 24 08:42:02 PM UTC 24 997381599 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.193604681 Aug 24 08:41:44 PM UTC 24 Aug 24 08:42:03 PM UTC 24 1350390637 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.2796961434 Aug 24 08:42:15 PM UTC 24 Aug 24 08:42:20 PM UTC 24 146575274 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1888091755 Aug 24 08:41:38 PM UTC 24 Aug 24 08:42:03 PM UTC 24 2136360198 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.907633166 Aug 24 08:42:01 PM UTC 24 Aug 24 08:42:04 PM UTC 24 23042098 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.3987658403 Aug 24 08:42:01 PM UTC 24 Aug 24 08:42:04 PM UTC 24 89154239 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.2797517990 Aug 24 08:42:01 PM UTC 24 Aug 24 08:42:04 PM UTC 24 78771391 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.1952092178 Aug 24 08:41:57 PM UTC 24 Aug 24 08:42:04 PM UTC 24 142758121 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1692687969 Aug 24 08:41:46 PM UTC 24 Aug 24 08:42:04 PM UTC 24 845628870 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.4126510882 Aug 24 08:42:00 PM UTC 24 Aug 24 08:42:05 PM UTC 24 270544937 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.3254686643 Aug 24 08:41:50 PM UTC 24 Aug 24 08:42:05 PM UTC 24 1208786364 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.3768994560 Aug 24 08:41:55 PM UTC 24 Aug 24 08:42:05 PM UTC 24 901692875 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.841383497 Aug 24 08:41:59 PM UTC 24 Aug 24 08:42:06 PM UTC 24 105513382 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.3896906931 Aug 24 08:41:49 PM UTC 24 Aug 24 08:42:06 PM UTC 24 629144592 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.690520219 Aug 24 08:41:59 PM UTC 24 Aug 24 08:42:06 PM UTC 24 919263838 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1649386354 Aug 24 08:41:46 PM UTC 24 Aug 24 08:42:07 PM UTC 24 978958759 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.223669644 Aug 24 08:41:38 PM UTC 24 Aug 24 08:42:07 PM UTC 24 13823256191 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.2999500821 Aug 24 08:41:47 PM UTC 24 Aug 24 08:42:07 PM UTC 24 576410460 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.2521367138 Aug 24 08:42:04 PM UTC 24 Aug 24 08:42:07 PM UTC 24 26005010 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.4033275677 Aug 24 08:41:46 PM UTC 24 Aug 24 08:42:08 PM UTC 24 1509748810 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.2833995500 Aug 24 08:41:49 PM UTC 24 Aug 24 08:42:09 PM UTC 24 2220574441 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1255109640 Aug 24 08:41:50 PM UTC 24 Aug 24 08:42:09 PM UTC 24 2286497886 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.1637274381 Aug 24 08:41:50 PM UTC 24 Aug 24 08:42:09 PM UTC 24 344201554 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.1128825 Aug 24 08:41:44 PM UTC 24 Aug 24 08:42:09 PM UTC 24 2540037546 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.607948369 Aug 24 08:42:07 PM UTC 24 Aug 24 08:42:09 PM UTC 24 31869432 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.626925828 Aug 24 08:41:59 PM UTC 24 Aug 24 08:42:10 PM UTC 24 245777108 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.381266211 Aug 24 08:41:14 PM UTC 24 Aug 24 08:42:11 PM UTC 24 25603973887 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2278672905 Aug 24 08:42:08 PM UTC 24 Aug 24 08:42:11 PM UTC 24 42815745 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.3548311466 Aug 24 08:41:53 PM UTC 24 Aug 24 08:42:11 PM UTC 24 534490843 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1819205769 Aug 24 08:41:54 PM UTC 24 Aug 24 08:42:11 PM UTC 24 432425690 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.968408859 Aug 24 08:41:55 PM UTC 24 Aug 24 08:42:11 PM UTC 24 1510108890 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.1430319155 Aug 24 08:42:08 PM UTC 24 Aug 24 08:42:12 PM UTC 24 15306936 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.4163908736 Aug 24 08:42:08 PM UTC 24 Aug 24 08:42:12 PM UTC 24 43420227 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.443149549 Aug 24 08:41:54 PM UTC 24 Aug 24 08:42:12 PM UTC 24 858520091 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.2916403863 Aug 24 08:42:04 PM UTC 24 Aug 24 08:42:13 PM UTC 24 325963435 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.242137108 Aug 24 08:41:24 PM UTC 24 Aug 24 08:42:14 PM UTC 24 2464978039 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.66489138 Aug 24 08:41:54 PM UTC 24 Aug 24 08:42:14 PM UTC 24 455218607 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.378590959 Aug 24 08:41:34 PM UTC 24 Aug 24 08:42:19 PM UTC 24 345126624 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.16711511 Aug 24 08:41:59 PM UTC 24 Aug 24 08:42:14 PM UTC 24 265876822 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.1022095922 Aug 24 08:42:01 PM UTC 24 Aug 24 08:42:18 PM UTC 24 672943621 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.1313374881 Aug 24 08:42:15 PM UTC 24 Aug 24 08:42:21 PM UTC 24 152323275 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.3095236484 Aug 24 08:42:04 PM UTC 24 Aug 24 08:42:14 PM UTC 24 241367782 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.743117220 Aug 24 08:41:59 PM UTC 24 Aug 24 08:42:14 PM UTC 24 916671253 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.3396673600 Aug 24 08:41:56 PM UTC 24 Aug 24 08:42:15 PM UTC 24 2131142154 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.562925148 Aug 24 08:42:06 PM UTC 24 Aug 24 08:42:15 PM UTC 24 422094615 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.3787675082 Aug 24 08:42:04 PM UTC 24 Aug 24 08:42:15 PM UTC 24 805413388 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.2827833468 Aug 24 08:41:56 PM UTC 24 Aug 24 08:42:16 PM UTC 24 6357124315 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.358253943 Aug 24 08:42:11 PM UTC 24 Aug 24 08:42:16 PM UTC 24 275684532 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.3522184610 Aug 24 08:42:13 PM UTC 24 Aug 24 08:42:16 PM UTC 24 69571450 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.1562272847 Aug 24 08:42:06 PM UTC 24 Aug 24 08:42:19 PM UTC 24 1168589910 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2732680290 Aug 24 08:41:28 PM UTC 24 Aug 24 08:42:17 PM UTC 24 5956735596 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.968248004 Aug 24 08:42:15 PM UTC 24 Aug 24 08:42:17 PM UTC 24 20782047 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.774486346 Aug 24 08:41:50 PM UTC 24 Aug 24 08:42:18 PM UTC 24 2797632644 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.2757663149 Aug 24 08:42:02 PM UTC 24 Aug 24 08:42:18 PM UTC 24 257178561 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.2266165314 Aug 24 08:42:01 PM UTC 24 Aug 24 08:42:18 PM UTC 24 332211552 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.60271916 Aug 24 08:42:05 PM UTC 24 Aug 24 08:42:20 PM UTC 24 300766938 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.2827404084 Aug 24 08:42:08 PM UTC 24 Aug 24 08:42:21 PM UTC 24 818200936 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.769401132 Aug 24 08:41:59 PM UTC 24 Aug 24 08:42:21 PM UTC 24 1983897056 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.2062913713 Aug 24 08:42:12 PM UTC 24 Aug 24 08:42:21 PM UTC 24 1595242314 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.872719173 Aug 24 08:41:24 PM UTC 24 Aug 24 08:42:22 PM UTC 24 410528931 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.4031698789 Aug 24 08:42:10 PM UTC 24 Aug 24 08:42:22 PM UTC 24 1632848785 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.236316228 Aug 24 08:42:15 PM UTC 24 Aug 24 08:42:46 PM UTC 24 4106124669 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.3344260308 Aug 24 08:42:10 PM UTC 24 Aug 24 08:42:22 PM UTC 24 2042877270 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.1799274675 Aug 24 08:42:06 PM UTC 24 Aug 24 08:42:22 PM UTC 24 1491372751 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.4097743254 Aug 24 08:41:32 PM UTC 24 Aug 24 08:42:22 PM UTC 24 5905611355 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.4111322518 Aug 24 08:42:20 PM UTC 24 Aug 24 08:42:22 PM UTC 24 69798891 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.4120296790 Aug 24 08:41:36 PM UTC 24 Aug 24 08:42:22 PM UTC 24 948821156 ps