Group : alert_esc_agent_pkg::alert_esc_trans_cg
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Group : alert_esc_agent_pkg::alert_esc_trans_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
50.00 50.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_esc_agent_0/alert_esc_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
alert_esc_agent_pkg.m_esc_trans_cg 50.00 1 100 1 64 64
alert_esc_agent_pkg.m_esc_trans_cg_(1) 50.00 1 100 1 64 64




Group Instance : alert_esc_agent_pkg.m_esc_trans_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance alert_esc_agent_pkg.m_esc_trans_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance alert_esc_agent_pkg.m_esc_trans_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_handshake_complete 2 1 1 50.00 100 1 1 0



Group Instance : alert_esc_agent_pkg.m_esc_trans_cg_(1)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance alert_esc_agent_pkg.m_esc_trans_cg_(1)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance alert_esc_agent_pkg.m_esc_trans_cg_(1)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_handshake_complete 2 1 1 50.00 100 1 1 0


Summary for Variable cp_handshake_complete

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for cp_handshake_complete

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
ping_trans 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
alert_esc_trans 9377 1 T4 5 T21 6 T19 44


Summary for Variable cp_handshake_complete

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for cp_handshake_complete

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
ping_trans 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
alert_esc_trans 9169 1 T4 6 T5 4 T21 3

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