Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	730591	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

923341

1

T1

6

T2

2

T3

132

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1353866	1			T1	9		T2	2		T3	126
values[0x0]	149418	1			T1	2		T2	1		T3	45
values[0x1]	150648	1			T1	6		T3	40		T4	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	576838	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1077094

1

T1

9

T2

2

T3

150

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5206	1			T3	3		T4	2		T7	1
valid_sources[0x01]	8171	1			T3	2		T4	1		T5	2
valid_sources[0x02]	5192	1			T3	1		T15	2		T7	1
valid_sources[0x03]	57809	1			T1	1		T15	5		T7	2
valid_sources[0x04]	5565	1			T3	2		T4	2		T15	5
valid_sources[0x05]	5066	1			T15	5		T7	1		T21	1
valid_sources[0x06]	5472	1			T3	3		T15	7		T7	2
valid_sources[0x07]	5258	1			T15	5		T7	3		T21	1
valid_sources[0x08]	5461	1			T5	1		T15	7		T7	4
valid_sources[0x09]	5687	1			T4	1		T5	1		T15	1
valid_sources[0x0a]	6152	1			T15	2		T21	2		T19	4
valid_sources[0x0b]	5337	1			T15	4		T7	2		T19	8
valid_sources[0x0c]	5384	1			T15	3		T7	3		T21	1
valid_sources[0x0d]	5286	1			T4	3		T15	5		T7	1
valid_sources[0x0e]	6185	1			T3	3		T4	1		T15	8
valid_sources[0x0f]	6676	1			T5	6		T15	4		T7	1
valid_sources[0x10]	5257	1			T3	1		T4	3		T15	2
valid_sources[0x11]	5222	1			T4	1		T15	8		T7	1
valid_sources[0x12]	5408	1			T3	1		T4	1		T15	6
valid_sources[0x13]	5277	1			T1	1		T4	1		T15	4
valid_sources[0x14]	5367	1			T4	4		T15	9		T21	1
valid_sources[0x15]	5203	1			T5	1		T15	3		T7	2
valid_sources[0x16]	4933	1			T3	1		T15	3		T7	1
valid_sources[0x17]	6556	1			T3	1		T4	1		T15	4
valid_sources[0x18]	5320	1			T15	3		T7	1		T21	2
valid_sources[0x19]	5179	1			T3	4		T15	5		T7	1
valid_sources[0x1a]	8275	1			T15	2		T7	1		T21	1
valid_sources[0x1b]	5375	1			T3	1		T4	2		T15	9
valid_sources[0x1c]	5091	1			T15	8		T21	1		T19	9
valid_sources[0x1d]	5055	1			T3	5		T5	1		T15	5
valid_sources[0x1e]	4975	1			T4	2		T15	3		T7	1
valid_sources[0x1f]	6312	1			T15	6		T7	1		T21	3
valid_sources[0x20]	5262	1			T3	2		T15	8		T7	2
valid_sources[0x21]	5271	1			T15	1		T7	5		T21	1
valid_sources[0x22]	7010	1			T4	1		T15	7		T7	1
valid_sources[0x23]	5296	1			T15	4		T7	1		T19	5
valid_sources[0x24]	5773	1			T3	1		T15	7		T7	1
valid_sources[0x25]	5086	1			T15	5		T7	1		T19	3
valid_sources[0x26]	7206	1			T15	3		T7	1		T21	3
valid_sources[0x27]	4982	1			T5	3		T15	7		T7	3
valid_sources[0x28]	7161	1			T15	3		T7	1		T21	1
valid_sources[0x29]	5188	1			T3	1		T15	4		T21	1
valid_sources[0x2a]	5227	1			T15	8		T21	2		T19	2
valid_sources[0x2b]	5056	1			T1	2		T15	2		T7	1
valid_sources[0x2c]	5714	1			T3	2		T15	6		T7	1
valid_sources[0x2d]	5041	1			T1	1		T3	4		T4	5
valid_sources[0x2e]	5441	1			T3	1		T15	5		T21	1
valid_sources[0x2f]	5503	1			T3	1		T4	2		T15	9
valid_sources[0x30]	5075	1			T5	6		T15	4		T7	1
valid_sources[0x31]	5143	1			T3	4		T4	5		T7	3
valid_sources[0x32]	7145	1			T15	3		T7	1		T21	4
valid_sources[0x33]	4994	1			T3	3		T4	1		T5	1
valid_sources[0x34]	5171	1			T4	4		T15	4		T7	1
valid_sources[0x35]	14212	1			T15	1		T7	1		T21	1
valid_sources[0x36]	6573	1			T4	3		T15	3		T7	1
valid_sources[0x37]	5307	1			T3	2		T4	4		T15	2
valid_sources[0x38]	10589	1			T4	2		T15	1		T21	4
valid_sources[0x39]	5148	1			T3	1		T15	1		T7	1
valid_sources[0x3a]	8705	1			T3	1		T5	1		T15	1
valid_sources[0x3b]	8377	1			T4	2		T15	4		T7	1
valid_sources[0x3c]	5568	1			T4	2		T15	1		T21	2
valid_sources[0x3d]	5397	1			T5	2		T15	3		T7	3
valid_sources[0x3e]	7306	1			T1	4		T15	11		T21	2
valid_sources[0x3f]	7561	1			T15	5		T21	1		T19	2
valid_sources[0x40]	5894	1			T3	5		T15	7		T21	2
valid_sources[0x41]	10743	1			T4	1		T5	3		T15	3
valid_sources[0x42]	7153	1			T3	4		T4	2		T15	8
valid_sources[0x43]	5248	1			T1	1		T3	1		T15	5
valid_sources[0x44]	6231	1			T15	7		T21	6		T19	4
valid_sources[0x45]	7342	1			T4	1		T5	2		T15	5
valid_sources[0x46]	5425	1			T4	3		T15	1		T21	1
valid_sources[0x47]	7253	1			T15	1		T19	2		T20	7
valid_sources[0x48]	5491	1			T4	2		T15	5		T7	1
valid_sources[0x49]	10424	1			T3	3		T5	6		T15	3
valid_sources[0x4a]	5230	1			T4	1		T15	1		T21	1
valid_sources[0x4b]	5185	1			T15	1		T7	1		T19	6
valid_sources[0x4c]	5188	1			T3	1		T5	3		T14	3
valid_sources[0x4d]	6784	1			T3	4		T4	1		T5	1
valid_sources[0x4e]	5158	1			T4	2		T15	4		T7	2
valid_sources[0x4f]	5200	1			T4	5		T15	6		T21	1
valid_sources[0x50]	5549	1			T4	1		T15	4		T7	1
valid_sources[0x51]	5237	1			T15	2		T7	1		T21	1
valid_sources[0x52]	5042	1			T4	3		T15	3		T7	2
valid_sources[0x53]	5050	1			T1	1		T3	1		T15	5
valid_sources[0x54]	5160	1			T15	3		T21	3		T19	1
valid_sources[0x55]	5277	1			T15	1		T7	2		T19	4
valid_sources[0x56]	5639	1			T4	4		T15	3		T21	1
valid_sources[0x57]	5437	1			T3	1		T4	2		T15	4
valid_sources[0x58]	5147	1			T4	2		T13	189		T15	4
valid_sources[0x59]	5162	1			T3	2		T4	2		T15	3
valid_sources[0x5a]	6325	1			T4	1		T15	2		T21	3
valid_sources[0x5b]	5338	1			T3	1		T4	1		T15	3
valid_sources[0x5c]	7372	1			T15	4		T7	3		T21	1
valid_sources[0x5d]	5064	1			T3	2		T15	3		T21	1
valid_sources[0x5e]	12668	1			T3	1		T15	4		T7	2
valid_sources[0x5f]	5333	1			T15	2		T7	1		T21	3
valid_sources[0x60]	7811	1			T4	1		T15	3		T7	3
valid_sources[0x61]	5523	1			T15	1		T21	1		T19	9
valid_sources[0x62]	5567	1			T3	1		T4	1		T15	3
valid_sources[0x63]	5339	1			T3	1		T15	5		T7	2
valid_sources[0x64]	7188	1			T4	3		T15	5		T19	6
valid_sources[0x65]	5052	1			T3	1		T4	1		T15	5
valid_sources[0x66]	9759	1			T3	2		T4	1		T15	3
valid_sources[0x67]	6813	1			T3	1		T4	1		T15	1
valid_sources[0x68]	5286	1			T3	3		T4	2		T15	4
valid_sources[0x69]	11032	1			T4	2		T15	1		T7	3
valid_sources[0x6a]	6548	1			T3	1		T5	4		T15	4
valid_sources[0x6b]	5108	1			T15	3		T7	2		T21	3
valid_sources[0x6c]	7844	1			T4	3		T15	4		T21	1
valid_sources[0x6d]	5078	1			T3	2		T15	4		T7	2
valid_sources[0x6e]	5132	1			T15	2		T21	3		T19	4
valid_sources[0x6f]	5411	1			T5	3		T15	5		T19	7
valid_sources[0x70]	7660	1			T4	2		T7	1		T21	1
valid_sources[0x71]	5424	1			T3	1		T15	5		T7	1
valid_sources[0x72]	5681	1			T3	5		T4	1		T15	6
valid_sources[0x73]	5059	1			T3	5		T4	2		T5	1
valid_sources[0x74]	5106	1			T1	1		T15	2		T20	1
valid_sources[0x75]	5157	1			T2	3		T3	2		T4	3
valid_sources[0x76]	8974	1			T3	1		T4	2		T15	7
valid_sources[0x77]	5245	1			T15	1		T7	1		T21	3
valid_sources[0x78]	7000	1			T4	1		T15	6		T7	1
valid_sources[0x79]	5563	1			T4	1		T15	5		T19	6
valid_sources[0x7a]	5297	1			T3	1		T15	5		T7	4
valid_sources[0x7b]	5284	1			T4	1		T5	3		T15	1
valid_sources[0x7c]	20305	1			T3	2		T4	1		T15	8
valid_sources[0x7d]	5190	1			T4	7		T15	1		T7	1
valid_sources[0x7e]	6221	1			T15	4		T7	2		T19	3
valid_sources[0x7f]	5301	1			T15	6		T21	2		T19	14
valid_sources[0x80]	5229	1			T4	4		T5	3		T15	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

665039

1

T2

1

T3

61

T4

59

values[0x0]

all_enables

biggest_size

129611

1

T1

2

T2

1

T3

38

values[0x1]

all_enables

biggest_size

128691

1

T1

4

T3

33

T4

38