Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	59708902	16578	0	0
claim_transition_if_regwen_rd_A	59708902	2220	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59708902	16578	0	0
T46	114905	6	0	0
T56	28924	0	0	0
T70	47337	0	0	0
T71	75081	0	0	0
T86	318926	0	0	0
T88	0	7	0	0
T89	0	1	0	0
T92	0	9	0	0
T107	0	11	0	0
T115	0	3	0	0
T148	0	22	0	0
T149	0	3	0	0
T150	0	7	0	0
T151	0	1	0	0
T152	22980	0	0	0
T153	44600	0	0	0
T154	76931	0	0	0
T155	2040	0	0	0
T156	1280	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59708902	2220	0	0
T79	1716	0	0	0
T108	0	16	0	0
T112	0	26	0	0
T115	326782	8	0	0
T119	0	12	0	0
T142	0	6	0	0
T151	0	15	0	0
T157	0	5	0	0
T158	0	451	0	0
T159	0	282	0	0
T160	0	16	0	0
T161	30502	0	0	0
T162	337131	0	0	0
T163	16245	0	0	0
T164	1562	0	0	0
T165	1650	0	0	0
T166	5578	0	0	0
T167	3347	0	0	0
T168	6434	0	0	0