Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62940714

1

T1

1495

T2

1279

T3

4411

auto[1]

1143086

1

T4

495

T5

198

T15

10498

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62943862

1

T1

1495

T2

1279

T3

4411

auto[1]

1139938

1

T4

693

T5

297

T15

7521

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5428062	1			T1	112		T2	84		T3	1627
auto[IdleSt]	16010198	1			T1	103		T2	1195		T3	354
auto[ClkMuxSt]	28493	1			T1	1		T3	14		T4	12
auto[CntIncrSt]	28362	1			T1	1		T3	14		T4	12
auto[CntProgSt]	1154114	1			T1	30		T3	419		T4	24
auto[TransCheckSt]	22477	1			T1	1		T3	14		T5	7
auto[TokenHashSt]	19259526	1			T1	496		T3	367		T5	810
auto[FlashRmaSt]	28016	1			T3	42		T5	18		T6	15
auto[TokenCheck0St]	9896	1			T3	14		T5	7		T6	15
auto[TokenCheck1St]	7055	1			T3	14		T5	7		T6	15
auto[TransProgSt]	249565	1			T3	474		T5	14		T6	281
auto[PostTransSt]	8820535	1			T1	751		T3	1058		T4	988
auto[ScrapSt]	123344	1			T6	269		T15	4		T49	70
auto[EscalateSt]	4858154	1			T4	1667		T5	1225		T15	14212
auto[InvalidSt]	8054539	1			T5	706		T25	2801		T14	14010

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1464	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	8054539	1			T5	706		T25	2801		T14	14010
EscalateSt	4858154	1			T4	1667		T5	1225		T15	14212
ScrapSt	123344	1			T6	269		T15	4		T49	70
PostTransSt	8820535	1			T1	751		T3	1058		T4	988
TransProgSt	249565	1			T3	474		T5	14		T6	281
TokenCheck1St	7055	1			T3	14		T5	7		T6	15
TokenCheck0St	9896	1			T3	14		T5	7		T6	15
FlashRmaSt	28016	1			T3	42		T5	18		T6	15
TokenHashSt	19259526	1			T1	496		T3	367		T5	810
TransCheckSt	22477	1			T1	1		T3	14		T5	7
CntProgSt	1154114	1			T1	30		T3	419		T4	24
CntIncrSt	28362	1			T1	1		T3	14		T4	12
ClkMuxSt	28493	1			T1	1		T3	14		T4	12
IdleSt	16010198	1			T1	103		T2	1195		T3	354
ResetSt	5428062	1			T1	112		T2	84		T3	1627
arcs[ResetSt=>IdleSt]	42418	1			T1	1		T2	1		T3	14
arcs[IdleSt=>ScrapSt]	246	1			T6	1		T15	1		T49	2
arcs[IdleSt=>ClkMuxSt]	28390	1			T1	1		T3	14		T4	12
arcs[ClkMuxSt=>CntIncrSt]	28362	1			T1	1		T3	14		T4	12
arcs[CntIncrSt=>PostTransSt]	1306	1			T19	6		T21	6		T22	5
arcs[CntIncrSt=>CntProgSt]	26976	1			T1	1		T3	14		T4	12
arcs[CntProgSt=>PostTransSt]	3411	1			T4	12		T13	10		T19	10
arcs[CntProgSt=>TransCheckSt]	22477	1			T1	1		T3	14		T5	7
arcs[TransCheckSt=>PostTransSt]	3081	1			T19	13		T17	27		T21	7
arcs[TransCheckSt=>TokenHashSt]	19294	1			T1	1		T3	14		T5	7
arcs[TokenHashSt=>PostTransSt]	8521	1			T1	1		T19	31		T16	1
arcs[TokenHashSt=>FlashRmaSt]	9942	1			T3	14		T5	7		T6	15
arcs[FlashRmaSt=>TokenCheck0St]	9896	1			T3	14		T5	7		T6	15
arcs[TokenCheck0St=>PostTransSt]	2784	1			T19	14		T17	13		T25	19
arcs[TokenCheck0St=>TokenCheck1St]	7055	1			T3	14		T5	7		T6	15
arcs[TokenCheck1St=>PostTransSt]	590	1			T17	3		T21	1		T50	10
arcs[TransProgSt=>PostTransSt]	5642	1			T3	14		T5	7		T6	15
arcs[IdleSt=>EscalateSt]	142	1			T15	5		T68	2		T65	5
arcs[ClkMuxSt=>EscalateSt]	28	1			T15	1		T65	1		T66	1
arcs[CntIncrSt=>EscalateSt]	80	1			T15	4		T67	3		T68	2
arcs[CntProgSt=>EscalateSt]	1088	1			T15	19		T67	35		T68	26
arcs[TransCheckSt=>EscalateSt]	102	1			T67	2		T68	2		T65	3
arcs[TokenHashSt=>EscalateSt]	831	1			T15	7		T67	16		T68	6
arcs[FlashRmaSt=>EscalateSt]	46	1			T15	2		T67	1		T69	1
arcs[TokenCheck0St=>EscalateSt]	57	1			T15	1		T67	4		T68	1
arcs[TokenCheck1St=>EscalateSt]	27	1			T67	2		T68	1		T66	1
arcs[TransProgSt=>EscalateSt]	796	1			T15	21		T67	26		T68	10
arcs[PostTransSt=>EscalateSt]	3708	1			T4	12		T15	1		T13	10
arcs[InvalidSt=>EscalateSt]	10185	1			T5	5		T25	14		T14	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5427870	1			T1	112		T2	84		T3	1627
auto[0]	auto[IdleSt]	16010097	1			T1	103		T2	1195		T3	354
auto[0]	auto[ClkMuxSt]	28475	1			T1	1		T3	14		T4	12
auto[0]	auto[CntIncrSt]	28308	1			T1	1		T3	14		T4	12
auto[0]	auto[CntProgSt]	1153409	1			T1	30		T3	419		T4	24
auto[0]	auto[TransCheckSt]	22415	1			T1	1		T3	14		T5	7
auto[0]	auto[TokenHashSt]	19258969	1			T1	496		T3	367		T5	810
auto[0]	auto[FlashRmaSt]	27987	1			T3	42		T5	18		T6	15
auto[0]	auto[TokenCheck0St]	9860	1			T3	14		T5	7		T6	15
auto[0]	auto[TokenCheck1St]	7040	1			T3	14		T5	7		T6	15
auto[0]	auto[TransProgSt]	249022	1			T3	474		T5	14		T6	281
auto[0]	auto[PostTransSt]	8818639	1			T1	751		T3	1058		T4	983
auto[0]	auto[ScrapSt]	123311	1			T6	269		T15	3		T49	70
auto[0]	auto[EscalateSt]	3724448	1			T4	1177		T5	1029		T15	3766
auto[0]	auto[InvalidSt]	8049400	1			T5	704		T25	2795		T14	14007
auto[1]	auto[ResetSt]	192	1			T15	7		T67	4		T68	2
auto[1]	auto[IdleSt]	101	1			T15	5		T68	2		T65	3
auto[1]	auto[ClkMuxSt]	18	1			T15	1		T261	1		T262	4
auto[1]	auto[CntIncrSt]	54	1			T15	2		T67	3		T68	2
auto[1]	auto[CntProgSt]	705	1			T15	13		T67	27		T68	13
auto[1]	auto[TransCheckSt]	62	1			T67	1		T68	1		T65	2
auto[1]	auto[TokenHashSt]	557	1			T15	4		T67	6		T68	1
auto[1]	auto[FlashRmaSt]	29	1			T15	2		T67	1		T69	1
auto[1]	auto[TokenCheck0St]	36	1			T15	1		T67	2		T68	1
auto[1]	auto[TokenCheck1St]	15	1			T67	1		T66	1		T263	1
auto[1]	auto[TransProgSt]	543	1			T15	16		T67	17		T68	7
auto[1]	auto[PostTransSt]	1896	1			T4	5		T13	8		T19	5
auto[1]	auto[ScrapSt]	33	1			T15	1		T67	1		T66	2
auto[1]	auto[EscalateSt]	1133706	1			T4	490		T5	196		T15	10446
auto[1]	auto[InvalidSt]	5139	1			T5	2		T25	6		T14	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5427882	1			T1	112		T2	84		T3	1627
auto[0]	auto[IdleSt]	16010099	1			T1	103		T2	1195		T3	354
auto[0]	auto[ClkMuxSt]	28476	1			T1	1		T3	14		T4	12
auto[0]	auto[CntIncrSt]	28302	1			T1	1		T3	14		T4	12
auto[0]	auto[CntProgSt]	1153377	1			T1	30		T3	419		T4	24
auto[0]	auto[TransCheckSt]	22408	1			T1	1		T3	14		T5	7
auto[0]	auto[TokenHashSt]	19258971	1			T1	496		T3	367		T5	810
auto[0]	auto[FlashRmaSt]	27981	1			T3	42		T5	18		T6	15
auto[0]	auto[TokenCheck0St]	9857	1			T3	14		T5	7		T6	15
auto[0]	auto[TokenCheck1St]	7036	1			T3	14		T5	7		T6	15
auto[0]	auto[TransProgSt]	249031	1			T3	474		T5	14		T6	281
auto[0]	auto[PostTransSt]	8818632	1			T1	751		T3	1058		T4	981
auto[0]	auto[ScrapSt]	123311	1			T6	269		T15	4		T49	70
auto[0]	auto[EscalateSt]	3727542	1			T4	981		T5	931		T15	6729
auto[0]	auto[InvalidSt]	8049493	1			T5	703		T25	2793		T14	14008
auto[1]	auto[ResetSt]	180	1			T15	3		T67	5		T68	3
auto[1]	auto[IdleSt]	99	1			T15	3		T65	3		T70	4
auto[1]	auto[ClkMuxSt]	17	1			T65	1		T66	1		T171	1
auto[1]	auto[CntIncrSt]	60	1			T15	2		T67	2		T68	1
auto[1]	auto[CntProgSt]	737	1			T15	13		T67	21		T68	22
auto[1]	auto[TransCheckSt]	69	1			T67	2		T68	2		T65	2
auto[1]	auto[TokenHashSt]	555	1			T15	5		T67	12		T68	6
auto[1]	auto[FlashRmaSt]	35	1			T67	1		T69	1		T264	1
auto[1]	auto[TokenCheck0St]	39	1			T67	2		T68	1		T65	1
auto[1]	auto[TokenCheck1St]	19	1			T67	1		T68	1		T66	1
auto[1]	auto[TransProgSt]	534	1			T15	11		T67	20		T68	6
auto[1]	auto[PostTransSt]	1903	1			T4	7		T15	1		T13	2
auto[1]	auto[ScrapSt]	33	1			T70	1		T263	1		T265	1
auto[1]	auto[EscalateSt]	1130612	1			T4	686		T5	294		T15	7483
auto[1]	auto[InvalidSt]	5046	1			T5	3		T25	8		T14	2