Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.99 97.92 95.84 93.40 97.62 98.52 99.00 96.64


Total tests in report: 1004
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.69 67.69 81.48 81.48 45.56 45.56 55.28 55.28 64.29 64.29 81.57 81.57 92.29 92.29 53.36 53.36 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1910004892
77.82 10.13 88.18 6.70 73.20 27.63 72.33 17.04 69.05 4.76 86.65 5.08 94.03 1.74 61.31 7.95 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3145603347
82.96 5.14 95.08 6.90 78.37 5.18 75.58 3.25 78.57 9.52 90.04 3.39 94.03 0.00 69.08 7.77 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.4269737875
85.76 2.80 95.54 0.46 80.13 1.76 83.25 7.67 83.33 4.76 92.80 2.75 94.28 0.25 71.02 1.94 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1025776005
87.22 1.46 96.50 0.96 84.38 4.25 83.48 0.23 83.33 0.00 94.07 1.27 94.78 0.50 74.03 3.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.35810068
88.57 1.35 96.50 0.00 85.58 1.20 86.88 3.40 85.71 2.38 94.07 0.00 95.27 0.50 75.97 1.94 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3984734332
89.85 1.28 96.70 0.20 86.51 0.92 87.58 0.70 88.10 2.38 94.92 0.85 95.27 0.00 79.86 3.89 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2814244629
91.06 1.21 96.91 0.20 88.35 1.85 87.62 0.04 88.10 0.00 95.55 0.64 96.27 1.00 84.63 4.77 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4209512717
91.97 0.91 97.01 0.10 89.28 0.92 88.06 0.44 90.48 2.38 96.61 1.06 96.52 0.25 85.87 1.24 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2412439485
92.86 0.89 97.01 0.00 89.28 0.00 88.08 0.02 95.24 4.76 96.61 0.00 96.52 0.00 87.28 1.41 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3462141922
93.59 0.73 97.06 0.05 89.46 0.18 89.94 1.86 95.24 0.00 96.61 0.00 96.52 0.00 90.28 3.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2584987713
93.94 0.35 97.06 0.00 89.56 0.09 89.94 0.00 97.62 2.38 96.61 0.00 96.52 0.00 90.28 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2237166297
94.29 0.35 97.06 0.00 89.56 0.00 91.52 1.58 97.62 0.00 96.61 0.00 96.52 0.00 91.17 0.88 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1312004724
94.56 0.27 97.06 0.00 90.20 0.65 91.52 0.00 97.62 0.00 96.61 0.00 96.52 0.00 92.40 1.24 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3356849448
94.79 0.23 97.41 0.36 91.13 0.92 91.64 0.12 97.62 0.00 96.82 0.21 96.52 0.00 92.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.3472135981
95.00 0.21 97.41 0.00 91.13 0.00 91.64 0.00 97.62 0.00 96.82 0.00 98.01 1.49 92.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1366318517
95.22 0.21 97.46 0.05 92.14 1.02 91.64 0.00 97.62 0.00 97.25 0.42 98.01 0.00 92.40 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1358366366
95.40 0.18 97.62 0.15 92.14 0.00 91.99 0.35 97.62 0.00 97.46 0.21 98.01 0.00 92.93 0.53 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.851567272
95.57 0.17 97.72 0.10 92.42 0.28 92.26 0.26 97.62 0.00 97.67 0.21 98.01 0.00 93.29 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.4183938078
95.68 0.11 97.82 0.10 92.42 0.00 92.39 0.13 97.62 0.00 97.88 0.21 98.01 0.00 93.64 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2437598482
95.79 0.11 97.82 0.00 92.42 0.00 92.61 0.22 97.62 0.00 97.88 0.00 98.01 0.00 94.17 0.53 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3939807166
95.90 0.11 97.82 0.00 93.16 0.74 92.61 0.00 97.62 0.00 97.88 0.00 98.01 0.00 94.17 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3918583008
96.00 0.10 97.82 0.00 93.72 0.55 92.61 0.00 97.62 0.00 97.88 0.00 98.01 0.00 94.35 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2725478440
96.10 0.10 97.92 0.10 94.09 0.37 92.61 0.00 97.62 0.00 98.09 0.21 98.01 0.00 94.35 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.3144403901
96.19 0.09 97.92 0.00 94.09 0.00 93.24 0.63 97.62 0.00 98.09 0.00 98.01 0.00 94.35 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.3852635353
96.27 0.08 97.92 0.00 94.09 0.00 93.29 0.05 97.62 0.00 98.09 0.00 98.51 0.50 94.35 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.4195840095
96.32 0.06 97.92 0.00 94.09 0.00 93.33 0.04 97.62 0.00 98.09 0.00 98.51 0.00 94.70 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3510900678
96.37 0.05 97.92 0.00 94.45 0.37 93.33 0.00 97.62 0.00 98.09 0.00 98.51 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1329717378
96.43 0.05 97.92 0.00 94.45 0.00 93.33 0.00 97.62 0.00 98.09 0.00 98.51 0.00 95.05 0.35 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.202595158
96.47 0.05 97.92 0.00 94.55 0.09 93.37 0.04 97.62 0.00 98.31 0.21 98.51 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.1837694586
96.51 0.04 97.92 0.00 94.82 0.28 93.37 0.00 97.62 0.00 98.31 0.00 98.51 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2330388685
96.55 0.04 97.92 0.00 95.10 0.28 93.37 0.00 97.62 0.00 98.31 0.00 98.51 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2157221195
96.59 0.04 97.92 0.00 95.19 0.09 93.37 0.00 97.62 0.00 98.31 0.00 98.51 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2127019184
96.63 0.04 97.92 0.00 95.19 0.00 93.37 0.00 97.62 0.00 98.31 0.00 98.76 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.84778110
96.66 0.04 97.92 0.00 95.19 0.00 93.37 0.00 97.62 0.00 98.31 0.00 99.00 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3104205280
96.69 0.03 97.92 0.00 95.19 0.00 93.37 0.00 97.62 0.00 98.52 0.21 99.00 0.00 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.3092137854
96.72 0.03 97.92 0.00 95.19 0.00 93.38 0.01 97.62 0.00 98.52 0.00 99.00 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.4038054237
96.75 0.03 97.92 0.00 95.38 0.18 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.991534585
96.77 0.03 97.92 0.00 95.38 0.00 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3520495493
96.80 0.03 97.92 0.00 95.38 0.00 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.976809
96.82 0.03 97.92 0.00 95.38 0.00 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.25054295
96.85 0.03 97.92 0.00 95.38 0.00 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.4116189457
96.87 0.03 97.92 0.00 95.38 0.00 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.2863473806
96.90 0.03 97.92 0.00 95.38 0.00 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.47 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1302002808
96.92 0.03 97.92 0.00 95.38 0.00 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.64 0.18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3300425657
96.94 0.01 97.92 0.00 95.47 0.09 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2764000198
96.95 0.01 97.92 0.00 95.56 0.09 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.44133221
96.96 0.01 97.92 0.00 95.66 0.09 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.342388295
96.98 0.01 97.92 0.00 95.75 0.09 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3504409592
96.99 0.01 97.92 0.00 95.84 0.09 93.38 0.00 97.62 0.00 98.52 0.00 99.00 0.00 96.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.319812187
96.99 0.01 97.92 0.00 95.84 0.00 93.40 0.02 97.62 0.00 98.52 0.00 99.00 0.00 96.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1819744354

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3006972740
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2839139223
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.404123942
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2967479455
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.188451005
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1006896238
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1255232353
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2118516404
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.855853637
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2675227905
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2904056165
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2639748074
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1784794407
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1261871994
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3560310805
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2165941663
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2054092241
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.676803023
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.97304401
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2723346532
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1848713107
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1173294476
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3140640753
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.612428555
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1207337447
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2699525183
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3737754813
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3839101590
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2234573042
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.327160071
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1319246821
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.417960216
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1727807267
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1232515721
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.342288099
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/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2448008247



Total test records in report: 1004
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.976809 Aug 27 06:53:45 AM UTC 24 Aug 27 06:53:47 AM UTC 24 213674001 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.4038054237 Aug 27 06:53:48 AM UTC 24 Aug 27 06:53:50 AM UTC 24 12936098 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.3456699653 Aug 27 06:53:45 AM UTC 24 Aug 27 06:53:50 AM UTC 24 91912917 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3520495493 Aug 27 06:53:46 AM UTC 24 Aug 27 06:53:51 AM UTC 24 434955222 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.2111638260 Aug 27 06:53:46 AM UTC 24 Aug 27 06:53:51 AM UTC 24 78643788 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.2257434002 Aug 27 06:53:48 AM UTC 24 Aug 27 06:53:53 AM UTC 24 230106660 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1910004892 Aug 27 06:53:48 AM UTC 24 Aug 27 06:53:56 AM UTC 24 642124318 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.35810068 Aug 27 06:53:50 AM UTC 24 Aug 27 06:53:57 AM UTC 24 301690535 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.513295930 Aug 27 06:53:50 AM UTC 24 Aug 27 06:53:58 AM UTC 24 163585225 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2437598482 Aug 27 06:53:49 AM UTC 24 Aug 27 06:53:58 AM UTC 24 569907501 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2270435066 Aug 27 06:53:56 AM UTC 24 Aug 27 06:53:58 AM UTC 24 29524144 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2814244629 Aug 27 06:53:47 AM UTC 24 Aug 27 06:53:59 AM UTC 24 573582984 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1622306973 Aug 27 06:53:56 AM UTC 24 Aug 27 06:53:59 AM UTC 24 93462593 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1695841705 Aug 27 06:53:57 AM UTC 24 Aug 27 06:54:00 AM UTC 24 13854923 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1025776005 Aug 27 06:53:52 AM UTC 24 Aug 27 06:54:00 AM UTC 24 344622451 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.3169224237 Aug 27 06:53:58 AM UTC 24 Aug 27 06:54:02 AM UTC 24 129889164 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.25054295 Aug 27 06:54:00 AM UTC 24 Aug 27 06:54:02 AM UTC 24 20789112 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.851567272 Aug 27 06:53:48 AM UTC 24 Aug 27 06:54:02 AM UTC 24 365469367 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3510900678 Aug 27 06:53:52 AM UTC 24 Aug 27 06:54:03 AM UTC 24 644662283 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.1431386846 Aug 27 06:54:02 AM UTC 24 Aug 27 06:54:05 AM UTC 24 107405386 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3145603347 Aug 27 06:53:49 AM UTC 24 Aug 27 06:54:06 AM UTC 24 973565881 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.1982781143 Aug 27 06:54:00 AM UTC 24 Aug 27 06:54:07 AM UTC 24 133905042 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.525681009 Aug 27 06:54:00 AM UTC 24 Aug 27 06:54:08 AM UTC 24 254832287 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3939807166 Aug 27 06:53:57 AM UTC 24 Aug 27 06:54:08 AM UTC 24 90799716 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2479700261 Aug 27 06:54:07 AM UTC 24 Aug 27 06:54:09 AM UTC 24 14228239 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.3472135981 Aug 27 06:54:07 AM UTC 24 Aug 27 06:54:09 AM UTC 24 46649538 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1535729118 Aug 27 06:53:59 AM UTC 24 Aug 27 06:54:10 AM UTC 24 1331720920 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.543128284 Aug 27 06:54:07 AM UTC 24 Aug 27 06:54:10 AM UTC 24 20064835 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3293428609 Aug 27 06:53:52 AM UTC 24 Aug 27 06:54:11 AM UTC 24 1699381872 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1118746640 Aug 27 06:54:07 AM UTC 24 Aug 27 06:54:11 AM UTC 24 90123078 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.1467027715 Aug 27 06:54:03 AM UTC 24 Aug 27 06:54:12 AM UTC 24 368152693 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.4116189457 Aug 27 06:54:09 AM UTC 24 Aug 27 06:54:12 AM UTC 24 35941726 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2412439485 Aug 27 06:53:54 AM UTC 24 Aug 27 06:54:12 AM UTC 24 921524510 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.3620101552 Aug 27 06:54:02 AM UTC 24 Aug 27 06:54:13 AM UTC 24 530772746 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.4199619338 Aug 27 06:53:45 AM UTC 24 Aug 27 06:54:14 AM UTC 24 754991143 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.4269737875 Aug 27 06:54:03 AM UTC 24 Aug 27 06:54:14 AM UTC 24 384418131 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.2442797929 Aug 27 06:54:03 AM UTC 24 Aug 27 06:54:14 AM UTC 24 427646788 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2346895748 Aug 27 06:53:50 AM UTC 24 Aug 27 06:54:16 AM UTC 24 1335596895 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2858408657 Aug 27 06:54:10 AM UTC 24 Aug 27 06:54:17 AM UTC 24 402806002 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.2507234245 Aug 27 06:54:07 AM UTC 24 Aug 27 06:54:17 AM UTC 24 246718232 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3462141922 Aug 27 06:53:59 AM UTC 24 Aug 27 06:54:18 AM UTC 24 1161385283 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3912300388 Aug 27 06:54:09 AM UTC 24 Aug 27 06:54:18 AM UTC 24 196105768 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.2882905729 Aug 27 06:54:13 AM UTC 24 Aug 27 06:54:18 AM UTC 24 608989816 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.2563387403 Aug 27 06:54:08 AM UTC 24 Aug 27 06:54:18 AM UTC 24 819999585 ps
T99 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.865452774 Aug 27 06:54:07 AM UTC 24 Aug 27 06:54:18 AM UTC 24 69493264 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.489868539 Aug 27 06:54:01 AM UTC 24 Aug 27 06:54:19 AM UTC 24 5526091873 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.488923829 Aug 27 06:54:17 AM UTC 24 Aug 27 06:54:20 AM UTC 24 19290243 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.4147551785 Aug 27 06:54:17 AM UTC 24 Aug 27 06:54:20 AM UTC 24 21312150 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.438358211 Aug 27 06:54:17 AM UTC 24 Aug 27 06:54:21 AM UTC 24 29031403 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3425180089 Aug 27 06:54:19 AM UTC 24 Aug 27 06:54:21 AM UTC 24 13939223 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.4195840095 Aug 27 06:54:12 AM UTC 24 Aug 27 06:54:23 AM UTC 24 774041016 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.2737728717 Aug 27 06:54:19 AM UTC 24 Aug 27 06:54:24 AM UTC 24 68899574 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1206505968 Aug 27 06:54:03 AM UTC 24 Aug 27 06:54:25 AM UTC 24 4191136651 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.1935438585 Aug 27 06:54:14 AM UTC 24 Aug 27 06:54:25 AM UTC 24 869511241 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1676355881 Aug 27 06:54:20 AM UTC 24 Aug 27 06:54:26 AM UTC 24 102817403 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.142469894 Aug 27 06:54:01 AM UTC 24 Aug 27 06:54:26 AM UTC 24 11326266950 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.3002009744 Aug 27 06:54:11 AM UTC 24 Aug 27 06:54:27 AM UTC 24 1276451917 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3326844030 Aug 27 06:54:19 AM UTC 24 Aug 27 06:54:27 AM UTC 24 101146891 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1312004724 Aug 27 06:53:49 AM UTC 24 Aug 27 06:54:27 AM UTC 24 2521291646 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.18182516 Aug 27 06:54:13 AM UTC 24 Aug 27 06:54:28 AM UTC 24 926273367 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.2848573747 Aug 27 06:53:57 AM UTC 24 Aug 27 06:54:28 AM UTC 24 899234702 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1504103375 Aug 27 06:54:14 AM UTC 24 Aug 27 06:54:28 AM UTC 24 392307602 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.4041536546 Aug 27 06:53:50 AM UTC 24 Aug 27 06:54:28 AM UTC 24 21676066293 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.861105751 Aug 27 06:54:11 AM UTC 24 Aug 27 06:54:28 AM UTC 24 2713888966 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4116308179 Aug 27 06:54:13 AM UTC 24 Aug 27 06:54:29 AM UTC 24 4339321840 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.4095374380 Aug 27 06:54:20 AM UTC 24 Aug 27 06:54:29 AM UTC 24 479480567 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.3627254161 Aug 27 06:54:19 AM UTC 24 Aug 27 06:54:29 AM UTC 24 981879841 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.485292479 Aug 27 06:54:00 AM UTC 24 Aug 27 06:54:31 AM UTC 24 1498413517 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.426956194 Aug 27 06:54:22 AM UTC 24 Aug 27 06:54:31 AM UTC 24 1392954727 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.1751795559 Aug 27 06:54:28 AM UTC 24 Aug 27 06:54:31 AM UTC 24 20053250 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2852285126 Aug 27 06:54:30 AM UTC 24 Aug 27 06:54:33 AM UTC 24 27344853 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.349824207 Aug 27 06:54:28 AM UTC 24 Aug 27 06:54:33 AM UTC 24 48600349 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2762503077 Aug 27 06:54:30 AM UTC 24 Aug 27 06:54:33 AM UTC 24 36906132 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.499684585 Aug 27 06:54:30 AM UTC 24 Aug 27 06:54:34 AM UTC 24 44183180 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.1794792688 Aug 27 06:54:25 AM UTC 24 Aug 27 06:54:35 AM UTC 24 1530501672 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2120006908 Aug 27 06:54:24 AM UTC 24 Aug 27 06:54:36 AM UTC 24 529260015 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1929926632 Aug 27 06:54:30 AM UTC 24 Aug 27 06:54:36 AM UTC 24 92875607 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2718920980 Aug 27 06:54:23 AM UTC 24 Aug 27 06:54:36 AM UTC 24 804041446 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.2434159019 Aug 27 06:54:19 AM UTC 24 Aug 27 06:54:37 AM UTC 24 818165842 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.254273246 Aug 27 06:54:26 AM UTC 24 Aug 27 06:54:37 AM UTC 24 923481601 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.4024304269 Aug 27 06:54:26 AM UTC 24 Aug 27 06:54:38 AM UTC 24 3501521688 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.3540067438 Aug 27 06:54:30 AM UTC 24 Aug 27 06:54:38 AM UTC 24 609837611 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.1399147365 Aug 27 06:54:19 AM UTC 24 Aug 27 06:54:38 AM UTC 24 567290400 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.449482469 Aug 27 06:54:34 AM UTC 24 Aug 27 06:54:39 AM UTC 24 191439690 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2584987713 Aug 27 06:54:19 AM UTC 24 Aug 27 06:54:39 AM UTC 24 808179100 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.2312864641 Aug 27 06:54:51 AM UTC 24 Aug 27 06:55:15 AM UTC 24 1868577364 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.1518688397 Aug 27 06:54:20 AM UTC 24 Aug 27 06:54:40 AM UTC 24 533240520 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.3822240496 Aug 27 06:54:16 AM UTC 24 Aug 27 06:54:40 AM UTC 24 640129188 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.63258377 Aug 27 06:54:30 AM UTC 24 Aug 27 06:54:40 AM UTC 24 376373972 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.3422074069 Aug 27 06:54:32 AM UTC 24 Aug 27 06:54:40 AM UTC 24 292013615 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.2236607024 Aug 27 06:54:38 AM UTC 24 Aug 27 06:54:41 AM UTC 24 21097976 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.2006523461 Aug 27 06:54:38 AM UTC 24 Aug 27 06:54:41 AM UTC 24 23666072 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1740269059 Aug 27 06:54:39 AM UTC 24 Aug 27 06:54:42 AM UTC 24 14363902 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.3352250552 Aug 27 06:54:07 AM UTC 24 Aug 27 06:54:42 AM UTC 24 5777359172 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.417153363 Aug 27 06:54:05 AM UTC 24 Aug 27 06:54:43 AM UTC 24 413931800 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.2155336165 Aug 27 06:54:41 AM UTC 24 Aug 27 06:54:43 AM UTC 24 20432778 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2934222478 Aug 27 06:54:41 AM UTC 24 Aug 27 06:54:44 AM UTC 24 245671385 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.165206253 Aug 27 06:54:40 AM UTC 24 Aug 27 06:54:45 AM UTC 24 349634305 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.1074379727 Aug 27 06:54:36 AM UTC 24 Aug 27 06:54:45 AM UTC 24 861362922 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.552158873 Aug 27 06:54:34 AM UTC 24 Aug 27 06:54:45 AM UTC 24 1860119064 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.347389979 Aug 27 06:54:36 AM UTC 24 Aug 27 06:54:45 AM UTC 24 864940864 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.333205150 Aug 27 06:54:41 AM UTC 24 Aug 27 06:54:45 AM UTC 24 71481444 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.4131006173 Aug 27 06:54:30 AM UTC 24 Aug 27 06:54:46 AM UTC 24 212142028 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.2146620973 Aug 27 06:54:32 AM UTC 24 Aug 27 06:54:46 AM UTC 24 1116564803 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.548673524 Aug 27 06:54:35 AM UTC 24 Aug 27 06:54:48 AM UTC 24 347079188 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2058466722 Aug 27 06:54:39 AM UTC 24 Aug 27 06:54:49 AM UTC 24 636702009 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.697936550 Aug 27 06:54:32 AM UTC 24 Aug 27 06:54:50 AM UTC 24 488925789 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.325058658 Aug 27 06:54:47 AM UTC 24 Aug 27 06:54:50 AM UTC 24 18591800 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2549861546 Aug 27 06:54:47 AM UTC 24 Aug 27 06:54:50 AM UTC 24 71254055 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1946997926 Aug 27 06:54:47 AM UTC 24 Aug 27 06:54:50 AM UTC 24 16699827 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.772154184 Aug 27 06:54:42 AM UTC 24 Aug 27 06:54:50 AM UTC 24 964931253 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.1837694586 Aug 27 06:54:38 AM UTC 24 Aug 27 06:55:13 AM UTC 24 1857732654 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.4287627390 Aug 27 06:54:02 AM UTC 24 Aug 27 06:54:50 AM UTC 24 12599602791 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.3868617010 Aug 27 06:54:47 AM UTC 24 Aug 27 06:54:50 AM UTC 24 136352196 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3886620127 Aug 27 06:54:16 AM UTC 24 Aug 27 06:54:52 AM UTC 24 431565703 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.1509956102 Aug 27 06:54:40 AM UTC 24 Aug 27 06:54:52 AM UTC 24 1710740758 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.2099932498 Aug 27 06:54:41 AM UTC 24 Aug 27 06:54:52 AM UTC 24 153150324 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.669048170 Aug 27 06:54:47 AM UTC 24 Aug 27 06:54:53 AM UTC 24 57158418 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.2863473806 Aug 27 06:54:51 AM UTC 24 Aug 27 06:54:53 AM UTC 24 42560392 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.1334990044 Aug 27 06:54:45 AM UTC 24 Aug 27 06:54:55 AM UTC 24 749113533 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.2408343645 Aug 27 06:54:45 AM UTC 24 Aug 27 06:54:55 AM UTC 24 293363494 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.2285618514 Aug 27 06:54:41 AM UTC 24 Aug 27 06:54:56 AM UTC 24 626381756 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.2564731784 Aug 27 06:54:27 AM UTC 24 Aug 27 06:54:56 AM UTC 24 4151595459 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.2123028393 Aug 27 06:54:56 AM UTC 24 Aug 27 06:54:58 AM UTC 24 15684912 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.861639985 Aug 27 06:54:56 AM UTC 24 Aug 27 06:54:59 AM UTC 24 86217490 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.314115742 Aug 27 06:54:45 AM UTC 24 Aug 27 06:54:59 AM UTC 24 1659757962 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3707049942 Aug 27 06:54:56 AM UTC 24 Aug 27 06:54:59 AM UTC 24 11591437 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.888325763 Aug 27 06:54:30 AM UTC 24 Aug 27 06:55:00 AM UTC 24 337912256 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1528968076 Aug 27 06:54:44 AM UTC 24 Aug 27 06:55:01 AM UTC 24 922803620 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.3220680085 Aug 27 06:54:49 AM UTC 24 Aug 27 06:55:02 AM UTC 24 2286224153 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1302002808 Aug 27 06:55:00 AM UTC 24 Aug 27 06:55:02 AM UTC 24 11378429 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.755722663 Aug 27 06:54:12 AM UTC 24 Aug 27 06:55:02 AM UTC 24 3124148402 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1211923263 Aug 27 06:54:51 AM UTC 24 Aug 27 06:55:02 AM UTC 24 1338575188 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.1415770997 Aug 27 06:54:58 AM UTC 24 Aug 27 06:55:03 AM UTC 24 84524924 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3867766119 Aug 27 06:54:47 AM UTC 24 Aug 27 06:55:04 AM UTC 24 2042630397 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.107504529 Aug 27 06:54:27 AM UTC 24 Aug 27 06:55:04 AM UTC 24 444833873 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.3852635353 Aug 27 06:54:39 AM UTC 24 Aug 27 06:55:04 AM UTC 24 1059132304 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.481639178 Aug 27 06:54:52 AM UTC 24 Aug 27 06:55:05 AM UTC 24 271379985 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.655904153 Aug 27 06:54:35 AM UTC 24 Aug 27 06:55:06 AM UTC 24 4071320751 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.3149838600 Aug 27 06:54:21 AM UTC 24 Aug 27 06:55:06 AM UTC 24 11357355079 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.3482205121 Aug 27 06:55:01 AM UTC 24 Aug 27 06:55:07 AM UTC 24 989186115 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.756805829 Aug 27 06:54:58 AM UTC 24 Aug 27 06:55:07 AM UTC 24 238686750 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1876880178 Aug 27 06:54:51 AM UTC 24 Aug 27 06:55:07 AM UTC 24 2929650913 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.269177126 Aug 27 06:55:03 AM UTC 24 Aug 27 06:55:07 AM UTC 24 101426020 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.2856213645 Aug 27 06:54:51 AM UTC 24 Aug 27 06:55:07 AM UTC 24 1687111529 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3641023457 Aug 27 06:54:51 AM UTC 24 Aug 27 06:55:09 AM UTC 24 515445201 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.1252835306 Aug 27 06:54:34 AM UTC 24 Aug 27 06:55:09 AM UTC 24 2150945657 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1171645448 Aug 27 06:55:00 AM UTC 24 Aug 27 06:55:09 AM UTC 24 278661609 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1181700276 Aug 27 06:55:08 AM UTC 24 Aug 27 06:55:10 AM UTC 24 80415756 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2557064850 Aug 27 06:54:54 AM UTC 24 Aug 27 06:55:10 AM UTC 24 318188875 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.3933672497 Aug 27 06:55:08 AM UTC 24 Aug 27 06:55:10 AM UTC 24 26315946 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.4248990005 Aug 27 06:55:00 AM UTC 24 Aug 27 06:55:10 AM UTC 24 1664488393 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.372136743 Aug 27 06:55:08 AM UTC 24 Aug 27 06:55:10 AM UTC 24 110112543 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3020969326 Aug 27 06:54:44 AM UTC 24 Aug 27 06:55:11 AM UTC 24 4374715023 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1800475698 Aug 27 06:54:04 AM UTC 24 Aug 27 06:55:12 AM UTC 24 5904063792 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.4204752119 Aug 27 06:54:54 AM UTC 24 Aug 27 06:55:12 AM UTC 24 690269742 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.151459159 Aug 27 06:55:00 AM UTC 24 Aug 27 06:55:14 AM UTC 24 299234049 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1343079933 Aug 27 06:55:04 AM UTC 24 Aug 27 06:55:12 AM UTC 24 7041879013 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.1875653992 Aug 27 06:55:10 AM UTC 24 Aug 27 06:55:14 AM UTC 24 38567856 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2257454630 Aug 27 06:55:11 AM UTC 24 Aug 27 06:55:14 AM UTC 24 11343493 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2736591265 Aug 27 06:54:51 AM UTC 24 Aug 27 06:55:14 AM UTC 24 5246480929 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.888367794 Aug 27 06:54:41 AM UTC 24 Aug 27 06:55:14 AM UTC 24 3372149284 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2166032027 Aug 27 06:55:06 AM UTC 24 Aug 27 06:55:16 AM UTC 24 2167824271 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1819744354 Aug 27 06:54:10 AM UTC 24 Aug 27 06:55:16 AM UTC 24 3592788628 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.711313301 Aug 27 06:55:13 AM UTC 24 Aug 27 06:55:16 AM UTC 24 453622136 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.874960844 Aug 27 06:55:15 AM UTC 24 Aug 27 06:55:17 AM UTC 24 17676933 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.3854686002 Aug 27 06:55:15 AM UTC 24 Aug 27 06:55:17 AM UTC 24 23893420 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2448008247 Aug 27 06:55:15 AM UTC 24 Aug 27 06:55:17 AM UTC 24 17935012 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2247373076 Aug 27 06:54:52 AM UTC 24 Aug 27 06:55:18 AM UTC 24 647247427 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.207510254 Aug 27 06:55:04 AM UTC 24 Aug 27 06:55:18 AM UTC 24 2226228494 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.2625390587 Aug 27 06:55:06 AM UTC 24 Aug 27 06:55:18 AM UTC 24 1588175064 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1559404385 Aug 27 06:54:47 AM UTC 24 Aug 27 06:55:18 AM UTC 24 1203539091 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.475624845 Aug 27 06:55:09 AM UTC 24 Aug 27 06:55:20 AM UTC 24 156776440 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3300425657 Aug 27 06:55:18 AM UTC 24 Aug 27 06:55:20 AM UTC 24 13449028 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.222159450 Aug 27 06:55:10 AM UTC 24 Aug 27 06:55:20 AM UTC 24 1259162667 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.4235611681 Aug 27 06:55:11 AM UTC 24 Aug 27 06:55:20 AM UTC 24 2243514504 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.2120568674 Aug 27 06:55:03 AM UTC 24 Aug 27 06:55:20 AM UTC 24 392346252 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.2989119029 Aug 27 06:55:17 AM UTC 24 Aug 27 06:55:21 AM UTC 24 122066927 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.2011632417 Aug 27 06:55:18 AM UTC 24 Aug 27 06:55:22 AM UTC 24 313276331 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.957341657 Aug 27 06:54:58 AM UTC 24 Aug 27 06:55:22 AM UTC 24 169903030 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.4080539992 Aug 27 06:55:12 AM UTC 24 Aug 27 06:55:23 AM UTC 24 634172962 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.1051662097 Aug 27 06:55:13 AM UTC 24 Aug 27 06:55:24 AM UTC 24 1387727985 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.3127652697 Aug 27 06:54:20 AM UTC 24 Aug 27 06:55:25 AM UTC 24 4878928431 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1314132074 Aug 27 06:55:15 AM UTC 24 Aug 27 06:55:25 AM UTC 24 351397003 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.2508048826 Aug 27 06:55:20 AM UTC 24 Aug 27 06:55:25 AM UTC 24 760398724 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.617394001 Aug 27 06:55:10 AM UTC 24 Aug 27 06:55:25 AM UTC 24 5429376632 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.2853287439 Aug 27 06:55:10 AM UTC 24 Aug 27 06:55:25 AM UTC 24 962488105 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.439168853 Aug 27 06:55:23 AM UTC 24 Aug 27 06:55:26 AM UTC 24 21057030 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1222129519 Aug 27 06:55:18 AM UTC 24 Aug 27 06:55:26 AM UTC 24 4034275189 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3695948621 Aug 27 06:54:42 AM UTC 24 Aug 27 06:55:26 AM UTC 24 12872695813 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.521867716 Aug 27 06:55:13 AM UTC 24 Aug 27 06:55:26 AM UTC 24 1763903765 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.1437530556 Aug 27 06:55:21 AM UTC 24 Aug 27 06:55:26 AM UTC 24 1254041899 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.2120878073 Aug 27 06:55:48 AM UTC 24 Aug 27 06:55:53 AM UTC 24 39404020 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.3780800661 Aug 27 06:55:16 AM UTC 24 Aug 27 06:55:26 AM UTC 24 56406460 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.2733024504 Aug 27 06:54:45 AM UTC 24 Aug 27 06:55:27 AM UTC 24 825894212 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2896723698 Aug 27 06:55:24 AM UTC 24 Aug 27 06:55:27 AM UTC 24 13755124 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1419652181 Aug 27 06:55:13 AM UTC 24 Aug 27 06:55:27 AM UTC 24 1317760482 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2774895795 Aug 27 06:55:24 AM UTC 24 Aug 27 06:55:27 AM UTC 24 28790892 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3228453526 Aug 27 06:55:15 AM UTC 24 Aug 27 06:55:27 AM UTC 24 612699661 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1180256832 Aug 27 06:55:18 AM UTC 24 Aug 27 06:55:29 AM UTC 24 249583835 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.96779305 Aug 27 06:55:21 AM UTC 24 Aug 27 06:55:30 AM UTC 24 738827099 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.2684714516 Aug 27 06:55:06 AM UTC 24 Aug 27 06:55:30 AM UTC 24 3180689082 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2750469926 Aug 27 06:54:32 AM UTC 24 Aug 27 06:55:30 AM UTC 24 4267573043 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.2080883260 Aug 27 06:54:51 AM UTC 24 Aug 27 06:55:30 AM UTC 24 1934623836 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.4072488426 Aug 27 06:54:41 AM UTC 24 Aug 27 06:55:31 AM UTC 24 1874031061 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1683709629 Aug 27 06:55:21 AM UTC 24 Aug 27 06:55:32 AM UTC 24 2368491747 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.1988108877 Aug 27 06:55:17 AM UTC 24 Aug 27 06:55:32 AM UTC 24 1338090929 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.1869028168 Aug 27 06:55:26 AM UTC 24 Aug 27 06:55:32 AM UTC 24 102694695 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2481161147 Aug 27 06:55:31 AM UTC 24 Aug 27 06:55:33 AM UTC 24 113651240 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3805345954 Aug 27 06:55:31 AM UTC 24 Aug 27 06:55:33 AM UTC 24 35025634 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3389649558 Aug 27 06:55:08 AM UTC 24 Aug 27 06:55:34 AM UTC 24 2071985717 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3864966729 Aug 27 06:55:27 AM UTC 24 Aug 27 06:55:34 AM UTC 24 374640232 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.3239960389 Aug 27 06:55:31 AM UTC 24 Aug 27 06:55:34 AM UTC 24 23058152 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.3751824472 Aug 27 06:55:28 AM UTC 24 Aug 27 06:55:35 AM UTC 24 1557311989 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.1944359415 Aug 27 06:55:26 AM UTC 24 Aug 27 06:55:35 AM UTC 24 86177760 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1532785587 Aug 27 06:55:19 AM UTC 24 Aug 27 06:55:36 AM UTC 24 1716052981 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.2237122617 Aug 27 06:55:26 AM UTC 24 Aug 27 06:55:36 AM UTC 24 411582265 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.1142258214 Aug 27 06:55:22 AM UTC 24 Aug 27 06:55:36 AM UTC 24 971151681 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1595776464 Aug 27 06:55:33 AM UTC 24 Aug 27 06:55:37 AM UTC 24 100941700 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.43967773 Aug 27 06:55:21 AM UTC 24 Aug 27 06:55:37 AM UTC 24 12874850019 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.4246692577 Aug 27 06:55:19 AM UTC 24 Aug 27 06:55:38 AM UTC 24 2026479124 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.3949800401 Aug 27 06:55:35 AM UTC 24 Aug 27 06:55:39 AM UTC 24 415832139 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.1271075246 Aug 27 06:55:27 AM UTC 24 Aug 27 06:55:39 AM UTC 24 1517141169 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.2200022344 Aug 27 06:55:29 AM UTC 24 Aug 27 06:55:40 AM UTC 24 248545718 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.3488037210 Aug 27 06:55:38 AM UTC 24 Aug 27 06:55:40 AM UTC 24 93326254 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1553921646 Aug 27 06:55:13 AM UTC 24 Aug 27 06:55:40 AM UTC 24 975504834 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3211262509 Aug 27 06:55:29 AM UTC 24 Aug 27 06:55:41 AM UTC 24 1246780077 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.404673196 Aug 27 06:55:39 AM UTC 24 Aug 27 06:55:41 AM UTC 24 58623058 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.3092137854 Aug 27 06:55:38 AM UTC 24 Aug 27 06:55:42 AM UTC 24 109341597 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.697631204 Aug 27 06:55:33 AM UTC 24 Aug 27 06:55:42 AM UTC 24 226001693 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.883725756 Aug 27 06:55:29 AM UTC 24 Aug 27 06:55:43 AM UTC 24 318439992 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.2479439752 Aug 27 06:55:31 AM UTC 24 Aug 27 06:55:43 AM UTC 24 102589495 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.6381056 Aug 27 06:55:15 AM UTC 24 Aug 27 06:55:44 AM UTC 24 329917745 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.253166111 Aug 27 06:55:40 AM UTC 24 Aug 27 06:55:45 AM UTC 24 262174003 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.701628676 Aug 27 06:55:33 AM UTC 24 Aug 27 06:55:45 AM UTC 24 441821136 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.2904194530 Aug 27 06:55:27 AM UTC 24 Aug 27 06:55:45 AM UTC 24 690040452 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.4292376738 Aug 27 06:55:35 AM UTC 24 Aug 27 06:55:45 AM UTC 24 2219821035 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.449691391 Aug 27 06:55:33 AM UTC 24 Aug 27 06:55:45 AM UTC 24 263170104 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.2674339276 Aug 27 06:55:42 AM UTC 24 Aug 27 06:55:53 AM UTC 24 216532027 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3767448672 Aug 27 06:55:05 AM UTC 24 Aug 27 06:55:46 AM UTC 24 3134910138 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.2141694866 Aug 27 06:55:36 AM UTC 24 Aug 27 06:55:46 AM UTC 24 1518094670 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.2683981557 Aug 27 06:55:22 AM UTC 24 Aug 27 06:55:46 AM UTC 24 982268956 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3823957570 Aug 27 06:55:36 AM UTC 24 Aug 27 06:55:49 AM UTC 24 842366074 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.425940856 Aug 27 06:55:40 AM UTC 24 Aug 27 06:55:51 AM UTC 24 50223802 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.2079739907 Aug 27 06:55:48 AM UTC 24 Aug 27 06:55:51 AM UTC 24 16829326 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1740541204 Aug 27 06:55:49 AM UTC 24 Aug 27 06:55:51 AM UTC 24 46995571 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3656702270 Aug 27 06:54:36 AM UTC 24 Aug 27 06:55:53 AM UTC 24 6456802131 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.2780894750 Aug 27 06:55:46 AM UTC 24 Aug 27 06:55:53 AM UTC 24 378211166 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3984734332 Aug 27 06:54:27 AM UTC 24 Aug 27 06:55:54 AM UTC 24 2365130226 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.202595158 Aug 27 06:55:42 AM UTC 24 Aug 27 06:55:54 AM UTC 24 1309608253 ps
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