Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62022823

1

T1

1141

T2

3369

T3

3404

auto[1]

1145215

1

T3

396

T4

99

T12

11754

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

62016095

1

T1

1141

T2

3369

T3

3503

auto[1]

1151943

1

T3

297

T4

396

T12

11586

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5334549	1			T1	114		T2	876		T3	748
auto[IdleSt]	18112105	1			T1	82		T2	1076		T3	1381
auto[ClkMuxSt]	29543	1			T1	1		T2	9		T3	7
auto[CntIncrSt]	29412	1			T1	1		T2	9		T3	7
auto[CntProgSt]	1245289	1			T1	2		T2	18		T3	242
auto[TransCheckSt]	23466	1			T1	1		T2	9		T4	6
auto[TokenHashSt]	15758801	1			T1	30		T2	196		T4	114
auto[FlashRmaSt]	27887	1			T2	55		T4	35		T6	35
auto[TokenCheck0St]	10095	1			T2	9		T4	6		T6	18
auto[TokenCheck1St]	7148	1			T2	9		T4	6		T6	18
auto[TransProgSt]	282501	1			T2	18		T4	111		T6	390
auto[PostTransSt]	10653380	1			T1	910		T2	1085		T3	457
auto[ScrapSt]	195417	1			T12	8		T28	2169		T21	4
auto[EscalateSt]	4727687	1			T3	958		T4	1312		T12	15829
auto[InvalidSt]	6729352	1			T4	663		T24	11789		T27	3123

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1406	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	6729352	1			T4	663		T24	11789		T27	3123
EscalateSt	4727687	1			T3	958		T4	1312		T12	15829
ScrapSt	195417	1			T12	8		T28	2169		T21	4
PostTransSt	10653380	1			T1	910		T2	1085		T3	457
TransProgSt	282501	1			T2	18		T4	111		T6	390
TokenCheck1St	7148	1			T2	9		T4	6		T6	18
TokenCheck0St	10095	1			T2	9		T4	6		T6	18
FlashRmaSt	27887	1			T2	55		T4	35		T6	35
TokenHashSt	15758801	1			T1	30		T2	196		T4	114
TransCheckSt	23466	1			T1	1		T2	9		T4	6
CntProgSt	1245289	1			T1	2		T2	18		T3	242
CntIncrSt	29412	1			T1	1		T2	9		T3	7
ClkMuxSt	29543	1			T1	1		T2	9		T3	7
IdleSt	18112105	1			T1	82		T2	1076		T3	1381
ResetSt	5334549	1			T1	114		T2	876		T3	748
arcs[ResetSt=>IdleSt]	42938	1			T1	1		T2	9		T3	8
arcs[IdleSt=>ScrapSt]	238	1			T12	2		T28	2		T21	1
arcs[IdleSt=>ClkMuxSt]	29446	1			T1	1		T2	9		T3	7
arcs[ClkMuxSt=>CntIncrSt]	29412	1			T1	1		T2	9		T3	7
arcs[CntIncrSt=>PostTransSt]	1427	1			T16	11		T13	8		T18	5
arcs[CntIncrSt=>CntProgSt]	27909	1			T1	1		T2	9		T3	7
arcs[CntProgSt=>PostTransSt]	3576	1			T3	7		T10	19		T16	11
arcs[CntProgSt=>TransCheckSt]	23466	1			T1	1		T2	9		T4	6
arcs[TransCheckSt=>PostTransSt]	3301	1			T16	11		T17	39		T13	5
arcs[TransCheckSt=>TokenHashSt]	20007	1			T1	1		T2	9		T4	6
arcs[TokenHashSt=>PostTransSt]	8925	1			T1	1		T16	30		T19	1
arcs[TokenHashSt=>FlashRmaSt]	10127	1			T2	9		T4	6		T6	18
arcs[FlashRmaSt=>TokenCheck0St]	10095	1			T2	9		T4	6		T6	18
arcs[TokenCheck0St=>PostTransSt]	2876	1			T16	13		T17	11		T26	16
arcs[TokenCheck0St=>TokenCheck1St]	7148	1			T2	9		T4	6		T6	18
arcs[TokenCheck1St=>PostTransSt]	609	1			T16	1		T17	9		T26	1
arcs[TransProgSt=>PostTransSt]	5850	1			T2	9		T4	6		T6	18
arcs[IdleSt=>EscalateSt]	199	1			T12	6		T52	5		T55	11
arcs[ClkMuxSt=>EscalateSt]	34	1			T12	1		T52	1		T53	1
arcs[CntIncrSt=>EscalateSt]	76	1			T21	4		T52	1		T54	4
arcs[CntProgSt=>EscalateSt]	867	1			T12	8		T21	11		T52	3
arcs[TransCheckSt=>EscalateSt]	158	1			T12	4		T21	6		T52	1
arcs[TokenHashSt=>EscalateSt]	955	1			T12	34		T21	34		T52	32
arcs[FlashRmaSt=>EscalateSt]	32	1			T12	2		T52	2		T54	1
arcs[TokenCheck0St=>EscalateSt]	71	1			T21	3		T52	1		T54	4
arcs[TokenCheck1St=>EscalateSt]	27	1			T12	1		T21	1		T52	1
arcs[TransProgSt=>EscalateSt]	662	1			T12	2		T21	7		T52	9
arcs[PostTransSt=>EscalateSt]	4026	1			T3	7		T12	16		T10	19
arcs[InvalidSt=>EscalateSt]	9720	1			T4	5		T24	8		T27	41

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5334349	1			T1	114		T2	876		T3	748
auto[0]	auto[IdleSt]	18111969	1			T1	82		T2	1076		T3	1381
auto[0]	auto[ClkMuxSt]	29524	1			T1	1		T2	9		T3	7
auto[0]	auto[CntIncrSt]	29361	1			T1	1		T2	9		T3	7
auto[0]	auto[CntProgSt]	1244683	1			T1	2		T2	18		T3	242
auto[0]	auto[TransCheckSt]	23360	1			T1	1		T2	9		T4	6
auto[0]	auto[TokenHashSt]	15758181	1			T1	30		T2	196		T4	114
auto[0]	auto[FlashRmaSt]	27865	1			T2	55		T4	35		T6	35
auto[0]	auto[TokenCheck0St]	10046	1			T2	9		T4	6		T6	18
auto[0]	auto[TokenCheck1St]	7132	1			T2	9		T4	6		T6	18
auto[0]	auto[TransProgSt]	282067	1			T2	18		T4	111		T6	390
auto[0]	auto[PostTransSt]	10651312	1			T1	910		T2	1085		T3	453
auto[0]	auto[ScrapSt]	195369	1			T12	6		T28	2169		T21	3
auto[0]	auto[EscalateSt]	3591675	1			T3	566		T4	1214		T12	4135
auto[0]	auto[InvalidSt]	6724524	1			T4	662		T24	11785		T27	3104
auto[1]	auto[ResetSt]	200	1			T12	6		T21	4		T52	8
auto[1]	auto[IdleSt]	136	1			T12	4		T52	4		T55	9
auto[1]	auto[ClkMuxSt]	19	1			T53	1		T221	3		T222	1
auto[1]	auto[CntIncrSt]	51	1			T21	2		T54	2		T55	2
auto[1]	auto[CntProgSt]	606	1			T12	7		T21	6		T52	2
auto[1]	auto[TransCheckSt]	106	1			T12	4		T21	4		T52	1
auto[1]	auto[TokenHashSt]	620	1			T12	23		T21	25		T52	21
auto[1]	auto[FlashRmaSt]	22	1			T12	2		T54	1		T55	1
auto[1]	auto[TokenCheck0St]	49	1			T21	2		T52	1		T54	3
auto[1]	auto[TokenCheck1St]	16	1			T12	1		T223	1		T53	2
auto[1]	auto[TransProgSt]	434	1			T12	2		T21	5		T52	7
auto[1]	auto[PostTransSt]	2068	1			T3	4		T12	9		T10	6
auto[1]	auto[ScrapSt]	48	1			T12	2		T21	1		T54	1
auto[1]	auto[EscalateSt]	1136012	1			T3	392		T4	98		T12	11694
auto[1]	auto[InvalidSt]	4828	1			T4	1		T24	4		T27	19

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5334347	1			T1	114		T2	876		T3	748
auto[0]	auto[IdleSt]	18111977	1			T1	82		T2	1076		T3	1381
auto[0]	auto[ClkMuxSt]	29520	1			T1	1		T2	9		T3	7
auto[0]	auto[CntIncrSt]	29359	1			T1	1		T2	9		T3	7
auto[0]	auto[CntProgSt]	1244715	1			T1	2		T2	18		T3	242
auto[0]	auto[TransCheckSt]	23364	1			T1	1		T2	9		T4	6
auto[0]	auto[TokenHashSt]	15758168	1			T1	30		T2	196		T4	114
auto[0]	auto[FlashRmaSt]	27867	1			T2	55		T4	35		T6	35
auto[0]	auto[TokenCheck0St]	10047	1			T2	9		T4	6		T6	18
auto[0]	auto[TokenCheck1St]	7132	1			T2	9		T4	6		T6	18
auto[0]	auto[TransProgSt]	282049	1			T2	18		T4	111		T6	390
auto[0]	auto[PostTransSt]	10651278	1			T1	910		T2	1085		T3	454
auto[0]	auto[ScrapSt]	195378	1			T12	8		T28	2169		T21	4
auto[0]	auto[EscalateSt]	3585028	1			T3	664		T4	920		T12	4301
auto[0]	auto[InvalidSt]	6724460	1			T4	659		T24	11785		T27	3101
auto[1]	auto[ResetSt]	202	1			T12	4		T21	2		T52	6
auto[1]	auto[IdleSt]	128	1			T12	3		T52	1		T55	9
auto[1]	auto[ClkMuxSt]	23	1			T12	1		T52	1		T221	4
auto[1]	auto[CntIncrSt]	53	1			T21	4		T52	1		T54	2
auto[1]	auto[CntProgSt]	574	1			T12	5		T21	7		T52	2
auto[1]	auto[TransCheckSt]	102	1			T12	2		T21	5		T52	1
auto[1]	auto[TokenHashSt]	633	1			T12	27		T21	19		T52	24
auto[1]	auto[FlashRmaSt]	20	1			T12	1		T52	2		T53	1
auto[1]	auto[TokenCheck0St]	48	1			T21	2		T52	1		T54	3
auto[1]	auto[TokenCheck1St]	16	1			T21	1		T52	1		T224	1
auto[1]	auto[TransProgSt]	452	1			T12	2		T21	3		T52	8
auto[1]	auto[PostTransSt]	2102	1			T3	3		T12	13		T10	13
auto[1]	auto[ScrapSt]	39	1			T53	2		T225	2		T168	2
auto[1]	auto[EscalateSt]	1142659	1			T3	294		T4	392		T12	11528
auto[1]	auto[InvalidSt]	4892	1			T4	4		T24	4		T27	22