Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.27 97.92 95.84 93.40 100.00 98.52 98.76 96.47


Total tests in report: 997
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.92 67.92 81.84 81.84 52.50 52.50 58.02 58.02 64.29 64.29 83.26 83.26 92.29 92.29 43.29 43.29 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.3165404587
80.42 12.49 89.09 7.26 81.42 28.93 79.05 21.03 78.57 14.29 90.47 7.20 93.78 1.49 50.53 7.24 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2992422287
86.01 5.59 95.74 6.65 82.07 0.65 81.58 2.53 85.71 7.14 92.80 2.33 94.03 0.25 70.14 19.61 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3073836745
87.48 1.47 96.75 1.01 85.77 3.70 81.88 0.30 85.71 0.00 94.49 1.69 94.78 0.75 72.97 2.83 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3388209788
88.81 1.33 97.01 0.25 88.17 2.40 81.94 0.06 85.71 0.00 95.13 0.64 95.77 1.00 77.92 4.95 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3062299032
90.05 1.25 97.06 0.05 88.45 0.28 85.38 3.44 85.71 0.00 96.19 1.06 95.77 0.00 81.80 3.89 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.61737486
91.02 0.97 97.16 0.10 88.45 0.00 85.64 0.25 90.48 4.76 96.61 0.42 95.77 0.00 83.04 1.24 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3691682420
91.99 0.97 97.16 0.00 89.56 1.11 87.16 1.52 90.48 0.00 96.61 0.00 96.02 0.25 86.93 3.89 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.610168907
92.73 0.75 97.21 0.05 90.20 0.65 87.62 0.47 92.86 2.38 96.82 0.21 96.27 0.25 88.16 1.24 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.541336648
93.35 0.61 97.26 0.05 90.20 0.00 87.68 0.06 95.24 2.38 97.03 0.21 96.27 0.00 89.75 1.59 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.3332663083
93.76 0.41 97.31 0.05 91.13 0.92 87.72 0.04 95.24 0.00 97.67 0.64 96.27 0.00 90.99 1.24 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.268755997
94.17 0.41 97.31 0.00 91.22 0.09 88.15 0.43 95.24 0.00 97.67 0.00 96.52 0.25 93.11 2.12 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2343204345
94.58 0.40 97.31 0.00 91.50 0.28 88.15 0.00 97.62 2.38 97.67 0.00 96.52 0.00 93.29 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.4129540764
94.92 0.34 97.31 0.00 91.50 0.00 88.17 0.02 100.00 2.38 97.67 0.00 96.52 0.00 93.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.1167088224
95.24 0.32 97.31 0.00 91.50 0.00 90.15 1.98 100.00 0.00 97.67 0.00 96.77 0.25 93.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.133995052
95.45 0.21 97.31 0.00 91.50 0.00 90.15 0.00 100.00 0.00 97.67 0.00 98.26 1.49 93.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.732218974
95.66 0.21 97.67 0.36 92.42 0.92 90.32 0.17 100.00 0.00 97.67 0.00 98.26 0.00 93.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.676737430
95.85 0.19 97.67 0.00 92.42 0.00 91.62 1.30 100.00 0.00 97.67 0.00 98.26 0.00 93.29 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.2981222464
96.00 0.16 97.67 0.00 93.35 0.92 91.62 0.00 100.00 0.00 97.67 0.00 98.26 0.00 93.46 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.384715783
96.15 0.15 97.82 0.15 93.35 0.00 91.75 0.13 100.00 0.00 98.09 0.42 98.26 0.00 93.82 0.35 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.4156525244
96.28 0.12 97.82 0.00 93.35 0.00 92.60 0.85 100.00 0.00 98.09 0.00 98.26 0.00 93.82 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.2897391639
96.38 0.10 97.92 0.10 93.35 0.00 92.66 0.06 100.00 0.00 98.31 0.21 98.26 0.00 94.17 0.35 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1638964736
96.46 0.08 97.92 0.00 93.35 0.00 92.86 0.20 100.00 0.00 98.31 0.00 98.26 0.00 94.52 0.35 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.3533041229
96.54 0.08 97.92 0.00 93.90 0.55 92.86 0.00 100.00 0.00 98.31 0.00 98.26 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.4163375150
96.60 0.07 97.92 0.00 94.36 0.46 92.86 0.00 100.00 0.00 98.31 0.00 98.26 0.00 94.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3705525194
96.67 0.06 97.92 0.00 94.36 0.00 92.86 0.00 100.00 0.00 98.31 0.00 98.51 0.25 94.70 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.3182757689
96.73 0.06 97.92 0.00 94.36 0.00 93.29 0.43 100.00 0.00 98.31 0.00 98.51 0.00 94.70 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1000547084
96.78 0.05 97.92 0.00 94.36 0.00 93.29 0.00 100.00 0.00 98.31 0.00 98.51 0.00 95.05 0.35 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.1617093168
96.82 0.05 97.92 0.00 94.45 0.09 93.31 0.02 100.00 0.00 98.52 0.21 98.51 0.00 95.05 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.3848743126
96.87 0.04 97.92 0.00 94.55 0.09 93.35 0.04 100.00 0.00 98.52 0.00 98.51 0.00 95.23 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.1922001182
96.90 0.04 97.92 0.00 94.55 0.00 93.35 0.00 100.00 0.00 98.52 0.00 98.76 0.25 95.23 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2095843114
96.93 0.03 97.92 0.00 94.55 0.00 93.37 0.02 100.00 0.00 98.52 0.00 98.76 0.00 95.41 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.2241828710
96.96 0.03 97.92 0.00 94.73 0.18 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.602123280
96.98 0.03 97.92 0.00 94.92 0.18 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2155301742
97.01 0.03 97.92 0.00 95.10 0.18 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.966048792
97.04 0.03 97.92 0.00 95.29 0.18 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3729362397
97.06 0.03 97.92 0.00 95.29 0.00 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.58 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.2842624949
97.09 0.03 97.92 0.00 95.29 0.00 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.76 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3654474160
97.11 0.03 97.92 0.00 95.29 0.00 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 95.94 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.1055176630
97.14 0.03 97.92 0.00 95.29 0.00 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.11 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.417154656
97.16 0.03 97.92 0.00 95.29 0.00 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.29 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.2989158730
97.19 0.03 97.92 0.00 95.29 0.00 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.47 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.722321332
97.20 0.01 97.92 0.00 95.38 0.09 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1471777427
97.21 0.01 97.92 0.00 95.47 0.09 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1514295541
97.23 0.01 97.92 0.00 95.56 0.09 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1307703474
97.24 0.01 97.92 0.00 95.66 0.09 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2898734374
97.25 0.01 97.92 0.00 95.75 0.09 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4169381934
97.27 0.01 97.92 0.00 95.84 0.09 93.37 0.00 100.00 0.00 98.52 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2371189677
97.27 0.01 97.92 0.00 95.84 0.00 93.39 0.02 100.00 0.00 98.52 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.450976878
97.27 0.01 97.92 0.00 95.84 0.00 93.40 0.01 100.00 0.00 98.52 0.00 98.76 0.00 96.47 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3072792443

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.573495327
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3464284366
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2937511350
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3880344524
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2906012340
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3847041823
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.24803019
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1857014864
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.990114710
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2658190337
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3267820720
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2657001249
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3582360824
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3490939314
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2850305911
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2297463714
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3638118182
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.528778691
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3941787315
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2959051501
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1474934736
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1784297633
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3899418047
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1022858713
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.967727999
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.140115235
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.574857285
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1220261074
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1300170610
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1421662201
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.270763056
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1844063589
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.17522376
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2875105059
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.342916934
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3233260390
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3471138453
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Total test records in report: 997
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3654474160 Aug 29 12:12:25 AM UTC 24 Aug 29 12:12:27 AM UTC 24 11546686 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.2250776911 Aug 29 12:12:24 AM UTC 24 Aug 29 12:12:28 AM UTC 24 68778935 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.2645675680 Aug 29 12:12:26 AM UTC 24 Aug 29 12:12:31 AM UTC 24 253519118 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.2842624949 Aug 29 12:12:29 AM UTC 24 Aug 29 12:12:31 AM UTC 24 12621136 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.2334391683 Aug 29 12:12:25 AM UTC 24 Aug 29 12:12:38 AM UTC 24 69539543 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.3388209788 Aug 29 12:12:32 AM UTC 24 Aug 29 12:12:40 AM UTC 24 805844492 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.1378417780 Aug 29 12:12:29 AM UTC 24 Aug 29 12:12:40 AM UTC 24 5935599598 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3378714881 Aug 29 12:12:38 AM UTC 24 Aug 29 12:12:45 AM UTC 24 1101073277 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.3165404587 Aug 29 12:12:27 AM UTC 24 Aug 29 12:12:46 AM UTC 24 1189961916 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.1638964736 Aug 29 12:12:31 AM UTC 24 Aug 29 12:12:47 AM UTC 24 1598913715 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.1922001182 Aug 29 12:12:27 AM UTC 24 Aug 29 12:12:48 AM UTC 24 365940054 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2343204345 Aug 29 12:12:30 AM UTC 24 Aug 29 12:12:50 AM UTC 24 2012082041 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.676737430 Aug 29 12:12:48 AM UTC 24 Aug 29 12:12:50 AM UTC 24 213293575 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.61737486 Aug 29 12:12:25 AM UTC 24 Aug 29 12:12:52 AM UTC 24 157949408 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3023585113 Aug 29 12:12:50 AM UTC 24 Aug 29 12:12:52 AM UTC 24 61518152 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.3409918762 Aug 29 12:12:40 AM UTC 24 Aug 29 12:12:53 AM UTC 24 1415890100 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1755350640 Aug 29 12:12:49 AM UTC 24 Aug 29 12:12:54 AM UTC 24 49755431 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.349343100 Aug 29 12:12:53 AM UTC 24 Aug 29 12:12:57 AM UTC 24 98935839 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.1055176630 Aug 29 12:12:58 AM UTC 24 Aug 29 12:13:00 AM UTC 24 13074255 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.4156525244 Aug 29 12:12:29 AM UTC 24 Aug 29 12:13:01 AM UTC 24 2851520394 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3073836745 Aug 29 12:12:40 AM UTC 24 Aug 29 12:13:03 AM UTC 24 5292635898 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.3402151897 Aug 29 12:12:58 AM UTC 24 Aug 29 12:13:04 AM UTC 24 243791219 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3823233597 Aug 29 12:12:42 AM UTC 24 Aug 29 12:13:04 AM UTC 24 562901317 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.986551385 Aug 29 12:12:53 AM UTC 24 Aug 29 12:13:05 AM UTC 24 75829460 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.1212311371 Aug 29 12:13:02 AM UTC 24 Aug 29 12:13:06 AM UTC 24 88714797 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3691682420 Aug 29 12:12:55 AM UTC 24 Aug 29 12:13:08 AM UTC 24 283810968 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.4161187341 Aug 29 12:13:31 AM UTC 24 Aug 29 12:13:47 AM UTC 24 395479659 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.2992422287 Aug 29 12:12:31 AM UTC 24 Aug 29 12:13:09 AM UTC 24 4852955763 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1488737147 Aug 29 12:12:53 AM UTC 24 Aug 29 12:13:09 AM UTC 24 291796268 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.4049323883 Aug 29 12:12:59 AM UTC 24 Aug 29 12:13:12 AM UTC 24 851079868 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.82190315 Aug 29 12:13:10 AM UTC 24 Aug 29 12:13:12 AM UTC 24 38625124 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2535948364 Aug 29 12:13:10 AM UTC 24 Aug 29 12:13:12 AM UTC 24 52133677 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3072792443 Aug 29 12:12:38 AM UTC 24 Aug 29 12:13:13 AM UTC 24 3326157276 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.2797925415 Aug 29 12:13:10 AM UTC 24 Aug 29 12:13:15 AM UTC 24 260309395 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.3407118353 Aug 29 12:13:01 AM UTC 24 Aug 29 12:13:15 AM UTC 24 436694675 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.3332663083 Aug 29 12:13:05 AM UTC 24 Aug 29 12:13:16 AM UTC 24 203216441 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.3379426006 Aug 29 12:13:02 AM UTC 24 Aug 29 12:13:16 AM UTC 24 2533544757 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2345354525 Aug 29 12:12:47 AM UTC 24 Aug 29 12:13:16 AM UTC 24 254192114 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.4117290286 Aug 29 12:13:12 AM UTC 24 Aug 29 12:13:17 AM UTC 24 370656831 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.2241828710 Aug 29 12:13:13 AM UTC 24 Aug 29 12:13:17 AM UTC 24 168503373 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.1361485325 Aug 29 12:13:05 AM UTC 24 Aug 29 12:13:18 AM UTC 24 175911661 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.417154656 Aug 29 12:13:15 AM UTC 24 Aug 29 12:13:18 AM UTC 24 26615411 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.1047233120 Aug 29 12:12:56 AM UTC 24 Aug 29 12:13:19 AM UTC 24 301686867 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.4230428556 Aug 29 12:13:18 AM UTC 24 Aug 29 12:13:21 AM UTC 24 58117188 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.1384844649 Aug 29 12:13:04 AM UTC 24 Aug 29 12:13:22 AM UTC 24 512695882 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.3182757689 Aug 29 12:13:18 AM UTC 24 Aug 29 12:13:22 AM UTC 24 166198556 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2024571805 Aug 29 12:13:16 AM UTC 24 Aug 29 12:13:23 AM UTC 24 197766324 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.2190399421 Aug 29 12:13:24 AM UTC 24 Aug 29 12:13:27 AM UTC 24 84228687 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2299530739 Aug 29 12:13:25 AM UTC 24 Aug 29 12:13:28 AM UTC 24 14680837 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.2981222464 Aug 29 12:12:51 AM UTC 24 Aug 29 12:13:28 AM UTC 24 305750148 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.587734665 Aug 29 12:13:25 AM UTC 24 Aug 29 12:13:29 AM UTC 24 218069465 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.990483218 Aug 29 12:13:14 AM UTC 24 Aug 29 12:13:29 AM UTC 24 796243915 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.450976878 Aug 29 12:12:29 AM UTC 24 Aug 29 12:13:29 AM UTC 24 1420356551 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.3816663533 Aug 29 12:13:13 AM UTC 24 Aug 29 12:13:30 AM UTC 24 478808158 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.541336648 Aug 29 12:13:08 AM UTC 24 Aug 29 12:13:56 AM UTC 24 1055521257 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.3606182348 Aug 29 12:13:13 AM UTC 24 Aug 29 12:13:30 AM UTC 24 461994108 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.1947078948 Aug 29 12:13:28 AM UTC 24 Aug 29 12:13:32 AM UTC 24 37466450 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.1027696782 Aug 29 12:13:31 AM UTC 24 Aug 29 12:13:33 AM UTC 24 13412527 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.1802424580 Aug 29 12:13:22 AM UTC 24 Aug 29 12:13:35 AM UTC 24 204889092 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2851143418 Aug 29 12:13:02 AM UTC 24 Aug 29 12:13:39 AM UTC 24 1903465813 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1083647088 Aug 29 12:13:19 AM UTC 24 Aug 29 12:13:39 AM UTC 24 1345375420 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.188800088 Aug 29 12:13:20 AM UTC 24 Aug 29 12:13:40 AM UTC 24 1558994810 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.686971375 Aug 29 12:13:01 AM UTC 24 Aug 29 12:13:40 AM UTC 24 5540518930 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.2577711184 Aug 29 12:13:27 AM UTC 24 Aug 29 12:13:41 AM UTC 24 61497002 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.2796147664 Aug 29 12:13:19 AM UTC 24 Aug 29 12:13:42 AM UTC 24 2567198138 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1604316265 Aug 29 12:13:22 AM UTC 24 Aug 29 12:13:43 AM UTC 24 574756821 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.2856661160 Aug 29 12:13:10 AM UTC 24 Aug 29 12:13:43 AM UTC 24 220270194 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1596593259 Aug 29 12:13:34 AM UTC 24 Aug 29 12:13:43 AM UTC 24 540532151 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.3536573988 Aug 29 12:12:59 AM UTC 24 Aug 29 12:13:47 AM UTC 24 1295297620 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.1666211342 Aug 29 12:13:30 AM UTC 24 Aug 29 12:13:47 AM UTC 24 284390212 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.3573182203 Aug 29 12:13:45 AM UTC 24 Aug 29 12:13:47 AM UTC 24 76645096 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.3286358767 Aug 29 12:13:18 AM UTC 24 Aug 29 12:13:48 AM UTC 24 546492771 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.3584759120 Aug 29 12:13:29 AM UTC 24 Aug 29 12:13:49 AM UTC 24 335967626 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1623611048 Aug 29 12:13:48 AM UTC 24 Aug 29 12:13:50 AM UTC 24 34446890 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.3159913866 Aug 29 12:13:48 AM UTC 24 Aug 29 12:13:52 AM UTC 24 44417568 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.1270058966 Aug 29 12:13:33 AM UTC 24 Aug 29 12:13:53 AM UTC 24 773043976 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.36707501 Aug 29 12:13:49 AM UTC 24 Aug 29 12:13:53 AM UTC 24 34107810 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.2817441082 Aug 29 12:13:39 AM UTC 24 Aug 29 12:13:54 AM UTC 24 3298331017 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2361883805 Aug 29 12:13:18 AM UTC 24 Aug 29 12:13:55 AM UTC 24 2946892451 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3933636897 Aug 29 12:13:42 AM UTC 24 Aug 29 12:13:55 AM UTC 24 662897029 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.3278696265 Aug 29 12:13:54 AM UTC 24 Aug 29 12:13:56 AM UTC 24 10568239 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.2772474507 Aug 29 12:13:42 AM UTC 24 Aug 29 12:13:57 AM UTC 24 1014162969 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1702393153 Aug 29 12:13:48 AM UTC 24 Aug 29 12:13:58 AM UTC 24 127021824 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.1070901619 Aug 29 12:13:42 AM UTC 24 Aug 29 12:13:59 AM UTC 24 440945791 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.4217935603 Aug 29 12:14:53 AM UTC 24 Aug 29 12:15:06 AM UTC 24 376574277 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.3400047681 Aug 29 12:13:56 AM UTC 24 Aug 29 12:13:59 AM UTC 24 214761632 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.911450026 Aug 29 12:13:24 AM UTC 24 Aug 29 12:14:00 AM UTC 24 207691675 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.389425098 Aug 29 12:13:25 AM UTC 24 Aug 29 12:14:01 AM UTC 24 255154017 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.560268910 Aug 29 12:14:58 AM UTC 24 Aug 29 12:15:06 AM UTC 24 328460267 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.571048316 Aug 29 12:13:31 AM UTC 24 Aug 29 12:14:02 AM UTC 24 336955956 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.4174206987 Aug 29 12:13:41 AM UTC 24 Aug 29 12:14:02 AM UTC 24 1032797347 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.1813350062 Aug 29 12:13:41 AM UTC 24 Aug 29 12:14:02 AM UTC 24 3777088751 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.3749813888 Aug 29 12:14:03 AM UTC 24 Aug 29 12:14:06 AM UTC 24 29977244 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.480465158 Aug 29 12:13:58 AM UTC 24 Aug 29 12:14:06 AM UTC 24 364378029 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.3657588531 Aug 29 12:13:55 AM UTC 24 Aug 29 12:14:06 AM UTC 24 542468796 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.1666750221 Aug 29 12:13:50 AM UTC 24 Aug 29 12:14:08 AM UTC 24 774920109 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1082655923 Aug 29 12:14:07 AM UTC 24 Aug 29 12:14:09 AM UTC 24 166451810 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.1895835350 Aug 29 12:13:53 AM UTC 24 Aug 29 12:14:11 AM UTC 24 1983189118 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.3974386955 Aug 29 12:14:09 AM UTC 24 Aug 29 12:14:12 AM UTC 24 192947798 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.3979197924 Aug 29 12:14:04 AM UTC 24 Aug 29 12:14:14 AM UTC 24 94954082 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.2741839121 Aug 29 12:13:59 AM UTC 24 Aug 29 12:14:14 AM UTC 24 486189868 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.2342401577 Aug 29 12:14:00 AM UTC 24 Aug 29 12:14:14 AM UTC 24 1049194171 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.922684747 Aug 29 12:13:45 AM UTC 24 Aug 29 12:14:16 AM UTC 24 135829135 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.3178329911 Aug 29 12:13:50 AM UTC 24 Aug 29 12:14:16 AM UTC 24 797150229 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.2989158730 Aug 29 12:14:14 AM UTC 24 Aug 29 12:14:16 AM UTC 24 21991963 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.1233492813 Aug 29 12:13:32 AM UTC 24 Aug 29 12:14:17 AM UTC 24 4155348451 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.817834351 Aug 29 12:13:58 AM UTC 24 Aug 29 12:14:18 AM UTC 24 721402094 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.3968119481 Aug 29 12:14:00 AM UTC 24 Aug 29 12:14:18 AM UTC 24 1443421436 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.1959970691 Aug 29 12:14:08 AM UTC 24 Aug 29 12:14:19 AM UTC 24 401314595 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.2123455919 Aug 29 12:13:48 AM UTC 24 Aug 29 12:14:19 AM UTC 24 2197339532 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.1532841827 Aug 29 12:14:17 AM UTC 24 Aug 29 12:14:24 AM UTC 24 237831625 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.1099082230 Aug 29 12:14:12 AM UTC 24 Aug 29 12:14:24 AM UTC 24 3065706891 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.4212044128 Aug 29 12:13:16 AM UTC 24 Aug 29 12:14:25 AM UTC 24 3852801155 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3585328295 Aug 29 12:14:13 AM UTC 24 Aug 29 12:14:25 AM UTC 24 319737136 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.78141912 Aug 29 12:14:19 AM UTC 24 Aug 29 12:14:26 AM UTC 24 854761326 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.2079003968 Aug 29 12:13:58 AM UTC 24 Aug 29 12:14:27 AM UTC 24 844186964 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.2422328443 Aug 29 12:14:26 AM UTC 24 Aug 29 12:14:29 AM UTC 24 14787892 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.480892368 Aug 29 12:14:18 AM UTC 24 Aug 29 12:14:30 AM UTC 24 1919495681 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2960262287 Aug 29 12:14:27 AM UTC 24 Aug 29 12:14:30 AM UTC 24 66287566 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.3771286403 Aug 29 12:14:21 AM UTC 24 Aug 29 12:14:32 AM UTC 24 1613493467 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2123152821 Aug 29 12:14:26 AM UTC 24 Aug 29 12:14:32 AM UTC 24 216304845 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.230002522 Aug 29 12:13:35 AM UTC 24 Aug 29 12:14:32 AM UTC 24 3491438352 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.599859218 Aug 29 12:14:15 AM UTC 24 Aug 29 12:14:33 AM UTC 24 8892755281 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.810587298 Aug 29 12:14:19 AM UTC 24 Aug 29 12:14:34 AM UTC 24 3676764169 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.907977458 Aug 29 12:14:33 AM UTC 24 Aug 29 12:14:35 AM UTC 24 30292084 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.4129540764 Aug 29 12:14:10 AM UTC 24 Aug 29 12:14:36 AM UTC 24 657067403 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.3697916987 Aug 29 12:14:31 AM UTC 24 Aug 29 12:14:36 AM UTC 24 1701592835 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.2344276337 Aug 29 12:14:24 AM UTC 24 Aug 29 12:14:37 AM UTC 24 279365576 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3633895507 Aug 29 12:14:19 AM UTC 24 Aug 29 12:14:40 AM UTC 24 749172326 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.683532026 Aug 29 12:14:30 AM UTC 24 Aug 29 12:14:42 AM UTC 24 68080198 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.3432420856 Aug 29 12:14:33 AM UTC 24 Aug 29 12:14:44 AM UTC 24 1910635415 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.3533041229 Aug 29 12:13:56 AM UTC 24 Aug 29 12:14:45 AM UTC 24 8661168173 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.3627784736 Aug 29 12:14:02 AM UTC 24 Aug 29 12:14:46 AM UTC 24 201984911 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.953729106 Aug 29 12:14:38 AM UTC 24 Aug 29 12:14:47 AM UTC 24 274530306 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.1801906749 Aug 29 12:14:31 AM UTC 24 Aug 29 12:14:48 AM UTC 24 1584221719 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.4154010460 Aug 29 12:14:33 AM UTC 24 Aug 29 12:14:49 AM UTC 24 3370257041 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.1358886385 Aug 29 12:14:07 AM UTC 24 Aug 29 12:14:49 AM UTC 24 776608886 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2116915120 Aug 29 12:13:55 AM UTC 24 Aug 29 12:14:50 AM UTC 24 7877613807 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.2987607984 Aug 29 12:14:48 AM UTC 24 Aug 29 12:14:50 AM UTC 24 60209391 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1298406413 Aug 29 12:14:34 AM UTC 24 Aug 29 12:14:50 AM UTC 24 935504994 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.2788879567 Aug 29 12:14:17 AM UTC 24 Aug 29 12:14:51 AM UTC 24 2691462630 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.610168907 Aug 29 12:12:46 AM UTC 24 Aug 29 12:14:52 AM UTC 24 22477844002 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1819525692 Aug 29 12:14:49 AM UTC 24 Aug 29 12:14:52 AM UTC 24 34822069 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.2249683215 Aug 29 12:13:43 AM UTC 24 Aug 29 12:14:53 AM UTC 24 1728228091 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.1571736176 Aug 29 12:14:38 AM UTC 24 Aug 29 12:14:53 AM UTC 24 865624017 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.1421836298 Aug 29 12:14:49 AM UTC 24 Aug 29 12:14:54 AM UTC 24 332260472 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.2715988722 Aug 29 12:14:53 AM UTC 24 Aug 29 12:14:56 AM UTC 24 22836845 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3013037494 Aug 29 12:14:37 AM UTC 24 Aug 29 12:14:56 AM UTC 24 9196210483 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.407231581 Aug 29 12:14:52 AM UTC 24 Aug 29 12:14:57 AM UTC 24 58701879 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.1058568977 Aug 29 12:14:43 AM UTC 24 Aug 29 12:14:58 AM UTC 24 577080780 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.4012745442 Aug 29 12:14:44 AM UTC 24 Aug 29 12:14:59 AM UTC 24 475746139 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2592370008 Aug 29 12:14:37 AM UTC 24 Aug 29 12:14:59 AM UTC 24 488757275 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.1061846790 Aug 29 12:14:54 AM UTC 24 Aug 29 12:14:59 AM UTC 24 147783413 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.3287593132 Aug 29 12:14:52 AM UTC 24 Aug 29 12:15:00 AM UTC 24 192399538 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1174457568 Aug 29 12:14:28 AM UTC 24 Aug 29 12:15:00 AM UTC 24 143758262 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.1717414397 Aug 29 12:14:56 AM UTC 24 Aug 29 12:15:03 AM UTC 24 153305307 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.1787431438 Aug 29 12:14:47 AM UTC 24 Aug 29 12:15:05 AM UTC 24 381866010 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.2185652864 Aug 29 12:14:53 AM UTC 24 Aug 29 12:15:05 AM UTC 24 1023646036 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.3978005220 Aug 29 12:15:05 AM UTC 24 Aug 29 12:15:07 AM UTC 24 275683504 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.480152952 Aug 29 12:14:52 AM UTC 24 Aug 29 12:15:08 AM UTC 24 3511536265 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.32044828 Aug 29 12:15:06 AM UTC 24 Aug 29 12:15:08 AM UTC 24 50549070 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.2684305494 Aug 29 12:15:06 AM UTC 24 Aug 29 12:15:09 AM UTC 24 42278347 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.1688664360 Aug 29 12:14:59 AM UTC 24 Aug 29 12:15:09 AM UTC 24 353737324 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3454183827 Aug 29 12:14:41 AM UTC 24 Aug 29 12:15:11 AM UTC 24 2675675646 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3290450479 Aug 29 12:13:07 AM UTC 24 Aug 29 12:16:07 AM UTC 24 50361757694 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.131339927 Aug 29 12:14:55 AM UTC 24 Aug 29 12:15:11 AM UTC 24 1889945992 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.1432839088 Aug 29 12:15:08 AM UTC 24 Aug 29 12:15:13 AM UTC 24 76286643 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.722321332 Aug 29 12:15:11 AM UTC 24 Aug 29 12:15:13 AM UTC 24 22871952 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.4194407951 Aug 29 12:13:23 AM UTC 24 Aug 29 12:15:14 AM UTC 24 14033285829 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3321735076 Aug 29 12:14:50 AM UTC 24 Aug 29 12:15:16 AM UTC 24 1005409770 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.1770389117 Aug 29 12:15:00 AM UTC 24 Aug 29 12:15:16 AM UTC 24 1157516692 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.404319057 Aug 29 12:15:00 AM UTC 24 Aug 29 12:15:18 AM UTC 24 484695760 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.3331639202 Aug 29 12:15:00 AM UTC 24 Aug 29 12:15:19 AM UTC 24 2824454826 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.3318119665 Aug 29 12:15:09 AM UTC 24 Aug 29 12:15:19 AM UTC 24 884513932 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.1815685486 Aug 29 12:15:15 AM UTC 24 Aug 29 12:15:21 AM UTC 24 1585556628 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.46199024 Aug 29 12:15:16 AM UTC 24 Aug 29 12:15:21 AM UTC 24 124380790 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.286053750 Aug 29 12:15:09 AM UTC 24 Aug 29 12:15:22 AM UTC 24 3686986673 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.1839784171 Aug 29 12:15:09 AM UTC 24 Aug 29 12:15:23 AM UTC 24 648365090 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3746452872 Aug 29 12:12:43 AM UTC 24 Aug 29 12:15:24 AM UTC 24 15614036190 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.1184790972 Aug 29 12:14:17 AM UTC 24 Aug 29 12:15:24 AM UTC 24 1627241859 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.1000547084 Aug 29 12:14:16 AM UTC 24 Aug 29 12:15:24 AM UTC 24 1494426765 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.4192876342 Aug 29 12:15:22 AM UTC 24 Aug 29 12:15:24 AM UTC 24 17812325 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.2441369535 Aug 29 12:15:14 AM UTC 24 Aug 29 12:15:24 AM UTC 24 184130837 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.882241419 Aug 29 12:15:07 AM UTC 24 Aug 29 12:15:24 AM UTC 24 566196709 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.2897391639 Aug 29 12:15:25 AM UTC 24 Aug 29 12:16:01 AM UTC 24 855721012 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.606314640 Aug 29 12:15:55 AM UTC 24 Aug 29 12:16:07 AM UTC 24 744852957 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.68968427 Aug 29 12:15:25 AM UTC 24 Aug 29 12:15:27 AM UTC 24 16584302 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.2138048417 Aug 29 12:15:23 AM UTC 24 Aug 29 12:15:27 AM UTC 24 84269835 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.4226119371 Aug 29 12:15:19 AM UTC 24 Aug 29 12:15:27 AM UTC 24 390950458 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.2695685364 Aug 29 12:15:25 AM UTC 24 Aug 29 12:15:30 AM UTC 24 142573117 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.400173458 Aug 29 12:15:28 AM UTC 24 Aug 29 12:15:30 AM UTC 24 13549404 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.1419848400 Aug 29 12:15:12 AM UTC 24 Aug 29 12:15:31 AM UTC 24 605950034 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.3919905284 Aug 29 12:15:28 AM UTC 24 Aug 29 12:15:32 AM UTC 24 499284889 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.2620657403 Aug 29 12:15:20 AM UTC 24 Aug 29 12:15:33 AM UTC 24 1083515146 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.3590345761 Aug 29 12:15:56 AM UTC 24 Aug 29 12:16:05 AM UTC 24 1028244865 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.463146714 Aug 29 12:15:54 AM UTC 24 Aug 29 12:16:07 AM UTC 24 289766616 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.2158455252 Aug 29 12:15:12 AM UTC 24 Aug 29 12:15:35 AM UTC 24 2113155611 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.2870600818 Aug 29 12:15:28 AM UTC 24 Aug 29 12:15:37 AM UTC 24 560349683 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1522867431 Aug 29 12:15:00 AM UTC 24 Aug 29 12:15:37 AM UTC 24 1300490793 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.2986852171 Aug 29 12:15:25 AM UTC 24 Aug 29 12:15:37 AM UTC 24 112234030 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.277229550 Aug 29 12:14:37 AM UTC 24 Aug 29 12:15:37 AM UTC 24 5389127613 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.1589586896 Aug 29 12:15:20 AM UTC 24 Aug 29 12:15:37 AM UTC 24 286249181 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3802820580 Aug 29 12:15:31 AM UTC 24 Aug 29 12:15:38 AM UTC 24 209718255 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.337751000 Aug 29 12:13:56 AM UTC 24 Aug 29 12:15:38 AM UTC 24 3179691560 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.845565485 Aug 29 12:15:25 AM UTC 24 Aug 29 12:15:39 AM UTC 24 376962077 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.828251695 Aug 29 12:15:28 AM UTC 24 Aug 29 12:15:40 AM UTC 24 438295426 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1258406785 Aug 29 12:15:17 AM UTC 24 Aug 29 12:15:41 AM UTC 24 1264507472 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.473969323 Aug 29 12:15:38 AM UTC 24 Aug 29 12:15:41 AM UTC 24 33153329 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.1286501722 Aug 29 12:15:38 AM UTC 24 Aug 29 12:15:41 AM UTC 24 47278003 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.3420519292 Aug 29 12:15:25 AM UTC 24 Aug 29 12:15:43 AM UTC 24 1334325747 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2361309215 Aug 29 12:15:38 AM UTC 24 Aug 29 12:15:43 AM UTC 24 432612867 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.474148018 Aug 29 12:15:41 AM UTC 24 Aug 29 12:15:43 AM UTC 24 16845758 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.133995052 Aug 29 12:13:24 AM UTC 24 Aug 29 12:15:44 AM UTC 24 6677244537 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.1863326423 Aug 29 12:15:07 AM UTC 24 Aug 29 12:15:46 AM UTC 24 659462019 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1788736942 Aug 29 12:15:34 AM UTC 24 Aug 29 12:15:48 AM UTC 24 1427806087 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.3987574647 Aug 29 12:15:37 AM UTC 24 Aug 29 12:15:49 AM UTC 24 1995342817 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.1975518843 Aug 29 12:15:40 AM UTC 24 Aug 29 12:15:49 AM UTC 24 288646051 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.1833485982 Aug 29 12:15:14 AM UTC 24 Aug 29 12:15:50 AM UTC 24 7392861861 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.2453267607 Aug 29 12:14:57 AM UTC 24 Aug 29 12:15:51 AM UTC 24 12429510928 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.1724344660 Aug 29 12:15:45 AM UTC 24 Aug 29 12:15:51 AM UTC 24 577114623 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.2127506089 Aug 29 12:15:28 AM UTC 24 Aug 29 12:15:51 AM UTC 24 2305182763 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3900334026 Aug 29 12:15:42 AM UTC 24 Aug 29 12:15:52 AM UTC 24 370900012 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2333592698 Aug 29 12:15:34 AM UTC 24 Aug 29 12:15:53 AM UTC 24 816667490 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.74488005 Aug 29 12:16:06 AM UTC 24 Aug 29 12:16:09 AM UTC 24 20886098 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.628236018 Aug 29 12:13:06 AM UTC 24 Aug 29 12:15:53 AM UTC 24 14009922059 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.1294657382 Aug 29 12:15:45 AM UTC 24 Aug 29 12:15:54 AM UTC 24 1066821319 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.1688142213 Aug 29 12:15:52 AM UTC 24 Aug 29 12:15:54 AM UTC 24 24945422 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1945086228 Aug 29 12:15:53 AM UTC 24 Aug 29 12:15:55 AM UTC 24 11733071 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.3067372106 Aug 29 12:15:32 AM UTC 24 Aug 29 12:15:56 AM UTC 24 6178877614 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.1557714836 Aug 29 12:15:52 AM UTC 24 Aug 29 12:15:56 AM UTC 24 187027507 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.210685002 Aug 29 12:15:41 AM UTC 24 Aug 29 12:15:57 AM UTC 24 215523111 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.1528942129 Aug 29 12:15:47 AM UTC 24 Aug 29 12:15:58 AM UTC 24 899526693 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.3308819292 Aug 29 12:15:49 AM UTC 24 Aug 29 12:15:59 AM UTC 24 973050362 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.3358268195 Aug 29 12:15:42 AM UTC 24 Aug 29 12:15:59 AM UTC 24 536357672 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.477219675 Aug 29 12:15:54 AM UTC 24 Aug 29 12:15:59 AM UTC 24 93400742 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.1888591593 Aug 29 12:15:37 AM UTC 24 Aug 29 12:16:01 AM UTC 24 2277468216 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.2679004723 Aug 29 12:15:39 AM UTC 24 Aug 29 12:16:05 AM UTC 24 847822939 ps
T346 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.625596872 Aug 29 12:16:06 AM UTC 24 Aug 29 12:16:08 AM UTC 24 14165542 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.3061699675 Aug 29 12:16:00 AM UTC 24 Aug 29 12:16:09 AM UTC 24 401975717 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3425303601 Aug 29 12:15:50 AM UTC 24 Aug 29 12:16:09 AM UTC 24 339162116 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1950905061 Aug 29 12:16:07 AM UTC 24 Aug 29 12:16:09 AM UTC 24 29094305 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.779624313 Aug 29 12:15:43 AM UTC 24 Aug 29 12:16:10 AM UTC 24 928584891 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.969038531 Aug 29 12:15:38 AM UTC 24 Aug 29 12:16:10 AM UTC 24 4718202338 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.900170109 Aug 29 12:14:54 AM UTC 24 Aug 29 12:16:11 AM UTC 24 1468316424 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.149989456 Aug 29 12:16:00 AM UTC 24 Aug 29 12:16:12 AM UTC 24 380830622 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.4110676057 Aug 29 12:16:00 AM UTC 24 Aug 29 12:16:12 AM UTC 24 448121147 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.1630476855 Aug 29 12:16:10 AM UTC 24 Aug 29 12:16:12 AM UTC 24 129064829 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.423583672 Aug 29 12:15:55 AM UTC 24 Aug 29 12:16:12 AM UTC 24 2005823416 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.383776327 Aug 29 12:15:58 AM UTC 24 Aug 29 12:16:15 AM UTC 24 607337962 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.3250956545 Aug 29 12:16:08 AM UTC 24 Aug 29 12:16:17 AM UTC 24 183669346 ps
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