Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64259315

1

T1

1459

T2

713

T3

2167

auto[1]

1098974

1

T4

792

T5

297

T14

10178

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64242023

1

T1

1459

T2

713

T3

2167

auto[1]

1116266

1

T4

891

T5

594

T14

10588

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	5405068	1			T1	87		T2	85		T3	570
auto[IdleSt]	16046940	1			T1	16		T2	628		T3	556
auto[ClkMuxSt]	28497	1			T1	1		T3	6		T4	17
auto[CntIncrSt]	28291	1			T1	1		T3	6		T4	17
auto[CntProgSt]	1481009	1			T1	323		T3	92		T4	696
auto[TransCheckSt]	22267	1			T1	1		T3	6		T5	4
auto[TokenHashSt]	21285924	1			T1	162		T3	139		T5	442
auto[FlashRmaSt]	27506	1			T3	30		T5	4		T13	49
auto[TokenCheck0St]	9773	1			T3	6		T5	4		T13	9
auto[TokenCheck1St]	6995	1			T3	6		T5	4		T13	9
auto[TransProgSt]	332151	1			T3	118		T5	78		T13	18
auto[PostTransSt]	8852805	1			T1	868		T3	598		T4	1232
auto[ScrapSt]	185527	1			T3	34		T13	1141		T14	16
auto[EscalateSt]	4629613	1			T4	2249		T5	1544		T14	15015
auto[InvalidSt]	7014526	1			T5	651		T22	36		T26	1053

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1397	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	7014526	1			T5	651		T22	36		T26	1053
EscalateSt	4629613	1			T4	2249		T5	1544		T14	15015
ScrapSt	185527	1			T3	34		T13	1141		T14	16
PostTransSt	8852805	1			T1	868		T3	598		T4	1232
TransProgSt	332151	1			T3	118		T5	78		T13	18
TokenCheck1St	6995	1			T3	6		T5	4		T13	9
TokenCheck0St	9773	1			T3	6		T5	4		T13	9
FlashRmaSt	27506	1			T3	30		T5	4		T13	49
TokenHashSt	21285924	1			T1	162		T3	139		T5	442
TransCheckSt	22267	1			T1	1		T3	6		T5	4
CntProgSt	1481009	1			T1	323		T3	92		T4	696
CntIncrSt	28291	1			T1	1		T3	6		T4	17
ClkMuxSt	28497	1			T1	1		T3	6		T4	17
IdleSt	16046940	1			T1	16		T2	628		T3	556
ResetSt	5405068	1			T1	87		T2	85		T3	570
arcs[ResetSt=>IdleSt]	41751	1			T1	1		T2	1		T3	7
arcs[IdleSt=>ScrapSt]	228	1			T3	1		T13	1		T14	4
arcs[IdleSt=>ClkMuxSt]	28325	1			T1	1		T3	6		T4	17
arcs[ClkMuxSt=>CntIncrSt]	28291	1			T1	1		T3	6		T4	17
arcs[CntIncrSt=>PostTransSt]	1247	1			T16	5		T25	3		T27	13
arcs[CntIncrSt=>CntProgSt]	26975	1			T1	1		T3	6		T4	17
arcs[CntProgSt=>PostTransSt]	3653	1			T4	17		T16	7		T28	5
arcs[CntProgSt=>TransCheckSt]	22267	1			T1	1		T3	6		T5	4
arcs[TransCheckSt=>PostTransSt]	3124	1			T16	5		T23	47		T25	9
arcs[TransCheckSt=>TokenHashSt]	19034	1			T1	1		T3	6		T5	4
arcs[TokenHashSt=>PostTransSt]	8526	1			T1	1		T16	25		T17	1
arcs[TokenHashSt=>FlashRmaSt]	9814	1			T3	6		T5	4		T13	9
arcs[FlashRmaSt=>TokenCheck0St]	9773	1			T3	6		T5	4		T13	9
arcs[TokenCheck0St=>PostTransSt]	2724	1			T16	5		T23	23		T26	18
arcs[TokenCheck0St=>TokenCheck1St]	6995	1			T3	6		T5	4		T13	9
arcs[TokenCheck1St=>PostTransSt]	580	1			T16	3		T23	6		T26	1
arcs[TransProgSt=>PostTransSt]	5602	1			T3	6		T5	4		T13	9
arcs[IdleSt=>EscalateSt]	187	1			T14	4		T63	8		T64	4
arcs[ClkMuxSt=>EscalateSt]	34	1			T14	1		T63	3		T64	3
arcs[CntIncrSt=>EscalateSt]	69	1			T14	1		T45	2		T65	1
arcs[CntProgSt=>EscalateSt]	1055	1			T14	30		T45	38		T65	6
arcs[TransCheckSt=>EscalateSt]	109	1			T65	5		T63	8		T64	7
arcs[TokenHashSt=>EscalateSt]	694	1			T14	7		T45	7		T65	19
arcs[FlashRmaSt=>EscalateSt]	41	1			T65	2		T63	3		T66	1
arcs[TokenCheck0St=>EscalateSt]	54	1			T45	2		T65	1		T63	1
arcs[TokenCheck1St=>EscalateSt]	28	1			T14	2		T45	1		T66	1
arcs[TransProgSt=>EscalateSt]	785	1			T14	19		T45	15		T65	6
arcs[PostTransSt=>EscalateSt]	3977	1			T4	17		T14	5		T16	7
arcs[InvalidSt=>EscalateSt]	9622	1			T5	9		T26	14		T49	6

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5404901	1			T1	87		T2	85		T3	570
auto[0]	auto[IdleSt]	16046820	1			T1	16		T2	628		T3	556
auto[0]	auto[ClkMuxSt]	28475	1			T1	1		T3	6		T4	17
auto[0]	auto[CntIncrSt]	28249	1			T1	1		T3	6		T4	17
auto[0]	auto[CntProgSt]	1480304	1			T1	323		T3	92		T4	696
auto[0]	auto[TransCheckSt]	22198	1			T1	1		T3	6		T5	4
auto[0]	auto[TokenHashSt]	21285469	1			T1	162		T3	139		T5	442
auto[0]	auto[FlashRmaSt]	27478	1			T3	30		T5	4		T13	49
auto[0]	auto[TokenCheck0St]	9738	1			T3	6		T5	4		T13	9
auto[0]	auto[TokenCheck1St]	6973	1			T3	6		T5	4		T13	9
auto[0]	auto[TransProgSt]	331633	1			T3	118		T5	78		T13	18
auto[0]	auto[PostTransSt]	8850786	1			T1	868		T3	598		T4	1224
auto[0]	auto[ScrapSt]	185479	1			T3	34		T13	1141		T14	14
auto[0]	auto[EscalateSt]	3539647	1			T4	1465		T5	1250		T14	4890
auto[0]	auto[InvalidSt]	7009768	1			T5	648		T22	36		T26	1045
auto[1]	auto[ResetSt]	167	1			T14	7		T45	2		T65	3
auto[1]	auto[IdleSt]	120	1			T14	1		T63	6		T64	2
auto[1]	auto[ClkMuxSt]	22	1			T14	1		T64	3		T234	1
auto[1]	auto[CntIncrSt]	42	1			T14	1		T45	2		T65	1
auto[1]	auto[CntProgSt]	705	1			T14	22		T45	25		T65	3
auto[1]	auto[TransCheckSt]	69	1			T65	2		T63	6		T64	3
auto[1]	auto[TokenHashSt]	455	1			T14	3		T45	4		T65	10
auto[1]	auto[FlashRmaSt]	28	1			T65	2		T63	2		T234	1
auto[1]	auto[TokenCheck0St]	35	1			T45	1		T65	1		T63	1
auto[1]	auto[TokenCheck1St]	22	1			T14	1		T45	1		T66	1
auto[1]	auto[TransProgSt]	518	1			T14	10		T45	10		T65	6
auto[1]	auto[PostTransSt]	2019	1			T4	8		T14	5		T16	2
auto[1]	auto[ScrapSt]	48	1			T14	2		T63	2		T67	2
auto[1]	auto[EscalateSt]	1089966	1			T4	784		T5	294		T14	10125
auto[1]	auto[InvalidSt]	4758	1			T5	3		T26	8		T49	4

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	5404910	1			T1	87		T2	85		T3	570
auto[0]	auto[IdleSt]	16046815	1			T1	16		T2	628		T3	556
auto[0]	auto[ClkMuxSt]	28477	1			T1	1		T3	6		T4	17
auto[0]	auto[CntIncrSt]	28241	1			T1	1		T3	6		T4	17
auto[0]	auto[CntProgSt]	1480305	1			T1	323		T3	92		T4	696
auto[0]	auto[TransCheckSt]	22196	1			T1	1		T3	6		T5	4
auto[0]	auto[TokenHashSt]	21285466	1			T1	162		T3	139		T5	442
auto[0]	auto[FlashRmaSt]	27478	1			T3	30		T5	4		T13	49
auto[0]	auto[TokenCheck0St]	9738	1			T3	6		T5	4		T13	9
auto[0]	auto[TokenCheck1St]	6976	1			T3	6		T5	4		T13	9
auto[0]	auto[TransProgSt]	331620	1			T3	118		T5	78		T13	18
auto[0]	auto[PostTransSt]	8850738	1			T1	868		T3	598		T4	1223
auto[0]	auto[ScrapSt]	185483	1			T3	34		T13	1141		T14	14
auto[0]	auto[EscalateSt]	3522521	1			T4	1367		T5	956		T14	4483
auto[0]	auto[InvalidSt]	7009662	1			T5	645		T22	36		T26	1047
auto[1]	auto[ResetSt]	158	1			T14	6		T45	2		T65	1
auto[1]	auto[IdleSt]	125	1			T14	3		T63	6		T64	3
auto[1]	auto[ClkMuxSt]	20	1			T63	3		T64	2		T234	1
auto[1]	auto[CntIncrSt]	50	1			T14	1		T65	1		T63	1
auto[1]	auto[CntProgSt]	704	1			T14	18		T45	26		T65	5
auto[1]	auto[TransCheckSt]	71	1			T65	5		T63	3		T64	5
auto[1]	auto[TokenHashSt]	458	1			T14	6		T45	5		T65	13
auto[1]	auto[FlashRmaSt]	28	1			T65	2		T63	2		T66	1
auto[1]	auto[TokenCheck0St]	35	1			T45	1		T63	1		T235	2
auto[1]	auto[TokenCheck1St]	19	1			T14	2		T235	1		T236	1
auto[1]	auto[TransProgSt]	531	1			T14	14		T45	11		T65	4
auto[1]	auto[PostTransSt]	2067	1			T4	9		T14	4		T16	5
auto[1]	auto[ScrapSt]	44	1			T14	2		T63	2		T237	2
auto[1]	auto[EscalateSt]	1107092	1			T4	882		T5	588		T14	10532
auto[1]	auto[InvalidSt]	4864	1			T5	6		T26	6		T49	2